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bellard54936002003-05-13 00:25:15 +00001/*
bellardfd6ce8f2003-05-14 19:00:11 +00002 * virtual page mapping and translated block handling
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard54936002003-05-13 00:25:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
bellard67b915a2004-03-31 23:37:16 +000020#include "config.h"
bellardd5a8f072004-09-29 21:15:28 +000021#ifdef _WIN32
ths4fddf622007-12-17 04:42:29 +000022#define WIN32_LEAN_AND_MEAN
bellardd5a8f072004-09-29 21:15:28 +000023#include <windows.h>
24#else
bellarda98d49b2004-11-14 16:22:05 +000025#include <sys/types.h>
bellardd5a8f072004-09-29 21:15:28 +000026#include <sys/mman.h>
27#endif
bellard54936002003-05-13 00:25:15 +000028#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <errno.h>
33#include <unistd.h>
34#include <inttypes.h>
35
bellard6180a182003-09-30 21:04:53 +000036#include "cpu.h"
37#include "exec-all.h"
aurel32ca10f862008-04-11 21:35:42 +000038#include "qemu-common.h"
pbrook53a59602006-03-25 19:31:22 +000039#if defined(CONFIG_USER_ONLY)
40#include <qemu.h>
41#endif
bellard54936002003-05-13 00:25:15 +000042
bellardfd6ce8f2003-05-14 19:00:11 +000043//#define DEBUG_TB_INVALIDATE
bellard66e85a22003-06-24 13:28:12 +000044//#define DEBUG_FLUSH
bellard9fa3e852004-01-04 18:06:42 +000045//#define DEBUG_TLB
pbrook67d3b952006-12-18 05:03:52 +000046//#define DEBUG_UNASSIGNED
bellardfd6ce8f2003-05-14 19:00:11 +000047
48/* make various TB consistency checks */
ths5fafdf22007-09-16 21:08:06 +000049//#define DEBUG_TB_CHECK
50//#define DEBUG_TLB_CHECK
bellardfd6ce8f2003-05-14 19:00:11 +000051
ths1196be32007-03-17 15:17:58 +000052//#define DEBUG_IOPORT
blueswir1db7b5422007-05-26 17:36:03 +000053//#define DEBUG_SUBPAGE
ths1196be32007-03-17 15:17:58 +000054
pbrook99773bd2006-04-16 15:14:59 +000055#if !defined(CONFIG_USER_ONLY)
56/* TB consistency checks only implemented for usermode emulation. */
57#undef DEBUG_TB_CHECK
58#endif
59
bellardfd6ce8f2003-05-14 19:00:11 +000060/* threshold to flush the translated code buffer */
blueswir1d07bde82007-12-11 19:35:45 +000061#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - code_gen_max_block_size())
bellardfd6ce8f2003-05-14 19:00:11 +000062
bellard9fa3e852004-01-04 18:06:42 +000063#define SMC_BITMAP_USE_THRESHOLD 10
64
65#define MMAP_AREA_START 0x00000000
66#define MMAP_AREA_END 0xa8000000
bellardfd6ce8f2003-05-14 19:00:11 +000067
bellard108c49b2005-07-24 12:55:09 +000068#if defined(TARGET_SPARC64)
69#define TARGET_PHYS_ADDR_SPACE_BITS 41
blueswir15dcb6b92007-05-19 12:58:30 +000070#elif defined(TARGET_SPARC)
71#define TARGET_PHYS_ADDR_SPACE_BITS 36
j_mayerbedb69e2007-04-05 20:08:21 +000072#elif defined(TARGET_ALPHA)
73#define TARGET_PHYS_ADDR_SPACE_BITS 42
74#define TARGET_VIRT_ADDR_SPACE_BITS 42
bellard108c49b2005-07-24 12:55:09 +000075#elif defined(TARGET_PPC64)
76#define TARGET_PHYS_ADDR_SPACE_BITS 42
aurel3200f82b82008-04-27 21:12:55 +000077#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
78#define TARGET_PHYS_ADDR_SPACE_BITS 42
79#elif defined(TARGET_I386) && !defined(USE_KQEMU)
80#define TARGET_PHYS_ADDR_SPACE_BITS 36
bellard108c49b2005-07-24 12:55:09 +000081#else
82/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
83#define TARGET_PHYS_ADDR_SPACE_BITS 32
84#endif
85
bellardfd6ce8f2003-05-14 19:00:11 +000086TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
bellard9fa3e852004-01-04 18:06:42 +000087TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
bellardfd6ce8f2003-05-14 19:00:11 +000088int nb_tbs;
bellardeb51d102003-05-14 21:51:13 +000089/* any access to the tbs or the page table must use this lock */
90spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
bellardfd6ce8f2003-05-14 19:00:11 +000091
bellardb8076a72005-04-07 22:20:31 +000092uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));
bellardfd6ce8f2003-05-14 19:00:11 +000093uint8_t *code_gen_ptr;
94
aurel3200f82b82008-04-27 21:12:55 +000095ram_addr_t phys_ram_size;
bellard9fa3e852004-01-04 18:06:42 +000096int phys_ram_fd;
97uint8_t *phys_ram_base;
bellard1ccde1c2004-02-06 19:46:14 +000098uint8_t *phys_ram_dirty;
bellarde9a1ab12007-02-08 23:08:38 +000099static ram_addr_t phys_ram_alloc_offset = 0;
bellard9fa3e852004-01-04 18:06:42 +0000100
bellard6a00d602005-11-21 23:25:50 +0000101CPUState *first_cpu;
102/* current CPU in the current thread. It is only valid inside
103 cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000104CPUState *cpu_single_env;
bellard6a00d602005-11-21 23:25:50 +0000105
bellard54936002003-05-13 00:25:15 +0000106typedef struct PageDesc {
bellard92e873b2004-05-21 14:52:29 +0000107 /* list of TBs intersecting this ram page */
bellardfd6ce8f2003-05-14 19:00:11 +0000108 TranslationBlock *first_tb;
bellard9fa3e852004-01-04 18:06:42 +0000109 /* in order to optimize self modifying code, we count the number
110 of lookups we do to a given page to use a bitmap */
111 unsigned int code_write_count;
112 uint8_t *code_bitmap;
113#if defined(CONFIG_USER_ONLY)
114 unsigned long flags;
115#endif
bellard54936002003-05-13 00:25:15 +0000116} PageDesc;
117
bellard92e873b2004-05-21 14:52:29 +0000118typedef struct PhysPageDesc {
119 /* offset in host memory of the page + io_index in the low 12 bits */
aurel3200f82b82008-04-27 21:12:55 +0000120 ram_addr_t phys_offset;
bellard92e873b2004-05-21 14:52:29 +0000121} PhysPageDesc;
122
bellard54936002003-05-13 00:25:15 +0000123#define L2_BITS 10
j_mayerbedb69e2007-04-05 20:08:21 +0000124#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
125/* XXX: this is a temporary hack for alpha target.
126 * In the future, this is to be replaced by a multi-level table
127 * to actually be able to handle the complete 64 bits address space.
128 */
129#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
130#else
aurel3203875442008-04-22 20:45:18 +0000131#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
j_mayerbedb69e2007-04-05 20:08:21 +0000132#endif
bellard54936002003-05-13 00:25:15 +0000133
134#define L1_SIZE (1 << L1_BITS)
135#define L2_SIZE (1 << L2_BITS)
136
bellard33417e72003-08-10 21:47:01 +0000137static void io_mem_init(void);
bellardfd6ce8f2003-05-14 19:00:11 +0000138
bellard83fb7ad2004-07-05 21:25:26 +0000139unsigned long qemu_real_host_page_size;
140unsigned long qemu_host_page_bits;
141unsigned long qemu_host_page_size;
142unsigned long qemu_host_page_mask;
bellard54936002003-05-13 00:25:15 +0000143
bellard92e873b2004-05-21 14:52:29 +0000144/* XXX: for system emulation, it could just be an array */
bellard54936002003-05-13 00:25:15 +0000145static PageDesc *l1_map[L1_SIZE];
bellard0a962c02005-02-10 22:00:27 +0000146PhysPageDesc **l1_phys_map;
bellard54936002003-05-13 00:25:15 +0000147
bellard33417e72003-08-10 21:47:01 +0000148/* io memory support */
bellard33417e72003-08-10 21:47:01 +0000149CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
150CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000151void *io_mem_opaque[IO_MEM_NB_ENTRIES];
bellard33417e72003-08-10 21:47:01 +0000152static int io_mem_nb;
pbrook6658ffb2007-03-16 23:58:11 +0000153#if defined(CONFIG_SOFTMMU)
154static int io_mem_watch;
155#endif
bellard33417e72003-08-10 21:47:01 +0000156
bellard34865132003-10-05 14:28:56 +0000157/* log support */
158char *logfilename = "/tmp/qemu.log";
159FILE *logfile;
160int loglevel;
pbrooke735b912007-06-30 13:53:24 +0000161static int log_append = 0;
bellard34865132003-10-05 14:28:56 +0000162
bellarde3db7222005-01-26 22:00:47 +0000163/* statistics */
164static int tlb_flush_count;
165static int tb_flush_count;
166static int tb_phys_invalidate_count;
167
blueswir1db7b5422007-05-26 17:36:03 +0000168#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
169typedef struct subpage_t {
170 target_phys_addr_t base;
blueswir13ee89922008-01-02 19:45:26 +0000171 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
172 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
173 void *opaque[TARGET_PAGE_SIZE][2][4];
blueswir1db7b5422007-05-26 17:36:03 +0000174} subpage_t;
175
bellardb346ff42003-06-15 20:05:50 +0000176static void page_init(void)
bellard54936002003-05-13 00:25:15 +0000177{
bellard83fb7ad2004-07-05 21:25:26 +0000178 /* NOTE: we can always suppose that qemu_host_page_size >=
bellard54936002003-05-13 00:25:15 +0000179 TARGET_PAGE_SIZE */
bellard67b915a2004-03-31 23:37:16 +0000180#ifdef _WIN32
bellardd5a8f072004-09-29 21:15:28 +0000181 {
182 SYSTEM_INFO system_info;
183 DWORD old_protect;
ths3b46e622007-09-17 08:09:54 +0000184
bellardd5a8f072004-09-29 21:15:28 +0000185 GetSystemInfo(&system_info);
186 qemu_real_host_page_size = system_info.dwPageSize;
ths3b46e622007-09-17 08:09:54 +0000187
bellardd5a8f072004-09-29 21:15:28 +0000188 VirtualProtect(code_gen_buffer, sizeof(code_gen_buffer),
189 PAGE_EXECUTE_READWRITE, &old_protect);
190 }
bellard67b915a2004-03-31 23:37:16 +0000191#else
bellard83fb7ad2004-07-05 21:25:26 +0000192 qemu_real_host_page_size = getpagesize();
bellardd5a8f072004-09-29 21:15:28 +0000193 {
194 unsigned long start, end;
195
196 start = (unsigned long)code_gen_buffer;
197 start &= ~(qemu_real_host_page_size - 1);
ths3b46e622007-09-17 08:09:54 +0000198
bellardd5a8f072004-09-29 21:15:28 +0000199 end = (unsigned long)code_gen_buffer + sizeof(code_gen_buffer);
200 end += qemu_real_host_page_size - 1;
201 end &= ~(qemu_real_host_page_size - 1);
ths3b46e622007-09-17 08:09:54 +0000202
ths5fafdf22007-09-16 21:08:06 +0000203 mprotect((void *)start, end - start,
bellardd5a8f072004-09-29 21:15:28 +0000204 PROT_READ | PROT_WRITE | PROT_EXEC);
205 }
bellard67b915a2004-03-31 23:37:16 +0000206#endif
bellardd5a8f072004-09-29 21:15:28 +0000207
bellard83fb7ad2004-07-05 21:25:26 +0000208 if (qemu_host_page_size == 0)
209 qemu_host_page_size = qemu_real_host_page_size;
210 if (qemu_host_page_size < TARGET_PAGE_SIZE)
211 qemu_host_page_size = TARGET_PAGE_SIZE;
212 qemu_host_page_bits = 0;
213 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
214 qemu_host_page_bits++;
215 qemu_host_page_mask = ~(qemu_host_page_size - 1);
bellard108c49b2005-07-24 12:55:09 +0000216 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
217 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
balrog50a95692007-12-12 01:16:23 +0000218
219#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
220 {
221 long long startaddr, endaddr;
222 FILE *f;
223 int n;
224
225 f = fopen("/proc/self/maps", "r");
226 if (f) {
227 do {
228 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
229 if (n == 2) {
230 page_set_flags(TARGET_PAGE_ALIGN(startaddr),
231 TARGET_PAGE_ALIGN(endaddr),
232 PAGE_RESERVED);
233 }
234 } while (!feof(f));
235 fclose(f);
236 }
237 }
238#endif
bellard54936002003-05-13 00:25:15 +0000239}
240
aurel3200f82b82008-04-27 21:12:55 +0000241static inline PageDesc *page_find_alloc(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000242{
bellard54936002003-05-13 00:25:15 +0000243 PageDesc **lp, *p;
244
bellard54936002003-05-13 00:25:15 +0000245 lp = &l1_map[index >> L2_BITS];
246 p = *lp;
247 if (!p) {
248 /* allocate if not found */
bellard59817cc2004-02-16 22:01:13 +0000249 p = qemu_malloc(sizeof(PageDesc) * L2_SIZE);
bellardfd6ce8f2003-05-14 19:00:11 +0000250 memset(p, 0, sizeof(PageDesc) * L2_SIZE);
bellard54936002003-05-13 00:25:15 +0000251 *lp = p;
252 }
253 return p + (index & (L2_SIZE - 1));
254}
255
aurel3200f82b82008-04-27 21:12:55 +0000256static inline PageDesc *page_find(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000257{
bellard54936002003-05-13 00:25:15 +0000258 PageDesc *p;
259
bellard54936002003-05-13 00:25:15 +0000260 p = l1_map[index >> L2_BITS];
261 if (!p)
262 return 0;
bellardfd6ce8f2003-05-14 19:00:11 +0000263 return p + (index & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000264}
265
bellard108c49b2005-07-24 12:55:09 +0000266static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
bellard92e873b2004-05-21 14:52:29 +0000267{
bellard108c49b2005-07-24 12:55:09 +0000268 void **lp, **p;
pbrooke3f4e2a2006-04-08 20:02:06 +0000269 PhysPageDesc *pd;
bellard92e873b2004-05-21 14:52:29 +0000270
bellard108c49b2005-07-24 12:55:09 +0000271 p = (void **)l1_phys_map;
272#if TARGET_PHYS_ADDR_SPACE_BITS > 32
273
274#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
275#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
276#endif
277 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000278 p = *lp;
279 if (!p) {
280 /* allocate if not found */
bellard108c49b2005-07-24 12:55:09 +0000281 if (!alloc)
282 return NULL;
283 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
284 memset(p, 0, sizeof(void *) * L1_SIZE);
285 *lp = p;
286 }
287#endif
288 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pbrooke3f4e2a2006-04-08 20:02:06 +0000289 pd = *lp;
290 if (!pd) {
291 int i;
bellard108c49b2005-07-24 12:55:09 +0000292 /* allocate if not found */
293 if (!alloc)
294 return NULL;
pbrooke3f4e2a2006-04-08 20:02:06 +0000295 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
296 *lp = pd;
297 for (i = 0; i < L2_SIZE; i++)
298 pd[i].phys_offset = IO_MEM_UNASSIGNED;
bellard92e873b2004-05-21 14:52:29 +0000299 }
pbrooke3f4e2a2006-04-08 20:02:06 +0000300 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000301}
302
bellard108c49b2005-07-24 12:55:09 +0000303static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
bellard92e873b2004-05-21 14:52:29 +0000304{
bellard108c49b2005-07-24 12:55:09 +0000305 return phys_page_find_alloc(index, 0);
bellard92e873b2004-05-21 14:52:29 +0000306}
307
bellard9fa3e852004-01-04 18:06:42 +0000308#if !defined(CONFIG_USER_ONLY)
bellard6a00d602005-11-21 23:25:50 +0000309static void tlb_protect_code(ram_addr_t ram_addr);
ths5fafdf22007-09-16 21:08:06 +0000310static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +0000311 target_ulong vaddr);
bellard9fa3e852004-01-04 18:06:42 +0000312#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000313
bellard6a00d602005-11-21 23:25:50 +0000314void cpu_exec_init(CPUState *env)
bellardfd6ce8f2003-05-14 19:00:11 +0000315{
bellard6a00d602005-11-21 23:25:50 +0000316 CPUState **penv;
317 int cpu_index;
318
bellardfd6ce8f2003-05-14 19:00:11 +0000319 if (!code_gen_ptr) {
bellard57fec1f2008-02-01 10:50:11 +0000320 cpu_gen_init();
bellardfd6ce8f2003-05-14 19:00:11 +0000321 code_gen_ptr = code_gen_buffer;
bellardb346ff42003-06-15 20:05:50 +0000322 page_init();
bellard33417e72003-08-10 21:47:01 +0000323 io_mem_init();
bellardfd6ce8f2003-05-14 19:00:11 +0000324 }
bellard6a00d602005-11-21 23:25:50 +0000325 env->next_cpu = NULL;
326 penv = &first_cpu;
327 cpu_index = 0;
328 while (*penv != NULL) {
329 penv = (CPUState **)&(*penv)->next_cpu;
330 cpu_index++;
331 }
332 env->cpu_index = cpu_index;
pbrook6658ffb2007-03-16 23:58:11 +0000333 env->nb_watchpoints = 0;
bellard6a00d602005-11-21 23:25:50 +0000334 *penv = env;
bellardfd6ce8f2003-05-14 19:00:11 +0000335}
336
bellard9fa3e852004-01-04 18:06:42 +0000337static inline void invalidate_page_bitmap(PageDesc *p)
338{
339 if (p->code_bitmap) {
bellard59817cc2004-02-16 22:01:13 +0000340 qemu_free(p->code_bitmap);
bellard9fa3e852004-01-04 18:06:42 +0000341 p->code_bitmap = NULL;
342 }
343 p->code_write_count = 0;
344}
345
bellardfd6ce8f2003-05-14 19:00:11 +0000346/* set to NULL all the 'first_tb' fields in all PageDescs */
347static void page_flush_tb(void)
348{
349 int i, j;
350 PageDesc *p;
351
352 for(i = 0; i < L1_SIZE; i++) {
353 p = l1_map[i];
354 if (p) {
bellard9fa3e852004-01-04 18:06:42 +0000355 for(j = 0; j < L2_SIZE; j++) {
356 p->first_tb = NULL;
357 invalidate_page_bitmap(p);
358 p++;
359 }
bellardfd6ce8f2003-05-14 19:00:11 +0000360 }
361 }
362}
363
364/* flush all the translation blocks */
bellardd4e81642003-05-25 16:46:15 +0000365/* XXX: tb_flush is currently not thread safe */
bellard6a00d602005-11-21 23:25:50 +0000366void tb_flush(CPUState *env1)
bellardfd6ce8f2003-05-14 19:00:11 +0000367{
bellard6a00d602005-11-21 23:25:50 +0000368 CPUState *env;
bellard01243112004-01-04 15:48:17 +0000369#if defined(DEBUG_FLUSH)
blueswir1ab3d1722007-11-04 07:31:40 +0000370 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
371 (unsigned long)(code_gen_ptr - code_gen_buffer),
372 nb_tbs, nb_tbs > 0 ?
373 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
bellardfd6ce8f2003-05-14 19:00:11 +0000374#endif
pbrooka208e542008-03-31 17:07:36 +0000375 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > CODE_GEN_BUFFER_SIZE)
376 cpu_abort(env1, "Internal error: code buffer overflow\n");
377
bellardfd6ce8f2003-05-14 19:00:11 +0000378 nb_tbs = 0;
ths3b46e622007-09-17 08:09:54 +0000379
bellard6a00d602005-11-21 23:25:50 +0000380 for(env = first_cpu; env != NULL; env = env->next_cpu) {
381 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
382 }
bellard9fa3e852004-01-04 18:06:42 +0000383
bellard8a8a6082004-10-03 13:36:49 +0000384 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
bellardfd6ce8f2003-05-14 19:00:11 +0000385 page_flush_tb();
bellard9fa3e852004-01-04 18:06:42 +0000386
bellardfd6ce8f2003-05-14 19:00:11 +0000387 code_gen_ptr = code_gen_buffer;
bellardd4e81642003-05-25 16:46:15 +0000388 /* XXX: flush processor icache at this point if cache flush is
389 expensive */
bellarde3db7222005-01-26 22:00:47 +0000390 tb_flush_count++;
bellardfd6ce8f2003-05-14 19:00:11 +0000391}
392
393#ifdef DEBUG_TB_CHECK
394
j_mayerbc98a7e2007-04-04 07:55:12 +0000395static void tb_invalidate_check(target_ulong address)
bellardfd6ce8f2003-05-14 19:00:11 +0000396{
397 TranslationBlock *tb;
398 int i;
399 address &= TARGET_PAGE_MASK;
pbrook99773bd2006-04-16 15:14:59 +0000400 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
401 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000402 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
403 address >= tb->pc + tb->size)) {
404 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
pbrook99773bd2006-04-16 15:14:59 +0000405 address, (long)tb->pc, tb->size);
bellardfd6ce8f2003-05-14 19:00:11 +0000406 }
407 }
408 }
409}
410
411/* verify that all the pages have correct rights for code */
412static void tb_page_check(void)
413{
414 TranslationBlock *tb;
415 int i, flags1, flags2;
ths3b46e622007-09-17 08:09:54 +0000416
pbrook99773bd2006-04-16 15:14:59 +0000417 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
418 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000419 flags1 = page_get_flags(tb->pc);
420 flags2 = page_get_flags(tb->pc + tb->size - 1);
421 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
422 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
pbrook99773bd2006-04-16 15:14:59 +0000423 (long)tb->pc, tb->size, flags1, flags2);
bellardfd6ce8f2003-05-14 19:00:11 +0000424 }
425 }
426 }
427}
428
bellardd4e81642003-05-25 16:46:15 +0000429void tb_jmp_check(TranslationBlock *tb)
430{
431 TranslationBlock *tb1;
432 unsigned int n1;
433
434 /* suppress any remaining jumps to this TB */
435 tb1 = tb->jmp_first;
436 for(;;) {
437 n1 = (long)tb1 & 3;
438 tb1 = (TranslationBlock *)((long)tb1 & ~3);
439 if (n1 == 2)
440 break;
441 tb1 = tb1->jmp_next[n1];
442 }
443 /* check end of list */
444 if (tb1 != tb) {
445 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
446 }
447}
448
bellardfd6ce8f2003-05-14 19:00:11 +0000449#endif
450
451/* invalidate one TB */
452static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
453 int next_offset)
454{
455 TranslationBlock *tb1;
456 for(;;) {
457 tb1 = *ptb;
458 if (tb1 == tb) {
459 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
460 break;
461 }
462 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
463 }
464}
465
bellard9fa3e852004-01-04 18:06:42 +0000466static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
467{
468 TranslationBlock *tb1;
469 unsigned int n1;
470
471 for(;;) {
472 tb1 = *ptb;
473 n1 = (long)tb1 & 3;
474 tb1 = (TranslationBlock *)((long)tb1 & ~3);
475 if (tb1 == tb) {
476 *ptb = tb1->page_next[n1];
477 break;
478 }
479 ptb = &tb1->page_next[n1];
480 }
481}
482
bellardd4e81642003-05-25 16:46:15 +0000483static inline void tb_jmp_remove(TranslationBlock *tb, int n)
484{
485 TranslationBlock *tb1, **ptb;
486 unsigned int n1;
487
488 ptb = &tb->jmp_next[n];
489 tb1 = *ptb;
490 if (tb1) {
491 /* find tb(n) in circular list */
492 for(;;) {
493 tb1 = *ptb;
494 n1 = (long)tb1 & 3;
495 tb1 = (TranslationBlock *)((long)tb1 & ~3);
496 if (n1 == n && tb1 == tb)
497 break;
498 if (n1 == 2) {
499 ptb = &tb1->jmp_first;
500 } else {
501 ptb = &tb1->jmp_next[n1];
502 }
503 }
504 /* now we can suppress tb(n) from the list */
505 *ptb = tb->jmp_next[n];
506
507 tb->jmp_next[n] = NULL;
508 }
509}
510
511/* reset the jump entry 'n' of a TB so that it is not chained to
512 another TB */
513static inline void tb_reset_jump(TranslationBlock *tb, int n)
514{
515 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
516}
517
aurel3200f82b82008-04-27 21:12:55 +0000518static inline void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000519{
bellard6a00d602005-11-21 23:25:50 +0000520 CPUState *env;
bellardfd6ce8f2003-05-14 19:00:11 +0000521 PageDesc *p;
bellard8a40a182005-11-20 10:35:40 +0000522 unsigned int h, n1;
aurel3200f82b82008-04-27 21:12:55 +0000523 target_phys_addr_t phys_pc;
bellard8a40a182005-11-20 10:35:40 +0000524 TranslationBlock *tb1, *tb2;
ths3b46e622007-09-17 08:09:54 +0000525
bellard9fa3e852004-01-04 18:06:42 +0000526 /* remove the TB from the hash list */
527 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
528 h = tb_phys_hash_func(phys_pc);
ths5fafdf22007-09-16 21:08:06 +0000529 tb_remove(&tb_phys_hash[h], tb,
bellard9fa3e852004-01-04 18:06:42 +0000530 offsetof(TranslationBlock, phys_hash_next));
bellardfd6ce8f2003-05-14 19:00:11 +0000531
bellard9fa3e852004-01-04 18:06:42 +0000532 /* remove the TB from the page list */
533 if (tb->page_addr[0] != page_addr) {
534 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
535 tb_page_remove(&p->first_tb, tb);
536 invalidate_page_bitmap(p);
537 }
538 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
539 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
540 tb_page_remove(&p->first_tb, tb);
541 invalidate_page_bitmap(p);
542 }
543
bellard8a40a182005-11-20 10:35:40 +0000544 tb_invalidated_flag = 1;
545
546 /* remove the TB from the hash list */
547 h = tb_jmp_cache_hash_func(tb->pc);
bellard6a00d602005-11-21 23:25:50 +0000548 for(env = first_cpu; env != NULL; env = env->next_cpu) {
549 if (env->tb_jmp_cache[h] == tb)
550 env->tb_jmp_cache[h] = NULL;
551 }
bellard8a40a182005-11-20 10:35:40 +0000552
553 /* suppress this TB from the two jump lists */
554 tb_jmp_remove(tb, 0);
555 tb_jmp_remove(tb, 1);
556
557 /* suppress any remaining jumps to this TB */
558 tb1 = tb->jmp_first;
559 for(;;) {
560 n1 = (long)tb1 & 3;
561 if (n1 == 2)
562 break;
563 tb1 = (TranslationBlock *)((long)tb1 & ~3);
564 tb2 = tb1->jmp_next[n1];
565 tb_reset_jump(tb1, n1);
566 tb1->jmp_next[n1] = NULL;
567 tb1 = tb2;
568 }
569 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
570
bellarde3db7222005-01-26 22:00:47 +0000571 tb_phys_invalidate_count++;
bellard9fa3e852004-01-04 18:06:42 +0000572}
573
574static inline void set_bits(uint8_t *tab, int start, int len)
575{
576 int end, mask, end1;
577
578 end = start + len;
579 tab += start >> 3;
580 mask = 0xff << (start & 7);
581 if ((start & ~7) == (end & ~7)) {
582 if (start < end) {
583 mask &= ~(0xff << (end & 7));
584 *tab |= mask;
585 }
586 } else {
587 *tab++ |= mask;
588 start = (start + 8) & ~7;
589 end1 = end & ~7;
590 while (start < end1) {
591 *tab++ = 0xff;
592 start += 8;
593 }
594 if (start < end) {
595 mask = ~(0xff << (end & 7));
596 *tab |= mask;
597 }
598 }
599}
600
601static void build_page_bitmap(PageDesc *p)
602{
603 int n, tb_start, tb_end;
604 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +0000605
bellard59817cc2004-02-16 22:01:13 +0000606 p->code_bitmap = qemu_malloc(TARGET_PAGE_SIZE / 8);
bellard9fa3e852004-01-04 18:06:42 +0000607 if (!p->code_bitmap)
608 return;
609 memset(p->code_bitmap, 0, TARGET_PAGE_SIZE / 8);
610
611 tb = p->first_tb;
612 while (tb != NULL) {
613 n = (long)tb & 3;
614 tb = (TranslationBlock *)((long)tb & ~3);
615 /* NOTE: this is subtle as a TB may span two physical pages */
616 if (n == 0) {
617 /* NOTE: tb_end may be after the end of the page, but
618 it is not a problem */
619 tb_start = tb->pc & ~TARGET_PAGE_MASK;
620 tb_end = tb_start + tb->size;
621 if (tb_end > TARGET_PAGE_SIZE)
622 tb_end = TARGET_PAGE_SIZE;
623 } else {
624 tb_start = 0;
625 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
626 }
627 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
628 tb = tb->page_next[n];
629 }
630}
631
bellardd720b932004-04-25 17:57:43 +0000632#ifdef TARGET_HAS_PRECISE_SMC
633
ths5fafdf22007-09-16 21:08:06 +0000634static void tb_gen_code(CPUState *env,
bellardd720b932004-04-25 17:57:43 +0000635 target_ulong pc, target_ulong cs_base, int flags,
636 int cflags)
637{
638 TranslationBlock *tb;
639 uint8_t *tc_ptr;
640 target_ulong phys_pc, phys_page2, virt_page2;
641 int code_gen_size;
642
bellardc27004e2005-01-03 23:35:10 +0000643 phys_pc = get_phys_addr_code(env, pc);
644 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000645 if (!tb) {
646 /* flush must be done */
647 tb_flush(env);
648 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000649 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000650 }
651 tc_ptr = code_gen_ptr;
652 tb->tc_ptr = tc_ptr;
653 tb->cs_base = cs_base;
654 tb->flags = flags;
655 tb->cflags = cflags;
blueswir1d07bde82007-12-11 19:35:45 +0000656 cpu_gen_code(env, tb, &code_gen_size);
bellardd720b932004-04-25 17:57:43 +0000657 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000658
bellardd720b932004-04-25 17:57:43 +0000659 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000660 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellardd720b932004-04-25 17:57:43 +0000661 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000662 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
bellardd720b932004-04-25 17:57:43 +0000663 phys_page2 = get_phys_addr_code(env, virt_page2);
664 }
665 tb_link_phys(tb, phys_pc, phys_page2);
666}
667#endif
ths3b46e622007-09-17 08:09:54 +0000668
bellard9fa3e852004-01-04 18:06:42 +0000669/* invalidate all TBs which intersect with the target physical page
670 starting in range [start;end[. NOTE: start and end must refer to
bellardd720b932004-04-25 17:57:43 +0000671 the same physical page. 'is_cpu_write_access' should be true if called
672 from a real cpu write access: the virtual CPU will exit the current
673 TB if code is modified inside this TB. */
aurel3200f82b82008-04-27 21:12:55 +0000674void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
bellardd720b932004-04-25 17:57:43 +0000675 int is_cpu_write_access)
bellard9fa3e852004-01-04 18:06:42 +0000676{
bellardd720b932004-04-25 17:57:43 +0000677 int n, current_tb_modified, current_tb_not_found, current_flags;
bellardd720b932004-04-25 17:57:43 +0000678 CPUState *env = cpu_single_env;
bellard9fa3e852004-01-04 18:06:42 +0000679 PageDesc *p;
bellardea1c1802004-06-14 18:56:36 +0000680 TranslationBlock *tb, *tb_next, *current_tb, *saved_tb;
bellard9fa3e852004-01-04 18:06:42 +0000681 target_ulong tb_start, tb_end;
bellardd720b932004-04-25 17:57:43 +0000682 target_ulong current_pc, current_cs_base;
bellard9fa3e852004-01-04 18:06:42 +0000683
684 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000685 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000686 return;
ths5fafdf22007-09-16 21:08:06 +0000687 if (!p->code_bitmap &&
bellardd720b932004-04-25 17:57:43 +0000688 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
689 is_cpu_write_access) {
bellard9fa3e852004-01-04 18:06:42 +0000690 /* build code bitmap */
691 build_page_bitmap(p);
692 }
693
694 /* we remove all the TBs in the range [start, end[ */
695 /* XXX: see if in some cases it could be faster to invalidate all the code */
bellardd720b932004-04-25 17:57:43 +0000696 current_tb_not_found = is_cpu_write_access;
697 current_tb_modified = 0;
698 current_tb = NULL; /* avoid warning */
699 current_pc = 0; /* avoid warning */
700 current_cs_base = 0; /* avoid warning */
701 current_flags = 0; /* avoid warning */
bellard9fa3e852004-01-04 18:06:42 +0000702 tb = p->first_tb;
703 while (tb != NULL) {
704 n = (long)tb & 3;
705 tb = (TranslationBlock *)((long)tb & ~3);
706 tb_next = tb->page_next[n];
707 /* NOTE: this is subtle as a TB may span two physical pages */
708 if (n == 0) {
709 /* NOTE: tb_end may be after the end of the page, but
710 it is not a problem */
711 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
712 tb_end = tb_start + tb->size;
713 } else {
714 tb_start = tb->page_addr[1];
715 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
716 }
717 if (!(tb_end <= start || tb_start >= end)) {
bellardd720b932004-04-25 17:57:43 +0000718#ifdef TARGET_HAS_PRECISE_SMC
719 if (current_tb_not_found) {
720 current_tb_not_found = 0;
721 current_tb = NULL;
722 if (env->mem_write_pc) {
723 /* now we have a real cpu fault */
724 current_tb = tb_find_pc(env->mem_write_pc);
725 }
726 }
727 if (current_tb == tb &&
728 !(current_tb->cflags & CF_SINGLE_INSN)) {
729 /* If we are modifying the current TB, we must stop
730 its execution. We could be more precise by checking
731 that the modification is after the current PC, but it
732 would require a specialized function to partially
733 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +0000734
bellardd720b932004-04-25 17:57:43 +0000735 current_tb_modified = 1;
ths5fafdf22007-09-16 21:08:06 +0000736 cpu_restore_state(current_tb, env,
bellardd720b932004-04-25 17:57:43 +0000737 env->mem_write_pc, NULL);
738#if defined(TARGET_I386)
739 current_flags = env->hflags;
740 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
741 current_cs_base = (target_ulong)env->segs[R_CS].base;
742 current_pc = current_cs_base + env->eip;
743#else
744#error unsupported CPU
745#endif
746 }
747#endif /* TARGET_HAS_PRECISE_SMC */
bellard6f5a9f72005-11-26 20:12:28 +0000748 /* we need to do that to handle the case where a signal
749 occurs while doing tb_phys_invalidate() */
750 saved_tb = NULL;
751 if (env) {
752 saved_tb = env->current_tb;
753 env->current_tb = NULL;
754 }
bellard9fa3e852004-01-04 18:06:42 +0000755 tb_phys_invalidate(tb, -1);
bellard6f5a9f72005-11-26 20:12:28 +0000756 if (env) {
757 env->current_tb = saved_tb;
758 if (env->interrupt_request && env->current_tb)
759 cpu_interrupt(env, env->interrupt_request);
760 }
bellard9fa3e852004-01-04 18:06:42 +0000761 }
762 tb = tb_next;
763 }
764#if !defined(CONFIG_USER_ONLY)
765 /* if no code remaining, no need to continue to use slow writes */
766 if (!p->first_tb) {
767 invalidate_page_bitmap(p);
bellardd720b932004-04-25 17:57:43 +0000768 if (is_cpu_write_access) {
769 tlb_unprotect_code_phys(env, start, env->mem_write_vaddr);
770 }
771 }
772#endif
773#ifdef TARGET_HAS_PRECISE_SMC
774 if (current_tb_modified) {
775 /* we generate a block containing just the instruction
776 modifying the memory. It will ensure that it cannot modify
777 itself */
bellardea1c1802004-06-14 18:56:36 +0000778 env->current_tb = NULL;
ths5fafdf22007-09-16 21:08:06 +0000779 tb_gen_code(env, current_pc, current_cs_base, current_flags,
bellardd720b932004-04-25 17:57:43 +0000780 CF_SINGLE_INSN);
781 cpu_resume_from_signal(env, NULL);
bellard9fa3e852004-01-04 18:06:42 +0000782 }
783#endif
784}
785
786/* len must be <= 8 and start must be a multiple of len */
aurel3200f82b82008-04-27 21:12:55 +0000787static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
bellard9fa3e852004-01-04 18:06:42 +0000788{
789 PageDesc *p;
790 int offset, b;
bellard59817cc2004-02-16 22:01:13 +0000791#if 0
bellarda4193c82004-06-03 14:01:43 +0000792 if (1) {
793 if (loglevel) {
ths5fafdf22007-09-16 21:08:06 +0000794 fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
795 cpu_single_env->mem_write_vaddr, len,
796 cpu_single_env->eip,
bellarda4193c82004-06-03 14:01:43 +0000797 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
798 }
bellard59817cc2004-02-16 22:01:13 +0000799 }
800#endif
bellard9fa3e852004-01-04 18:06:42 +0000801 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000802 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000803 return;
804 if (p->code_bitmap) {
805 offset = start & ~TARGET_PAGE_MASK;
806 b = p->code_bitmap[offset >> 3] >> (offset & 7);
807 if (b & ((1 << len) - 1))
808 goto do_invalidate;
809 } else {
810 do_invalidate:
bellardd720b932004-04-25 17:57:43 +0000811 tb_invalidate_phys_page_range(start, start + len, 1);
bellard9fa3e852004-01-04 18:06:42 +0000812 }
813}
814
bellard9fa3e852004-01-04 18:06:42 +0000815#if !defined(CONFIG_SOFTMMU)
aurel3200f82b82008-04-27 21:12:55 +0000816static void tb_invalidate_phys_page(target_phys_addr_t addr,
bellardd720b932004-04-25 17:57:43 +0000817 unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +0000818{
bellardd720b932004-04-25 17:57:43 +0000819 int n, current_flags, current_tb_modified;
820 target_ulong current_pc, current_cs_base;
bellard9fa3e852004-01-04 18:06:42 +0000821 PageDesc *p;
bellardd720b932004-04-25 17:57:43 +0000822 TranslationBlock *tb, *current_tb;
823#ifdef TARGET_HAS_PRECISE_SMC
824 CPUState *env = cpu_single_env;
825#endif
bellard9fa3e852004-01-04 18:06:42 +0000826
827 addr &= TARGET_PAGE_MASK;
828 p = page_find(addr >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000829 if (!p)
bellardfd6ce8f2003-05-14 19:00:11 +0000830 return;
831 tb = p->first_tb;
bellardd720b932004-04-25 17:57:43 +0000832 current_tb_modified = 0;
833 current_tb = NULL;
834 current_pc = 0; /* avoid warning */
835 current_cs_base = 0; /* avoid warning */
836 current_flags = 0; /* avoid warning */
837#ifdef TARGET_HAS_PRECISE_SMC
838 if (tb && pc != 0) {
839 current_tb = tb_find_pc(pc);
840 }
841#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000842 while (tb != NULL) {
bellard9fa3e852004-01-04 18:06:42 +0000843 n = (long)tb & 3;
844 tb = (TranslationBlock *)((long)tb & ~3);
bellardd720b932004-04-25 17:57:43 +0000845#ifdef TARGET_HAS_PRECISE_SMC
846 if (current_tb == tb &&
847 !(current_tb->cflags & CF_SINGLE_INSN)) {
848 /* If we are modifying the current TB, we must stop
849 its execution. We could be more precise by checking
850 that the modification is after the current PC, but it
851 would require a specialized function to partially
852 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +0000853
bellardd720b932004-04-25 17:57:43 +0000854 current_tb_modified = 1;
855 cpu_restore_state(current_tb, env, pc, puc);
856#if defined(TARGET_I386)
857 current_flags = env->hflags;
858 current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
859 current_cs_base = (target_ulong)env->segs[R_CS].base;
860 current_pc = current_cs_base + env->eip;
861#else
862#error unsupported CPU
863#endif
864 }
865#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +0000866 tb_phys_invalidate(tb, addr);
867 tb = tb->page_next[n];
bellardfd6ce8f2003-05-14 19:00:11 +0000868 }
869 p->first_tb = NULL;
bellardd720b932004-04-25 17:57:43 +0000870#ifdef TARGET_HAS_PRECISE_SMC
871 if (current_tb_modified) {
872 /* we generate a block containing just the instruction
873 modifying the memory. It will ensure that it cannot modify
874 itself */
bellardea1c1802004-06-14 18:56:36 +0000875 env->current_tb = NULL;
ths5fafdf22007-09-16 21:08:06 +0000876 tb_gen_code(env, current_pc, current_cs_base, current_flags,
bellardd720b932004-04-25 17:57:43 +0000877 CF_SINGLE_INSN);
878 cpu_resume_from_signal(env, puc);
879 }
880#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000881}
bellard9fa3e852004-01-04 18:06:42 +0000882#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000883
884/* add the tb in the target page and protect it if necessary */
ths5fafdf22007-09-16 21:08:06 +0000885static inline void tb_alloc_page(TranslationBlock *tb,
pbrook53a59602006-03-25 19:31:22 +0000886 unsigned int n, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000887{
888 PageDesc *p;
bellard9fa3e852004-01-04 18:06:42 +0000889 TranslationBlock *last_first_tb;
bellardfd6ce8f2003-05-14 19:00:11 +0000890
bellard9fa3e852004-01-04 18:06:42 +0000891 tb->page_addr[n] = page_addr;
bellard3a7d9292005-08-21 09:26:42 +0000892 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +0000893 tb->page_next[n] = p->first_tb;
894 last_first_tb = p->first_tb;
895 p->first_tb = (TranslationBlock *)((long)tb | n);
896 invalidate_page_bitmap(p);
897
bellard107db442004-06-22 18:48:46 +0000898#if defined(TARGET_HAS_SMC) || 1
bellardd720b932004-04-25 17:57:43 +0000899
bellard9fa3e852004-01-04 18:06:42 +0000900#if defined(CONFIG_USER_ONLY)
bellardfd6ce8f2003-05-14 19:00:11 +0000901 if (p->flags & PAGE_WRITE) {
pbrook53a59602006-03-25 19:31:22 +0000902 target_ulong addr;
903 PageDesc *p2;
bellard9fa3e852004-01-04 18:06:42 +0000904 int prot;
905
bellardfd6ce8f2003-05-14 19:00:11 +0000906 /* force the host page as non writable (writes will have a
907 page fault + mprotect overhead) */
pbrook53a59602006-03-25 19:31:22 +0000908 page_addr &= qemu_host_page_mask;
bellardfd6ce8f2003-05-14 19:00:11 +0000909 prot = 0;
pbrook53a59602006-03-25 19:31:22 +0000910 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
911 addr += TARGET_PAGE_SIZE) {
912
913 p2 = page_find (addr >> TARGET_PAGE_BITS);
914 if (!p2)
915 continue;
916 prot |= p2->flags;
917 p2->flags &= ~PAGE_WRITE;
918 page_get_flags(addr);
919 }
ths5fafdf22007-09-16 21:08:06 +0000920 mprotect(g2h(page_addr), qemu_host_page_size,
bellardfd6ce8f2003-05-14 19:00:11 +0000921 (prot & PAGE_BITS) & ~PAGE_WRITE);
922#ifdef DEBUG_TB_INVALIDATE
blueswir1ab3d1722007-11-04 07:31:40 +0000923 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
pbrook53a59602006-03-25 19:31:22 +0000924 page_addr);
bellardfd6ce8f2003-05-14 19:00:11 +0000925#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000926 }
bellard9fa3e852004-01-04 18:06:42 +0000927#else
928 /* if some code is already present, then the pages are already
929 protected. So we handle the case where only the first TB is
930 allocated in a physical page */
931 if (!last_first_tb) {
bellard6a00d602005-11-21 23:25:50 +0000932 tlb_protect_code(page_addr);
bellard9fa3e852004-01-04 18:06:42 +0000933 }
934#endif
bellardd720b932004-04-25 17:57:43 +0000935
936#endif /* TARGET_HAS_SMC */
bellardfd6ce8f2003-05-14 19:00:11 +0000937}
938
939/* Allocate a new translation block. Flush the translation buffer if
940 too many translation blocks or too much generated code. */
bellardc27004e2005-01-03 23:35:10 +0000941TranslationBlock *tb_alloc(target_ulong pc)
bellardfd6ce8f2003-05-14 19:00:11 +0000942{
943 TranslationBlock *tb;
bellardfd6ce8f2003-05-14 19:00:11 +0000944
ths5fafdf22007-09-16 21:08:06 +0000945 if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
bellardfd6ce8f2003-05-14 19:00:11 +0000946 (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE)
bellardd4e81642003-05-25 16:46:15 +0000947 return NULL;
bellardfd6ce8f2003-05-14 19:00:11 +0000948 tb = &tbs[nb_tbs++];
949 tb->pc = pc;
bellardb448f2f2004-02-25 23:24:04 +0000950 tb->cflags = 0;
bellardd4e81642003-05-25 16:46:15 +0000951 return tb;
952}
953
bellard9fa3e852004-01-04 18:06:42 +0000954/* add a new TB and link it to the physical page tables. phys_page2 is
955 (-1) to indicate that only one page contains the TB. */
ths5fafdf22007-09-16 21:08:06 +0000956void tb_link_phys(TranslationBlock *tb,
bellard9fa3e852004-01-04 18:06:42 +0000957 target_ulong phys_pc, target_ulong phys_page2)
bellardd4e81642003-05-25 16:46:15 +0000958{
bellard9fa3e852004-01-04 18:06:42 +0000959 unsigned int h;
960 TranslationBlock **ptb;
961
962 /* add in the physical hash table */
963 h = tb_phys_hash_func(phys_pc);
964 ptb = &tb_phys_hash[h];
965 tb->phys_hash_next = *ptb;
966 *ptb = tb;
bellardfd6ce8f2003-05-14 19:00:11 +0000967
968 /* add in the page list */
bellard9fa3e852004-01-04 18:06:42 +0000969 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
970 if (phys_page2 != -1)
971 tb_alloc_page(tb, 1, phys_page2);
972 else
973 tb->page_addr[1] = -1;
bellard9fa3e852004-01-04 18:06:42 +0000974
bellardd4e81642003-05-25 16:46:15 +0000975 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
976 tb->jmp_next[0] = NULL;
977 tb->jmp_next[1] = NULL;
978
979 /* init original jump addresses */
980 if (tb->tb_next_offset[0] != 0xffff)
981 tb_reset_jump(tb, 0);
982 if (tb->tb_next_offset[1] != 0xffff)
983 tb_reset_jump(tb, 1);
bellard8a40a182005-11-20 10:35:40 +0000984
985#ifdef DEBUG_TB_CHECK
986 tb_page_check();
987#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000988}
989
bellarda513fe12003-05-27 23:29:48 +0000990/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
991 tb[1].tc_ptr. Return NULL if not found */
992TranslationBlock *tb_find_pc(unsigned long tc_ptr)
993{
994 int m_min, m_max, m;
995 unsigned long v;
996 TranslationBlock *tb;
997
998 if (nb_tbs <= 0)
999 return NULL;
1000 if (tc_ptr < (unsigned long)code_gen_buffer ||
1001 tc_ptr >= (unsigned long)code_gen_ptr)
1002 return NULL;
1003 /* binary search (cf Knuth) */
1004 m_min = 0;
1005 m_max = nb_tbs - 1;
1006 while (m_min <= m_max) {
1007 m = (m_min + m_max) >> 1;
1008 tb = &tbs[m];
1009 v = (unsigned long)tb->tc_ptr;
1010 if (v == tc_ptr)
1011 return tb;
1012 else if (tc_ptr < v) {
1013 m_max = m - 1;
1014 } else {
1015 m_min = m + 1;
1016 }
ths5fafdf22007-09-16 21:08:06 +00001017 }
bellarda513fe12003-05-27 23:29:48 +00001018 return &tbs[m_max];
1019}
bellard75012672003-06-21 13:11:07 +00001020
bellardea041c02003-06-25 16:16:50 +00001021static void tb_reset_jump_recursive(TranslationBlock *tb);
1022
1023static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1024{
1025 TranslationBlock *tb1, *tb_next, **ptb;
1026 unsigned int n1;
1027
1028 tb1 = tb->jmp_next[n];
1029 if (tb1 != NULL) {
1030 /* find head of list */
1031 for(;;) {
1032 n1 = (long)tb1 & 3;
1033 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1034 if (n1 == 2)
1035 break;
1036 tb1 = tb1->jmp_next[n1];
1037 }
1038 /* we are now sure now that tb jumps to tb1 */
1039 tb_next = tb1;
1040
1041 /* remove tb from the jmp_first list */
1042 ptb = &tb_next->jmp_first;
1043 for(;;) {
1044 tb1 = *ptb;
1045 n1 = (long)tb1 & 3;
1046 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1047 if (n1 == n && tb1 == tb)
1048 break;
1049 ptb = &tb1->jmp_next[n1];
1050 }
1051 *ptb = tb->jmp_next[n];
1052 tb->jmp_next[n] = NULL;
ths3b46e622007-09-17 08:09:54 +00001053
bellardea041c02003-06-25 16:16:50 +00001054 /* suppress the jump to next tb in generated code */
1055 tb_reset_jump(tb, n);
1056
bellard01243112004-01-04 15:48:17 +00001057 /* suppress jumps in the tb on which we could have jumped */
bellardea041c02003-06-25 16:16:50 +00001058 tb_reset_jump_recursive(tb_next);
1059 }
1060}
1061
1062static void tb_reset_jump_recursive(TranslationBlock *tb)
1063{
1064 tb_reset_jump_recursive2(tb, 0);
1065 tb_reset_jump_recursive2(tb, 1);
1066}
1067
bellard1fddef42005-04-17 19:16:13 +00001068#if defined(TARGET_HAS_ICE)
bellardd720b932004-04-25 17:57:43 +00001069static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1070{
j_mayer9b3c35e2007-04-07 11:21:28 +00001071 target_phys_addr_t addr;
1072 target_ulong pd;
pbrookc2f07f82006-04-08 17:14:56 +00001073 ram_addr_t ram_addr;
1074 PhysPageDesc *p;
bellardd720b932004-04-25 17:57:43 +00001075
pbrookc2f07f82006-04-08 17:14:56 +00001076 addr = cpu_get_phys_page_debug(env, pc);
1077 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1078 if (!p) {
1079 pd = IO_MEM_UNASSIGNED;
1080 } else {
1081 pd = p->phys_offset;
1082 }
1083 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
pbrook706cd4b2006-04-08 17:36:21 +00001084 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
bellardd720b932004-04-25 17:57:43 +00001085}
bellardc27004e2005-01-03 23:35:10 +00001086#endif
bellardd720b932004-04-25 17:57:43 +00001087
pbrook6658ffb2007-03-16 23:58:11 +00001088/* Add a watchpoint. */
1089int cpu_watchpoint_insert(CPUState *env, target_ulong addr)
1090{
1091 int i;
1092
1093 for (i = 0; i < env->nb_watchpoints; i++) {
1094 if (addr == env->watchpoint[i].vaddr)
1095 return 0;
1096 }
1097 if (env->nb_watchpoints >= MAX_WATCHPOINTS)
1098 return -1;
1099
1100 i = env->nb_watchpoints++;
1101 env->watchpoint[i].vaddr = addr;
1102 tlb_flush_page(env, addr);
1103 /* FIXME: This flush is needed because of the hack to make memory ops
1104 terminate the TB. It can be removed once the proper IO trap and
1105 re-execute bits are in. */
1106 tb_flush(env);
1107 return i;
1108}
1109
1110/* Remove a watchpoint. */
1111int cpu_watchpoint_remove(CPUState *env, target_ulong addr)
1112{
1113 int i;
1114
1115 for (i = 0; i < env->nb_watchpoints; i++) {
1116 if (addr == env->watchpoint[i].vaddr) {
1117 env->nb_watchpoints--;
1118 env->watchpoint[i] = env->watchpoint[env->nb_watchpoints];
1119 tlb_flush_page(env, addr);
1120 return 0;
1121 }
1122 }
1123 return -1;
1124}
1125
bellardc33a3462003-07-29 20:50:33 +00001126/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
1127 breakpoint is reached */
bellard2e126692004-04-25 21:28:44 +00001128int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
bellard4c3a88a2003-07-26 12:06:08 +00001129{
bellard1fddef42005-04-17 19:16:13 +00001130#if defined(TARGET_HAS_ICE)
bellard4c3a88a2003-07-26 12:06:08 +00001131 int i;
ths3b46e622007-09-17 08:09:54 +00001132
bellard4c3a88a2003-07-26 12:06:08 +00001133 for(i = 0; i < env->nb_breakpoints; i++) {
1134 if (env->breakpoints[i] == pc)
1135 return 0;
1136 }
1137
1138 if (env->nb_breakpoints >= MAX_BREAKPOINTS)
1139 return -1;
1140 env->breakpoints[env->nb_breakpoints++] = pc;
ths3b46e622007-09-17 08:09:54 +00001141
bellardd720b932004-04-25 17:57:43 +00001142 breakpoint_invalidate(env, pc);
bellard4c3a88a2003-07-26 12:06:08 +00001143 return 0;
1144#else
1145 return -1;
1146#endif
1147}
1148
1149/* remove a breakpoint */
bellard2e126692004-04-25 21:28:44 +00001150int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
bellard4c3a88a2003-07-26 12:06:08 +00001151{
bellard1fddef42005-04-17 19:16:13 +00001152#if defined(TARGET_HAS_ICE)
bellard4c3a88a2003-07-26 12:06:08 +00001153 int i;
1154 for(i = 0; i < env->nb_breakpoints; i++) {
1155 if (env->breakpoints[i] == pc)
1156 goto found;
1157 }
1158 return -1;
1159 found:
bellard4c3a88a2003-07-26 12:06:08 +00001160 env->nb_breakpoints--;
bellard1fddef42005-04-17 19:16:13 +00001161 if (i < env->nb_breakpoints)
1162 env->breakpoints[i] = env->breakpoints[env->nb_breakpoints];
bellardd720b932004-04-25 17:57:43 +00001163
1164 breakpoint_invalidate(env, pc);
bellard4c3a88a2003-07-26 12:06:08 +00001165 return 0;
1166#else
1167 return -1;
1168#endif
1169}
1170
bellardc33a3462003-07-29 20:50:33 +00001171/* enable or disable single step mode. EXCP_DEBUG is returned by the
1172 CPU loop after each instruction */
1173void cpu_single_step(CPUState *env, int enabled)
1174{
bellard1fddef42005-04-17 19:16:13 +00001175#if defined(TARGET_HAS_ICE)
bellardc33a3462003-07-29 20:50:33 +00001176 if (env->singlestep_enabled != enabled) {
1177 env->singlestep_enabled = enabled;
1178 /* must flush all the translated code to avoid inconsistancies */
bellard9fa3e852004-01-04 18:06:42 +00001179 /* XXX: only flush what is necessary */
bellard01243112004-01-04 15:48:17 +00001180 tb_flush(env);
bellardc33a3462003-07-29 20:50:33 +00001181 }
1182#endif
1183}
1184
bellard34865132003-10-05 14:28:56 +00001185/* enable or disable low levels log */
1186void cpu_set_log(int log_flags)
1187{
1188 loglevel = log_flags;
1189 if (loglevel && !logfile) {
pbrook11fcfab2007-07-01 18:21:11 +00001190 logfile = fopen(logfilename, log_append ? "a" : "w");
bellard34865132003-10-05 14:28:56 +00001191 if (!logfile) {
1192 perror(logfilename);
1193 _exit(1);
1194 }
bellard9fa3e852004-01-04 18:06:42 +00001195#if !defined(CONFIG_SOFTMMU)
1196 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1197 {
1198 static uint8_t logfile_buf[4096];
1199 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1200 }
1201#else
bellard34865132003-10-05 14:28:56 +00001202 setvbuf(logfile, NULL, _IOLBF, 0);
bellard9fa3e852004-01-04 18:06:42 +00001203#endif
pbrooke735b912007-06-30 13:53:24 +00001204 log_append = 1;
1205 }
1206 if (!loglevel && logfile) {
1207 fclose(logfile);
1208 logfile = NULL;
bellard34865132003-10-05 14:28:56 +00001209 }
1210}
1211
1212void cpu_set_log_filename(const char *filename)
1213{
1214 logfilename = strdup(filename);
pbrooke735b912007-06-30 13:53:24 +00001215 if (logfile) {
1216 fclose(logfile);
1217 logfile = NULL;
1218 }
1219 cpu_set_log(loglevel);
bellard34865132003-10-05 14:28:56 +00001220}
bellardc33a3462003-07-29 20:50:33 +00001221
bellard01243112004-01-04 15:48:17 +00001222/* mask must never be zero, except for A20 change call */
bellard68a79312003-06-30 13:12:32 +00001223void cpu_interrupt(CPUState *env, int mask)
bellardea041c02003-06-25 16:16:50 +00001224{
1225 TranslationBlock *tb;
aurel3215a51152008-03-28 22:29:15 +00001226 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
bellard59817cc2004-02-16 22:01:13 +00001227
bellard68a79312003-06-30 13:12:32 +00001228 env->interrupt_request |= mask;
bellardea041c02003-06-25 16:16:50 +00001229 /* if the cpu is currently executing code, we must unlink it and
1230 all the potentially executing TB */
1231 tb = env->current_tb;
bellardee8b7022004-02-03 23:35:10 +00001232 if (tb && !testandset(&interrupt_lock)) {
1233 env->current_tb = NULL;
bellardea041c02003-06-25 16:16:50 +00001234 tb_reset_jump_recursive(tb);
aurel3215a51152008-03-28 22:29:15 +00001235 resetlock(&interrupt_lock);
bellardea041c02003-06-25 16:16:50 +00001236 }
1237}
1238
bellardb54ad042004-05-20 13:42:52 +00001239void cpu_reset_interrupt(CPUState *env, int mask)
1240{
1241 env->interrupt_request &= ~mask;
1242}
1243
bellardf193c792004-03-21 17:06:25 +00001244CPULogItem cpu_log_items[] = {
ths5fafdf22007-09-16 21:08:06 +00001245 { CPU_LOG_TB_OUT_ASM, "out_asm",
bellardf193c792004-03-21 17:06:25 +00001246 "show generated host assembly code for each compiled TB" },
1247 { CPU_LOG_TB_IN_ASM, "in_asm",
1248 "show target assembly code for each compiled TB" },
ths5fafdf22007-09-16 21:08:06 +00001249 { CPU_LOG_TB_OP, "op",
bellard57fec1f2008-02-01 10:50:11 +00001250 "show micro ops for each compiled TB" },
bellardf193c792004-03-21 17:06:25 +00001251 { CPU_LOG_TB_OP_OPT, "op_opt",
blueswir1e01a1152008-03-14 17:37:11 +00001252 "show micro ops "
1253#ifdef TARGET_I386
1254 "before eflags optimization and "
bellardf193c792004-03-21 17:06:25 +00001255#endif
blueswir1e01a1152008-03-14 17:37:11 +00001256 "after liveness analysis" },
bellardf193c792004-03-21 17:06:25 +00001257 { CPU_LOG_INT, "int",
1258 "show interrupts/exceptions in short format" },
1259 { CPU_LOG_EXEC, "exec",
1260 "show trace before each executed TB (lots of logs)" },
bellard9fddaa02004-05-21 12:59:32 +00001261 { CPU_LOG_TB_CPU, "cpu",
thse91c8a72007-06-03 13:35:16 +00001262 "show CPU state before block translation" },
bellardf193c792004-03-21 17:06:25 +00001263#ifdef TARGET_I386
1264 { CPU_LOG_PCALL, "pcall",
1265 "show protected mode far calls/returns/exceptions" },
1266#endif
bellard8e3a9fd2004-10-09 17:32:58 +00001267#ifdef DEBUG_IOPORT
bellardfd872592004-05-12 19:11:15 +00001268 { CPU_LOG_IOPORT, "ioport",
1269 "show all i/o ports accesses" },
bellard8e3a9fd2004-10-09 17:32:58 +00001270#endif
bellardf193c792004-03-21 17:06:25 +00001271 { 0, NULL, NULL },
1272};
1273
1274static int cmp1(const char *s1, int n, const char *s2)
1275{
1276 if (strlen(s2) != n)
1277 return 0;
1278 return memcmp(s1, s2, n) == 0;
1279}
ths3b46e622007-09-17 08:09:54 +00001280
bellardf193c792004-03-21 17:06:25 +00001281/* takes a comma separated list of log masks. Return 0 if error. */
1282int cpu_str_to_log_mask(const char *str)
1283{
1284 CPULogItem *item;
1285 int mask;
1286 const char *p, *p1;
1287
1288 p = str;
1289 mask = 0;
1290 for(;;) {
1291 p1 = strchr(p, ',');
1292 if (!p1)
1293 p1 = p + strlen(p);
bellard8e3a9fd2004-10-09 17:32:58 +00001294 if(cmp1(p,p1-p,"all")) {
1295 for(item = cpu_log_items; item->mask != 0; item++) {
1296 mask |= item->mask;
1297 }
1298 } else {
bellardf193c792004-03-21 17:06:25 +00001299 for(item = cpu_log_items; item->mask != 0; item++) {
1300 if (cmp1(p, p1 - p, item->name))
1301 goto found;
1302 }
1303 return 0;
bellard8e3a9fd2004-10-09 17:32:58 +00001304 }
bellardf193c792004-03-21 17:06:25 +00001305 found:
1306 mask |= item->mask;
1307 if (*p1 != ',')
1308 break;
1309 p = p1 + 1;
1310 }
1311 return mask;
1312}
bellardea041c02003-06-25 16:16:50 +00001313
bellard75012672003-06-21 13:11:07 +00001314void cpu_abort(CPUState *env, const char *fmt, ...)
1315{
1316 va_list ap;
pbrook493ae1f2007-11-23 16:53:59 +00001317 va_list ap2;
bellard75012672003-06-21 13:11:07 +00001318
1319 va_start(ap, fmt);
pbrook493ae1f2007-11-23 16:53:59 +00001320 va_copy(ap2, ap);
bellard75012672003-06-21 13:11:07 +00001321 fprintf(stderr, "qemu: fatal: ");
1322 vfprintf(stderr, fmt, ap);
1323 fprintf(stderr, "\n");
1324#ifdef TARGET_I386
ths0573fbf2007-09-23 15:28:04 +00001325 if(env->intercept & INTERCEPT_SVM_MASK) {
1326 /* most probably the virtual machine should not
1327 be shut down but rather caught by the VMM */
1328 vmexit(SVM_EXIT_SHUTDOWN, 0);
1329 }
bellard7fe48482004-10-09 18:08:01 +00001330 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1331#else
1332 cpu_dump_state(env, stderr, fprintf, 0);
bellard75012672003-06-21 13:11:07 +00001333#endif
balrog924edca2007-06-10 14:07:13 +00001334 if (logfile) {
j_mayerf9373292007-09-29 12:18:20 +00001335 fprintf(logfile, "qemu: fatal: ");
pbrook493ae1f2007-11-23 16:53:59 +00001336 vfprintf(logfile, fmt, ap2);
j_mayerf9373292007-09-29 12:18:20 +00001337 fprintf(logfile, "\n");
1338#ifdef TARGET_I386
1339 cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1340#else
1341 cpu_dump_state(env, logfile, fprintf, 0);
1342#endif
balrog924edca2007-06-10 14:07:13 +00001343 fflush(logfile);
1344 fclose(logfile);
1345 }
pbrook493ae1f2007-11-23 16:53:59 +00001346 va_end(ap2);
j_mayerf9373292007-09-29 12:18:20 +00001347 va_end(ap);
bellard75012672003-06-21 13:11:07 +00001348 abort();
1349}
1350
thsc5be9f02007-02-28 20:20:53 +00001351CPUState *cpu_copy(CPUState *env)
1352{
ths01ba9812007-12-09 02:22:57 +00001353 CPUState *new_env = cpu_init(env->cpu_model_str);
thsc5be9f02007-02-28 20:20:53 +00001354 /* preserve chaining and index */
1355 CPUState *next_cpu = new_env->next_cpu;
1356 int cpu_index = new_env->cpu_index;
1357 memcpy(new_env, env, sizeof(CPUState));
1358 new_env->next_cpu = next_cpu;
1359 new_env->cpu_index = cpu_index;
1360 return new_env;
1361}
1362
bellard01243112004-01-04 15:48:17 +00001363#if !defined(CONFIG_USER_ONLY)
1364
bellardee8b7022004-02-03 23:35:10 +00001365/* NOTE: if flush_global is true, also flush global entries (not
1366 implemented yet) */
1367void tlb_flush(CPUState *env, int flush_global)
bellard33417e72003-08-10 21:47:01 +00001368{
bellard33417e72003-08-10 21:47:01 +00001369 int i;
bellard01243112004-01-04 15:48:17 +00001370
bellard9fa3e852004-01-04 18:06:42 +00001371#if defined(DEBUG_TLB)
1372 printf("tlb_flush:\n");
1373#endif
bellard01243112004-01-04 15:48:17 +00001374 /* must reset current TB so that interrupts cannot modify the
1375 links while we are modifying them */
1376 env->current_tb = NULL;
1377
bellard33417e72003-08-10 21:47:01 +00001378 for(i = 0; i < CPU_TLB_SIZE; i++) {
bellard84b7b8e2005-11-28 21:19:04 +00001379 env->tlb_table[0][i].addr_read = -1;
1380 env->tlb_table[0][i].addr_write = -1;
1381 env->tlb_table[0][i].addr_code = -1;
1382 env->tlb_table[1][i].addr_read = -1;
1383 env->tlb_table[1][i].addr_write = -1;
1384 env->tlb_table[1][i].addr_code = -1;
j_mayer6fa4cea2007-04-05 06:43:27 +00001385#if (NB_MMU_MODES >= 3)
1386 env->tlb_table[2][i].addr_read = -1;
1387 env->tlb_table[2][i].addr_write = -1;
1388 env->tlb_table[2][i].addr_code = -1;
1389#if (NB_MMU_MODES == 4)
1390 env->tlb_table[3][i].addr_read = -1;
1391 env->tlb_table[3][i].addr_write = -1;
1392 env->tlb_table[3][i].addr_code = -1;
1393#endif
1394#endif
bellard33417e72003-08-10 21:47:01 +00001395 }
bellard9fa3e852004-01-04 18:06:42 +00001396
bellard8a40a182005-11-20 10:35:40 +00001397 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
bellard9fa3e852004-01-04 18:06:42 +00001398
1399#if !defined(CONFIG_SOFTMMU)
1400 munmap((void *)MMAP_AREA_START, MMAP_AREA_END - MMAP_AREA_START);
1401#endif
bellard0a962c02005-02-10 22:00:27 +00001402#ifdef USE_KQEMU
1403 if (env->kqemu_enabled) {
1404 kqemu_flush(env, flush_global);
1405 }
1406#endif
bellarde3db7222005-01-26 22:00:47 +00001407 tlb_flush_count++;
bellard33417e72003-08-10 21:47:01 +00001408}
1409
bellard274da6b2004-05-20 21:56:27 +00001410static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
bellard61382a52003-10-27 21:22:23 +00001411{
ths5fafdf22007-09-16 21:08:06 +00001412 if (addr == (tlb_entry->addr_read &
bellard84b7b8e2005-11-28 21:19:04 +00001413 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001414 addr == (tlb_entry->addr_write &
bellard84b7b8e2005-11-28 21:19:04 +00001415 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001416 addr == (tlb_entry->addr_code &
bellard84b7b8e2005-11-28 21:19:04 +00001417 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1418 tlb_entry->addr_read = -1;
1419 tlb_entry->addr_write = -1;
1420 tlb_entry->addr_code = -1;
1421 }
bellard61382a52003-10-27 21:22:23 +00001422}
1423
bellard2e126692004-04-25 21:28:44 +00001424void tlb_flush_page(CPUState *env, target_ulong addr)
bellard33417e72003-08-10 21:47:01 +00001425{
bellard8a40a182005-11-20 10:35:40 +00001426 int i;
bellard9fa3e852004-01-04 18:06:42 +00001427 TranslationBlock *tb;
bellard01243112004-01-04 15:48:17 +00001428
bellard9fa3e852004-01-04 18:06:42 +00001429#if defined(DEBUG_TLB)
bellard108c49b2005-07-24 12:55:09 +00001430 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
bellard9fa3e852004-01-04 18:06:42 +00001431#endif
bellard01243112004-01-04 15:48:17 +00001432 /* must reset current TB so that interrupts cannot modify the
1433 links while we are modifying them */
1434 env->current_tb = NULL;
bellard33417e72003-08-10 21:47:01 +00001435
bellard61382a52003-10-27 21:22:23 +00001436 addr &= TARGET_PAGE_MASK;
bellard33417e72003-08-10 21:47:01 +00001437 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard84b7b8e2005-11-28 21:19:04 +00001438 tlb_flush_entry(&env->tlb_table[0][i], addr);
1439 tlb_flush_entry(&env->tlb_table[1][i], addr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001440#if (NB_MMU_MODES >= 3)
1441 tlb_flush_entry(&env->tlb_table[2][i], addr);
1442#if (NB_MMU_MODES == 4)
1443 tlb_flush_entry(&env->tlb_table[3][i], addr);
1444#endif
1445#endif
bellard01243112004-01-04 15:48:17 +00001446
pbrookb362e5e2006-11-12 20:40:55 +00001447 /* Discard jump cache entries for any tb which might potentially
1448 overlap the flushed page. */
1449 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1450 memset (&env->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(tb));
1451
1452 i = tb_jmp_cache_hash_page(addr);
1453 memset (&env->tb_jmp_cache[i], 0, TB_JMP_PAGE_SIZE * sizeof(tb));
bellard9fa3e852004-01-04 18:06:42 +00001454
bellard01243112004-01-04 15:48:17 +00001455#if !defined(CONFIG_SOFTMMU)
bellard9fa3e852004-01-04 18:06:42 +00001456 if (addr < MMAP_AREA_END)
bellard01243112004-01-04 15:48:17 +00001457 munmap((void *)addr, TARGET_PAGE_SIZE);
bellard61382a52003-10-27 21:22:23 +00001458#endif
bellard0a962c02005-02-10 22:00:27 +00001459#ifdef USE_KQEMU
1460 if (env->kqemu_enabled) {
1461 kqemu_flush_page(env, addr);
1462 }
1463#endif
bellard9fa3e852004-01-04 18:06:42 +00001464}
1465
bellard9fa3e852004-01-04 18:06:42 +00001466/* update the TLBs so that writes to code in the virtual page 'addr'
1467 can be detected */
bellard6a00d602005-11-21 23:25:50 +00001468static void tlb_protect_code(ram_addr_t ram_addr)
bellard61382a52003-10-27 21:22:23 +00001469{
ths5fafdf22007-09-16 21:08:06 +00001470 cpu_physical_memory_reset_dirty(ram_addr,
bellard6a00d602005-11-21 23:25:50 +00001471 ram_addr + TARGET_PAGE_SIZE,
1472 CODE_DIRTY_FLAG);
bellard9fa3e852004-01-04 18:06:42 +00001473}
1474
bellard9fa3e852004-01-04 18:06:42 +00001475/* update the TLB so that writes in physical page 'phys_addr' are no longer
bellard3a7d9292005-08-21 09:26:42 +00001476 tested for self modifying code */
ths5fafdf22007-09-16 21:08:06 +00001477static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +00001478 target_ulong vaddr)
bellard9fa3e852004-01-04 18:06:42 +00001479{
bellard3a7d9292005-08-21 09:26:42 +00001480 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
bellard1ccde1c2004-02-06 19:46:14 +00001481}
1482
ths5fafdf22007-09-16 21:08:06 +00001483static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
bellard1ccde1c2004-02-06 19:46:14 +00001484 unsigned long start, unsigned long length)
1485{
1486 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00001487 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1488 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00001489 if ((addr - start) < length) {
bellard84b7b8e2005-11-28 21:19:04 +00001490 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_NOTDIRTY;
bellard1ccde1c2004-02-06 19:46:14 +00001491 }
1492 }
1493}
1494
bellard3a7d9292005-08-21 09:26:42 +00001495void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +00001496 int dirty_flags)
bellard1ccde1c2004-02-06 19:46:14 +00001497{
1498 CPUState *env;
bellard4f2ac232004-04-26 19:44:02 +00001499 unsigned long length, start1;
bellard0a962c02005-02-10 22:00:27 +00001500 int i, mask, len;
1501 uint8_t *p;
bellard1ccde1c2004-02-06 19:46:14 +00001502
1503 start &= TARGET_PAGE_MASK;
1504 end = TARGET_PAGE_ALIGN(end);
1505
1506 length = end - start;
1507 if (length == 0)
1508 return;
bellard0a962c02005-02-10 22:00:27 +00001509 len = length >> TARGET_PAGE_BITS;
bellard3a7d9292005-08-21 09:26:42 +00001510#ifdef USE_KQEMU
bellard6a00d602005-11-21 23:25:50 +00001511 /* XXX: should not depend on cpu context */
1512 env = first_cpu;
bellard3a7d9292005-08-21 09:26:42 +00001513 if (env->kqemu_enabled) {
bellardf23db162005-08-21 19:12:28 +00001514 ram_addr_t addr;
1515 addr = start;
1516 for(i = 0; i < len; i++) {
1517 kqemu_set_notdirty(env, addr);
1518 addr += TARGET_PAGE_SIZE;
1519 }
bellard3a7d9292005-08-21 09:26:42 +00001520 }
1521#endif
bellardf23db162005-08-21 19:12:28 +00001522 mask = ~dirty_flags;
1523 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1524 for(i = 0; i < len; i++)
1525 p[i] &= mask;
1526
bellard1ccde1c2004-02-06 19:46:14 +00001527 /* we modify the TLB cache so that the dirty bit will be set again
1528 when accessing the range */
bellard59817cc2004-02-16 22:01:13 +00001529 start1 = start + (unsigned long)phys_ram_base;
bellard6a00d602005-11-21 23:25:50 +00001530 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1531 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001532 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
bellard6a00d602005-11-21 23:25:50 +00001533 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001534 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
j_mayer6fa4cea2007-04-05 06:43:27 +00001535#if (NB_MMU_MODES >= 3)
1536 for(i = 0; i < CPU_TLB_SIZE; i++)
1537 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1538#if (NB_MMU_MODES == 4)
1539 for(i = 0; i < CPU_TLB_SIZE; i++)
1540 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1541#endif
1542#endif
bellard6a00d602005-11-21 23:25:50 +00001543 }
bellard59817cc2004-02-16 22:01:13 +00001544
1545#if !defined(CONFIG_SOFTMMU)
1546 /* XXX: this is expensive */
1547 {
1548 VirtPageDesc *p;
1549 int j;
1550 target_ulong addr;
1551
1552 for(i = 0; i < L1_SIZE; i++) {
1553 p = l1_virt_map[i];
1554 if (p) {
1555 addr = i << (TARGET_PAGE_BITS + L2_BITS);
1556 for(j = 0; j < L2_SIZE; j++) {
1557 if (p->valid_tag == virt_valid_tag &&
1558 p->phys_addr >= start && p->phys_addr < end &&
1559 (p->prot & PROT_WRITE)) {
1560 if (addr < MMAP_AREA_END) {
ths5fafdf22007-09-16 21:08:06 +00001561 mprotect((void *)addr, TARGET_PAGE_SIZE,
bellard59817cc2004-02-16 22:01:13 +00001562 p->prot & ~PROT_WRITE);
1563 }
1564 }
1565 addr += TARGET_PAGE_SIZE;
1566 p++;
1567 }
1568 }
1569 }
1570 }
1571#endif
bellard1ccde1c2004-02-06 19:46:14 +00001572}
1573
bellard3a7d9292005-08-21 09:26:42 +00001574static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1575{
1576 ram_addr_t ram_addr;
1577
bellard84b7b8e2005-11-28 21:19:04 +00001578 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
ths5fafdf22007-09-16 21:08:06 +00001579 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
bellard3a7d9292005-08-21 09:26:42 +00001580 tlb_entry->addend - (unsigned long)phys_ram_base;
1581 if (!cpu_physical_memory_is_dirty(ram_addr)) {
bellard84b7b8e2005-11-28 21:19:04 +00001582 tlb_entry->addr_write |= IO_MEM_NOTDIRTY;
bellard3a7d9292005-08-21 09:26:42 +00001583 }
1584 }
1585}
1586
1587/* update the TLB according to the current state of the dirty bits */
1588void cpu_tlb_update_dirty(CPUState *env)
1589{
1590 int i;
1591 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001592 tlb_update_dirty(&env->tlb_table[0][i]);
bellard3a7d9292005-08-21 09:26:42 +00001593 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001594 tlb_update_dirty(&env->tlb_table[1][i]);
j_mayer6fa4cea2007-04-05 06:43:27 +00001595#if (NB_MMU_MODES >= 3)
1596 for(i = 0; i < CPU_TLB_SIZE; i++)
1597 tlb_update_dirty(&env->tlb_table[2][i]);
1598#if (NB_MMU_MODES == 4)
1599 for(i = 0; i < CPU_TLB_SIZE; i++)
1600 tlb_update_dirty(&env->tlb_table[3][i]);
1601#endif
1602#endif
bellard3a7d9292005-08-21 09:26:42 +00001603}
1604
ths5fafdf22007-09-16 21:08:06 +00001605static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry,
bellard108c49b2005-07-24 12:55:09 +00001606 unsigned long start)
bellard1ccde1c2004-02-06 19:46:14 +00001607{
1608 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00001609 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_NOTDIRTY) {
1610 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00001611 if (addr == start) {
bellard84b7b8e2005-11-28 21:19:04 +00001612 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | IO_MEM_RAM;
bellard1ccde1c2004-02-06 19:46:14 +00001613 }
1614 }
1615}
1616
1617/* update the TLB corresponding to virtual page vaddr and phys addr
1618 addr so that it is no longer dirty */
bellard6a00d602005-11-21 23:25:50 +00001619static inline void tlb_set_dirty(CPUState *env,
1620 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001621{
bellard1ccde1c2004-02-06 19:46:14 +00001622 int i;
1623
bellard1ccde1c2004-02-06 19:46:14 +00001624 addr &= TARGET_PAGE_MASK;
1625 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard84b7b8e2005-11-28 21:19:04 +00001626 tlb_set_dirty1(&env->tlb_table[0][i], addr);
1627 tlb_set_dirty1(&env->tlb_table[1][i], addr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001628#if (NB_MMU_MODES >= 3)
1629 tlb_set_dirty1(&env->tlb_table[2][i], addr);
1630#if (NB_MMU_MODES == 4)
1631 tlb_set_dirty1(&env->tlb_table[3][i], addr);
1632#endif
1633#endif
bellard9fa3e852004-01-04 18:06:42 +00001634}
1635
bellard59817cc2004-02-16 22:01:13 +00001636/* add a new TLB entry. At most one entry for a given virtual address
1637 is permitted. Return 0 if OK or 2 if the page could not be mapped
1638 (can only happen in non SOFTMMU mode for I/O pages or pages
1639 conflicting with the host address space). */
ths5fafdf22007-09-16 21:08:06 +00001640int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1641 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00001642 int mmu_idx, int is_softmmu)
bellard9fa3e852004-01-04 18:06:42 +00001643{
bellard92e873b2004-05-21 14:52:29 +00001644 PhysPageDesc *p;
bellard4f2ac232004-04-26 19:44:02 +00001645 unsigned long pd;
bellard9fa3e852004-01-04 18:06:42 +00001646 unsigned int index;
bellard4f2ac232004-04-26 19:44:02 +00001647 target_ulong address;
bellard108c49b2005-07-24 12:55:09 +00001648 target_phys_addr_t addend;
bellard9fa3e852004-01-04 18:06:42 +00001649 int ret;
bellard84b7b8e2005-11-28 21:19:04 +00001650 CPUTLBEntry *te;
pbrook6658ffb2007-03-16 23:58:11 +00001651 int i;
bellard9fa3e852004-01-04 18:06:42 +00001652
bellard92e873b2004-05-21 14:52:29 +00001653 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001654 if (!p) {
1655 pd = IO_MEM_UNASSIGNED;
bellard9fa3e852004-01-04 18:06:42 +00001656 } else {
1657 pd = p->phys_offset;
bellard9fa3e852004-01-04 18:06:42 +00001658 }
1659#if defined(DEBUG_TLB)
j_mayer6ebbf392007-10-14 07:07:08 +00001660 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1661 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
bellard9fa3e852004-01-04 18:06:42 +00001662#endif
1663
1664 ret = 0;
1665#if !defined(CONFIG_SOFTMMU)
ths5fafdf22007-09-16 21:08:06 +00001666 if (is_softmmu)
bellard9fa3e852004-01-04 18:06:42 +00001667#endif
1668 {
bellard2a4188a2006-06-25 21:54:59 +00001669 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
bellard9fa3e852004-01-04 18:06:42 +00001670 /* IO memory case */
1671 address = vaddr | pd;
1672 addend = paddr;
1673 } else {
1674 /* standard memory */
1675 address = vaddr;
1676 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1677 }
pbrook6658ffb2007-03-16 23:58:11 +00001678
1679 /* Make accesses to pages with watchpoints go via the
1680 watchpoint trap routines. */
1681 for (i = 0; i < env->nb_watchpoints; i++) {
1682 if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) {
1683 if (address & ~TARGET_PAGE_MASK) {
balrogd79acba2007-06-26 20:01:13 +00001684 env->watchpoint[i].addend = 0;
pbrook6658ffb2007-03-16 23:58:11 +00001685 address = vaddr | io_mem_watch;
1686 } else {
balrogd79acba2007-06-26 20:01:13 +00001687 env->watchpoint[i].addend = pd - paddr +
1688 (unsigned long) phys_ram_base;
pbrook6658ffb2007-03-16 23:58:11 +00001689 /* TODO: Figure out how to make read watchpoints coexist
1690 with code. */
1691 pd = (pd & TARGET_PAGE_MASK) | io_mem_watch | IO_MEM_ROMD;
1692 }
1693 }
1694 }
balrogd79acba2007-06-26 20:01:13 +00001695
bellard90f18422005-07-24 10:17:31 +00001696 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard9fa3e852004-01-04 18:06:42 +00001697 addend -= vaddr;
j_mayer6ebbf392007-10-14 07:07:08 +00001698 te = &env->tlb_table[mmu_idx][index];
bellard84b7b8e2005-11-28 21:19:04 +00001699 te->addend = addend;
bellard67b915a2004-03-31 23:37:16 +00001700 if (prot & PAGE_READ) {
bellard84b7b8e2005-11-28 21:19:04 +00001701 te->addr_read = address;
bellard9fa3e852004-01-04 18:06:42 +00001702 } else {
bellard84b7b8e2005-11-28 21:19:04 +00001703 te->addr_read = -1;
1704 }
1705 if (prot & PAGE_EXEC) {
1706 te->addr_code = address;
1707 } else {
1708 te->addr_code = -1;
bellard9fa3e852004-01-04 18:06:42 +00001709 }
bellard67b915a2004-03-31 23:37:16 +00001710 if (prot & PAGE_WRITE) {
ths5fafdf22007-09-16 21:08:06 +00001711 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
bellard856074e2006-07-04 09:47:34 +00001712 (pd & IO_MEM_ROMD)) {
1713 /* write access calls the I/O callback */
ths5fafdf22007-09-16 21:08:06 +00001714 te->addr_write = vaddr |
bellard856074e2006-07-04 09:47:34 +00001715 (pd & ~(TARGET_PAGE_MASK | IO_MEM_ROMD));
ths5fafdf22007-09-16 21:08:06 +00001716 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
bellard1ccde1c2004-02-06 19:46:14 +00001717 !cpu_physical_memory_is_dirty(pd)) {
bellard84b7b8e2005-11-28 21:19:04 +00001718 te->addr_write = vaddr | IO_MEM_NOTDIRTY;
bellard9fa3e852004-01-04 18:06:42 +00001719 } else {
bellard84b7b8e2005-11-28 21:19:04 +00001720 te->addr_write = address;
bellard9fa3e852004-01-04 18:06:42 +00001721 }
1722 } else {
bellard84b7b8e2005-11-28 21:19:04 +00001723 te->addr_write = -1;
bellard9fa3e852004-01-04 18:06:42 +00001724 }
1725 }
1726#if !defined(CONFIG_SOFTMMU)
1727 else {
1728 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM) {
1729 /* IO access: no mapping is done as it will be handled by the
1730 soft MMU */
1731 if (!(env->hflags & HF_SOFTMMU_MASK))
1732 ret = 2;
1733 } else {
1734 void *map_addr;
bellard9fa3e852004-01-04 18:06:42 +00001735
bellard59817cc2004-02-16 22:01:13 +00001736 if (vaddr >= MMAP_AREA_END) {
1737 ret = 2;
1738 } else {
1739 if (prot & PROT_WRITE) {
ths5fafdf22007-09-16 21:08:06 +00001740 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
bellardd720b932004-04-25 17:57:43 +00001741#if defined(TARGET_HAS_SMC) || 1
bellard59817cc2004-02-16 22:01:13 +00001742 first_tb ||
bellardd720b932004-04-25 17:57:43 +00001743#endif
ths5fafdf22007-09-16 21:08:06 +00001744 ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
bellard59817cc2004-02-16 22:01:13 +00001745 !cpu_physical_memory_is_dirty(pd))) {
1746 /* ROM: we do as if code was inside */
1747 /* if code is present, we only map as read only and save the
1748 original mapping */
1749 VirtPageDesc *vp;
ths3b46e622007-09-17 08:09:54 +00001750
bellard90f18422005-07-24 10:17:31 +00001751 vp = virt_page_find_alloc(vaddr >> TARGET_PAGE_BITS, 1);
bellard59817cc2004-02-16 22:01:13 +00001752 vp->phys_addr = pd;
1753 vp->prot = prot;
1754 vp->valid_tag = virt_valid_tag;
1755 prot &= ~PAGE_WRITE;
1756 }
bellard9fa3e852004-01-04 18:06:42 +00001757 }
ths5fafdf22007-09-16 21:08:06 +00001758 map_addr = mmap((void *)vaddr, TARGET_PAGE_SIZE, prot,
bellard59817cc2004-02-16 22:01:13 +00001759 MAP_SHARED | MAP_FIXED, phys_ram_fd, (pd & TARGET_PAGE_MASK));
1760 if (map_addr == MAP_FAILED) {
1761 cpu_abort(env, "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
1762 paddr, vaddr);
1763 }
bellard9fa3e852004-01-04 18:06:42 +00001764 }
1765 }
1766 }
1767#endif
1768 return ret;
1769}
1770
1771/* called from signal handler: invalidate the code and unprotect the
1772 page. Return TRUE if the fault was succesfully handled. */
pbrook53a59602006-03-25 19:31:22 +00001773int page_unprotect(target_ulong addr, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001774{
1775#if !defined(CONFIG_SOFTMMU)
1776 VirtPageDesc *vp;
1777
1778#if defined(DEBUG_TLB)
1779 printf("page_unprotect: addr=0x%08x\n", addr);
1780#endif
1781 addr &= TARGET_PAGE_MASK;
bellard59817cc2004-02-16 22:01:13 +00001782
1783 /* if it is not mapped, no need to worry here */
1784 if (addr >= MMAP_AREA_END)
1785 return 0;
bellard9fa3e852004-01-04 18:06:42 +00001786 vp = virt_page_find(addr >> TARGET_PAGE_BITS);
1787 if (!vp)
1788 return 0;
1789 /* NOTE: in this case, validate_tag is _not_ tested as it
1790 validates only the code TLB */
1791 if (vp->valid_tag != virt_valid_tag)
1792 return 0;
1793 if (!(vp->prot & PAGE_WRITE))
1794 return 0;
1795#if defined(DEBUG_TLB)
ths5fafdf22007-09-16 21:08:06 +00001796 printf("page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x\n",
bellard9fa3e852004-01-04 18:06:42 +00001797 addr, vp->phys_addr, vp->prot);
1798#endif
bellard59817cc2004-02-16 22:01:13 +00001799 if (mprotect((void *)addr, TARGET_PAGE_SIZE, vp->prot) < 0)
1800 cpu_abort(cpu_single_env, "error mprotect addr=0x%lx prot=%d\n",
1801 (unsigned long)addr, vp->prot);
bellardd720b932004-04-25 17:57:43 +00001802 /* set the dirty bit */
bellard0a962c02005-02-10 22:00:27 +00001803 phys_ram_dirty[vp->phys_addr >> TARGET_PAGE_BITS] = 0xff;
bellardd720b932004-04-25 17:57:43 +00001804 /* flush the code inside */
1805 tb_invalidate_phys_page(vp->phys_addr, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00001806 return 1;
1807#else
1808 return 0;
1809#endif
bellard33417e72003-08-10 21:47:01 +00001810}
1811
bellard01243112004-01-04 15:48:17 +00001812#else
1813
bellardee8b7022004-02-03 23:35:10 +00001814void tlb_flush(CPUState *env, int flush_global)
bellard01243112004-01-04 15:48:17 +00001815{
1816}
1817
bellard2e126692004-04-25 21:28:44 +00001818void tlb_flush_page(CPUState *env, target_ulong addr)
bellard01243112004-01-04 15:48:17 +00001819{
1820}
1821
ths5fafdf22007-09-16 21:08:06 +00001822int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1823 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00001824 int mmu_idx, int is_softmmu)
bellard33417e72003-08-10 21:47:01 +00001825{
bellard9fa3e852004-01-04 18:06:42 +00001826 return 0;
1827}
bellard33417e72003-08-10 21:47:01 +00001828
bellard9fa3e852004-01-04 18:06:42 +00001829/* dump memory mappings */
1830void page_dump(FILE *f)
1831{
1832 unsigned long start, end;
1833 int i, j, prot, prot1;
1834 PageDesc *p;
1835
1836 fprintf(f, "%-8s %-8s %-8s %s\n",
1837 "start", "end", "size", "prot");
1838 start = -1;
1839 end = -1;
1840 prot = 0;
1841 for(i = 0; i <= L1_SIZE; i++) {
1842 if (i < L1_SIZE)
1843 p = l1_map[i];
1844 else
1845 p = NULL;
1846 for(j = 0;j < L2_SIZE; j++) {
1847 if (!p)
1848 prot1 = 0;
1849 else
1850 prot1 = p[j].flags;
1851 if (prot1 != prot) {
1852 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
1853 if (start != -1) {
1854 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
ths5fafdf22007-09-16 21:08:06 +00001855 start, end, end - start,
bellard9fa3e852004-01-04 18:06:42 +00001856 prot & PAGE_READ ? 'r' : '-',
1857 prot & PAGE_WRITE ? 'w' : '-',
1858 prot & PAGE_EXEC ? 'x' : '-');
1859 }
1860 if (prot1 != 0)
1861 start = end;
1862 else
1863 start = -1;
1864 prot = prot1;
1865 }
1866 if (!p)
1867 break;
1868 }
bellard33417e72003-08-10 21:47:01 +00001869 }
bellard33417e72003-08-10 21:47:01 +00001870}
1871
pbrook53a59602006-03-25 19:31:22 +00001872int page_get_flags(target_ulong address)
bellard33417e72003-08-10 21:47:01 +00001873{
bellard9fa3e852004-01-04 18:06:42 +00001874 PageDesc *p;
1875
1876 p = page_find(address >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00001877 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00001878 return 0;
1879 return p->flags;
bellard33417e72003-08-10 21:47:01 +00001880}
1881
bellard9fa3e852004-01-04 18:06:42 +00001882/* modify the flags of a page and invalidate the code if
1883 necessary. The flag PAGE_WRITE_ORG is positionned automatically
1884 depending on PAGE_WRITE */
pbrook53a59602006-03-25 19:31:22 +00001885void page_set_flags(target_ulong start, target_ulong end, int flags)
bellard9fa3e852004-01-04 18:06:42 +00001886{
1887 PageDesc *p;
pbrook53a59602006-03-25 19:31:22 +00001888 target_ulong addr;
bellard9fa3e852004-01-04 18:06:42 +00001889
1890 start = start & TARGET_PAGE_MASK;
1891 end = TARGET_PAGE_ALIGN(end);
1892 if (flags & PAGE_WRITE)
1893 flags |= PAGE_WRITE_ORG;
1894 spin_lock(&tb_lock);
1895 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
1896 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
1897 /* if the write protection is set, then we invalidate the code
1898 inside */
ths5fafdf22007-09-16 21:08:06 +00001899 if (!(p->flags & PAGE_WRITE) &&
bellard9fa3e852004-01-04 18:06:42 +00001900 (flags & PAGE_WRITE) &&
1901 p->first_tb) {
bellardd720b932004-04-25 17:57:43 +00001902 tb_invalidate_phys_page(addr, 0, NULL);
bellard9fa3e852004-01-04 18:06:42 +00001903 }
1904 p->flags = flags;
1905 }
1906 spin_unlock(&tb_lock);
1907}
1908
ths3d97b402007-11-02 19:02:07 +00001909int page_check_range(target_ulong start, target_ulong len, int flags)
1910{
1911 PageDesc *p;
1912 target_ulong end;
1913 target_ulong addr;
1914
1915 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
1916 start = start & TARGET_PAGE_MASK;
1917
1918 if( end < start )
1919 /* we've wrapped around */
1920 return -1;
1921 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
1922 p = page_find(addr >> TARGET_PAGE_BITS);
1923 if( !p )
1924 return -1;
1925 if( !(p->flags & PAGE_VALID) )
1926 return -1;
1927
bellarddae32702007-11-14 10:51:00 +00001928 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
ths3d97b402007-11-02 19:02:07 +00001929 return -1;
bellarddae32702007-11-14 10:51:00 +00001930 if (flags & PAGE_WRITE) {
1931 if (!(p->flags & PAGE_WRITE_ORG))
1932 return -1;
1933 /* unprotect the page if it was put read-only because it
1934 contains translated code */
1935 if (!(p->flags & PAGE_WRITE)) {
1936 if (!page_unprotect(addr, 0, NULL))
1937 return -1;
1938 }
1939 return 0;
1940 }
ths3d97b402007-11-02 19:02:07 +00001941 }
1942 return 0;
1943}
1944
bellard9fa3e852004-01-04 18:06:42 +00001945/* called from signal handler: invalidate the code and unprotect the
1946 page. Return TRUE if the fault was succesfully handled. */
pbrook53a59602006-03-25 19:31:22 +00001947int page_unprotect(target_ulong address, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001948{
1949 unsigned int page_index, prot, pindex;
1950 PageDesc *p, *p1;
pbrook53a59602006-03-25 19:31:22 +00001951 target_ulong host_start, host_end, addr;
bellard9fa3e852004-01-04 18:06:42 +00001952
bellard83fb7ad2004-07-05 21:25:26 +00001953 host_start = address & qemu_host_page_mask;
bellard9fa3e852004-01-04 18:06:42 +00001954 page_index = host_start >> TARGET_PAGE_BITS;
1955 p1 = page_find(page_index);
1956 if (!p1)
1957 return 0;
bellard83fb7ad2004-07-05 21:25:26 +00001958 host_end = host_start + qemu_host_page_size;
bellard9fa3e852004-01-04 18:06:42 +00001959 p = p1;
1960 prot = 0;
1961 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
1962 prot |= p->flags;
1963 p++;
1964 }
1965 /* if the page was really writable, then we change its
1966 protection back to writable */
1967 if (prot & PAGE_WRITE_ORG) {
1968 pindex = (address - host_start) >> TARGET_PAGE_BITS;
1969 if (!(p1[pindex].flags & PAGE_WRITE)) {
ths5fafdf22007-09-16 21:08:06 +00001970 mprotect((void *)g2h(host_start), qemu_host_page_size,
bellard9fa3e852004-01-04 18:06:42 +00001971 (prot & PAGE_BITS) | PAGE_WRITE);
1972 p1[pindex].flags |= PAGE_WRITE;
1973 /* and since the content will be modified, we must invalidate
1974 the corresponding translated code. */
bellardd720b932004-04-25 17:57:43 +00001975 tb_invalidate_phys_page(address, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00001976#ifdef DEBUG_TB_CHECK
1977 tb_invalidate_check(address);
1978#endif
1979 return 1;
1980 }
1981 }
1982 return 0;
1983}
1984
bellard6a00d602005-11-21 23:25:50 +00001985static inline void tlb_set_dirty(CPUState *env,
1986 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001987{
1988}
bellard9fa3e852004-01-04 18:06:42 +00001989#endif /* defined(CONFIG_USER_ONLY) */
1990
blueswir1db7b5422007-05-26 17:36:03 +00001991static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
aurel3200f82b82008-04-27 21:12:55 +00001992 ram_addr_t memory);
1993static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
1994 ram_addr_t orig_memory);
blueswir1db7b5422007-05-26 17:36:03 +00001995#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
1996 need_subpage) \
1997 do { \
1998 if (addr > start_addr) \
1999 start_addr2 = 0; \
2000 else { \
2001 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2002 if (start_addr2 > 0) \
2003 need_subpage = 1; \
2004 } \
2005 \
blueswir149e9fba2007-05-30 17:25:06 +00002006 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
blueswir1db7b5422007-05-26 17:36:03 +00002007 end_addr2 = TARGET_PAGE_SIZE - 1; \
2008 else { \
2009 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2010 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2011 need_subpage = 1; \
2012 } \
2013 } while (0)
2014
bellard33417e72003-08-10 21:47:01 +00002015/* register physical memory. 'size' must be a multiple of the target
2016 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2017 io memory page */
ths5fafdf22007-09-16 21:08:06 +00002018void cpu_register_physical_memory(target_phys_addr_t start_addr,
aurel3200f82b82008-04-27 21:12:55 +00002019 ram_addr_t size,
2020 ram_addr_t phys_offset)
bellard33417e72003-08-10 21:47:01 +00002021{
bellard108c49b2005-07-24 12:55:09 +00002022 target_phys_addr_t addr, end_addr;
bellard92e873b2004-05-21 14:52:29 +00002023 PhysPageDesc *p;
bellard9d420372006-06-25 22:25:22 +00002024 CPUState *env;
aurel3200f82b82008-04-27 21:12:55 +00002025 ram_addr_t orig_size = size;
blueswir1db7b5422007-05-26 17:36:03 +00002026 void *subpage;
bellard33417e72003-08-10 21:47:01 +00002027
bellard5fd386f2004-05-23 21:11:22 +00002028 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
blueswir149e9fba2007-05-30 17:25:06 +00002029 end_addr = start_addr + (target_phys_addr_t)size;
2030 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
blueswir1db7b5422007-05-26 17:36:03 +00002031 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2032 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
aurel3200f82b82008-04-27 21:12:55 +00002033 ram_addr_t orig_memory = p->phys_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002034 target_phys_addr_t start_addr2, end_addr2;
2035 int need_subpage = 0;
2036
2037 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2038 need_subpage);
blueswir14254fab2008-01-01 16:57:19 +00002039 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002040 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2041 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2042 &p->phys_offset, orig_memory);
2043 } else {
2044 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2045 >> IO_MEM_SHIFT];
2046 }
2047 subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2048 } else {
2049 p->phys_offset = phys_offset;
2050 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2051 (phys_offset & IO_MEM_ROMD))
2052 phys_offset += TARGET_PAGE_SIZE;
2053 }
2054 } else {
2055 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2056 p->phys_offset = phys_offset;
2057 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2058 (phys_offset & IO_MEM_ROMD))
2059 phys_offset += TARGET_PAGE_SIZE;
2060 else {
2061 target_phys_addr_t start_addr2, end_addr2;
2062 int need_subpage = 0;
2063
2064 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2065 end_addr2, need_subpage);
2066
blueswir14254fab2008-01-01 16:57:19 +00002067 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002068 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2069 &p->phys_offset, IO_MEM_UNASSIGNED);
2070 subpage_register(subpage, start_addr2, end_addr2,
2071 phys_offset);
2072 }
2073 }
2074 }
bellard33417e72003-08-10 21:47:01 +00002075 }
ths3b46e622007-09-17 08:09:54 +00002076
bellard9d420372006-06-25 22:25:22 +00002077 /* since each CPU stores ram addresses in its TLB cache, we must
2078 reset the modified entries */
2079 /* XXX: slow ! */
2080 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2081 tlb_flush(env, 1);
2082 }
bellard33417e72003-08-10 21:47:01 +00002083}
2084
bellardba863452006-09-24 18:41:10 +00002085/* XXX: temporary until new memory mapping API */
aurel3200f82b82008-04-27 21:12:55 +00002086ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
bellardba863452006-09-24 18:41:10 +00002087{
2088 PhysPageDesc *p;
2089
2090 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2091 if (!p)
2092 return IO_MEM_UNASSIGNED;
2093 return p->phys_offset;
2094}
2095
bellarde9a1ab12007-02-08 23:08:38 +00002096/* XXX: better than nothing */
aurel3200f82b82008-04-27 21:12:55 +00002097ram_addr_t qemu_ram_alloc(ram_addr_t size)
bellarde9a1ab12007-02-08 23:08:38 +00002098{
2099 ram_addr_t addr;
balrog7fb4fdc2008-04-24 17:59:27 +00002100 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
aurel3200f82b82008-04-27 21:12:55 +00002101 fprintf(stderr, "Not enough memory (requested_size = %lu, max memory = %ld)\n",
aurel3203875442008-04-22 20:45:18 +00002102 size, phys_ram_size);
bellarde9a1ab12007-02-08 23:08:38 +00002103 abort();
2104 }
2105 addr = phys_ram_alloc_offset;
2106 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2107 return addr;
2108}
2109
2110void qemu_ram_free(ram_addr_t addr)
2111{
2112}
2113
bellarda4193c82004-06-03 14:01:43 +00002114static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
bellard33417e72003-08-10 21:47:01 +00002115{
pbrook67d3b952006-12-18 05:03:52 +00002116#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002117 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
pbrook67d3b952006-12-18 05:03:52 +00002118#endif
blueswir1b4f0a312007-05-06 17:59:24 +00002119#ifdef TARGET_SPARC
blueswir16c36d3f2007-05-17 19:30:10 +00002120 do_unassigned_access(addr, 0, 0, 0);
thsf1ccf902007-10-08 13:16:14 +00002121#elif TARGET_CRIS
2122 do_unassigned_access(addr, 0, 0, 0);
blueswir1b4f0a312007-05-06 17:59:24 +00002123#endif
bellard33417e72003-08-10 21:47:01 +00002124 return 0;
2125}
2126
bellarda4193c82004-06-03 14:01:43 +00002127static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard33417e72003-08-10 21:47:01 +00002128{
pbrook67d3b952006-12-18 05:03:52 +00002129#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002130 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
pbrook67d3b952006-12-18 05:03:52 +00002131#endif
blueswir1b4f0a312007-05-06 17:59:24 +00002132#ifdef TARGET_SPARC
blueswir16c36d3f2007-05-17 19:30:10 +00002133 do_unassigned_access(addr, 1, 0, 0);
thsf1ccf902007-10-08 13:16:14 +00002134#elif TARGET_CRIS
2135 do_unassigned_access(addr, 1, 0, 0);
blueswir1b4f0a312007-05-06 17:59:24 +00002136#endif
bellard33417e72003-08-10 21:47:01 +00002137}
2138
2139static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2140 unassigned_mem_readb,
2141 unassigned_mem_readb,
2142 unassigned_mem_readb,
2143};
2144
2145static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2146 unassigned_mem_writeb,
2147 unassigned_mem_writeb,
2148 unassigned_mem_writeb,
2149};
2150
bellarda4193c82004-06-03 14:01:43 +00002151static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002152{
bellard3a7d9292005-08-21 09:26:42 +00002153 unsigned long ram_addr;
2154 int dirty_flags;
2155 ram_addr = addr - (unsigned long)phys_ram_base;
2156 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2157 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2158#if !defined(CONFIG_USER_ONLY)
2159 tb_invalidate_phys_page_fast(ram_addr, 1);
2160 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2161#endif
2162 }
bellardc27004e2005-01-03 23:35:10 +00002163 stb_p((uint8_t *)(long)addr, val);
bellardf32fc642006-02-08 22:43:39 +00002164#ifdef USE_KQEMU
2165 if (cpu_single_env->kqemu_enabled &&
2166 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2167 kqemu_modify_page(cpu_single_env, ram_addr);
2168#endif
bellardf23db162005-08-21 19:12:28 +00002169 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2170 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2171 /* we remove the notdirty callback only if the code has been
2172 flushed */
2173 if (dirty_flags == 0xff)
bellard6a00d602005-11-21 23:25:50 +00002174 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002175}
2176
bellarda4193c82004-06-03 14:01:43 +00002177static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002178{
bellard3a7d9292005-08-21 09:26:42 +00002179 unsigned long ram_addr;
2180 int dirty_flags;
2181 ram_addr = addr - (unsigned long)phys_ram_base;
2182 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2183 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2184#if !defined(CONFIG_USER_ONLY)
2185 tb_invalidate_phys_page_fast(ram_addr, 2);
2186 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2187#endif
2188 }
bellardc27004e2005-01-03 23:35:10 +00002189 stw_p((uint8_t *)(long)addr, val);
bellardf32fc642006-02-08 22:43:39 +00002190#ifdef USE_KQEMU
2191 if (cpu_single_env->kqemu_enabled &&
2192 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2193 kqemu_modify_page(cpu_single_env, ram_addr);
2194#endif
bellardf23db162005-08-21 19:12:28 +00002195 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2196 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2197 /* we remove the notdirty callback only if the code has been
2198 flushed */
2199 if (dirty_flags == 0xff)
bellard6a00d602005-11-21 23:25:50 +00002200 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002201}
2202
bellarda4193c82004-06-03 14:01:43 +00002203static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002204{
bellard3a7d9292005-08-21 09:26:42 +00002205 unsigned long ram_addr;
2206 int dirty_flags;
2207 ram_addr = addr - (unsigned long)phys_ram_base;
2208 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2209 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2210#if !defined(CONFIG_USER_ONLY)
2211 tb_invalidate_phys_page_fast(ram_addr, 4);
2212 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2213#endif
2214 }
bellardc27004e2005-01-03 23:35:10 +00002215 stl_p((uint8_t *)(long)addr, val);
bellardf32fc642006-02-08 22:43:39 +00002216#ifdef USE_KQEMU
2217 if (cpu_single_env->kqemu_enabled &&
2218 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2219 kqemu_modify_page(cpu_single_env, ram_addr);
2220#endif
bellardf23db162005-08-21 19:12:28 +00002221 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2222 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2223 /* we remove the notdirty callback only if the code has been
2224 flushed */
2225 if (dirty_flags == 0xff)
bellard6a00d602005-11-21 23:25:50 +00002226 tlb_set_dirty(cpu_single_env, addr, cpu_single_env->mem_write_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002227}
2228
bellard3a7d9292005-08-21 09:26:42 +00002229static CPUReadMemoryFunc *error_mem_read[3] = {
2230 NULL, /* never used */
2231 NULL, /* never used */
2232 NULL, /* never used */
2233};
2234
bellard1ccde1c2004-02-06 19:46:14 +00002235static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2236 notdirty_mem_writeb,
2237 notdirty_mem_writew,
2238 notdirty_mem_writel,
2239};
2240
pbrook6658ffb2007-03-16 23:58:11 +00002241#if defined(CONFIG_SOFTMMU)
2242/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2243 so these check for a hit then pass through to the normal out-of-line
2244 phys routines. */
2245static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2246{
2247 return ldub_phys(addr);
2248}
2249
2250static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2251{
2252 return lduw_phys(addr);
2253}
2254
2255static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2256{
2257 return ldl_phys(addr);
2258}
2259
2260/* Generate a debug exception if a watchpoint has been hit.
2261 Returns the real physical address of the access. addr will be a host
balrogd79acba2007-06-26 20:01:13 +00002262 address in case of a RAM location. */
pbrook6658ffb2007-03-16 23:58:11 +00002263static target_ulong check_watchpoint(target_phys_addr_t addr)
2264{
2265 CPUState *env = cpu_single_env;
2266 target_ulong watch;
2267 target_ulong retaddr;
2268 int i;
2269
2270 retaddr = addr;
2271 for (i = 0; i < env->nb_watchpoints; i++) {
2272 watch = env->watchpoint[i].vaddr;
2273 if (((env->mem_write_vaddr ^ watch) & TARGET_PAGE_MASK) == 0) {
balrogd79acba2007-06-26 20:01:13 +00002274 retaddr = addr - env->watchpoint[i].addend;
pbrook6658ffb2007-03-16 23:58:11 +00002275 if (((addr ^ watch) & ~TARGET_PAGE_MASK) == 0) {
2276 cpu_single_env->watchpoint_hit = i + 1;
2277 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_DEBUG);
2278 break;
2279 }
2280 }
2281 }
2282 return retaddr;
2283}
2284
2285static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2286 uint32_t val)
2287{
2288 addr = check_watchpoint(addr);
2289 stb_phys(addr, val);
2290}
2291
2292static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2293 uint32_t val)
2294{
2295 addr = check_watchpoint(addr);
2296 stw_phys(addr, val);
2297}
2298
2299static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2300 uint32_t val)
2301{
2302 addr = check_watchpoint(addr);
2303 stl_phys(addr, val);
2304}
2305
2306static CPUReadMemoryFunc *watch_mem_read[3] = {
2307 watch_mem_readb,
2308 watch_mem_readw,
2309 watch_mem_readl,
2310};
2311
2312static CPUWriteMemoryFunc *watch_mem_write[3] = {
2313 watch_mem_writeb,
2314 watch_mem_writew,
2315 watch_mem_writel,
2316};
2317#endif
2318
blueswir1db7b5422007-05-26 17:36:03 +00002319static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2320 unsigned int len)
2321{
blueswir1db7b5422007-05-26 17:36:03 +00002322 uint32_t ret;
2323 unsigned int idx;
2324
2325 idx = SUBPAGE_IDX(addr - mmio->base);
2326#if defined(DEBUG_SUBPAGE)
2327 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2328 mmio, len, addr, idx);
2329#endif
blueswir13ee89922008-01-02 19:45:26 +00002330 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
blueswir1db7b5422007-05-26 17:36:03 +00002331
2332 return ret;
2333}
2334
2335static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2336 uint32_t value, unsigned int len)
2337{
blueswir1db7b5422007-05-26 17:36:03 +00002338 unsigned int idx;
2339
2340 idx = SUBPAGE_IDX(addr - mmio->base);
2341#if defined(DEBUG_SUBPAGE)
2342 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2343 mmio, len, addr, idx, value);
2344#endif
blueswir13ee89922008-01-02 19:45:26 +00002345 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
blueswir1db7b5422007-05-26 17:36:03 +00002346}
2347
2348static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2349{
2350#if defined(DEBUG_SUBPAGE)
2351 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2352#endif
2353
2354 return subpage_readlen(opaque, addr, 0);
2355}
2356
2357static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2358 uint32_t value)
2359{
2360#if defined(DEBUG_SUBPAGE)
2361 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2362#endif
2363 subpage_writelen(opaque, addr, value, 0);
2364}
2365
2366static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2367{
2368#if defined(DEBUG_SUBPAGE)
2369 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2370#endif
2371
2372 return subpage_readlen(opaque, addr, 1);
2373}
2374
2375static void subpage_writew (void *opaque, target_phys_addr_t addr,
2376 uint32_t value)
2377{
2378#if defined(DEBUG_SUBPAGE)
2379 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2380#endif
2381 subpage_writelen(opaque, addr, value, 1);
2382}
2383
2384static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2385{
2386#if defined(DEBUG_SUBPAGE)
2387 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2388#endif
2389
2390 return subpage_readlen(opaque, addr, 2);
2391}
2392
2393static void subpage_writel (void *opaque,
2394 target_phys_addr_t addr, uint32_t value)
2395{
2396#if defined(DEBUG_SUBPAGE)
2397 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2398#endif
2399 subpage_writelen(opaque, addr, value, 2);
2400}
2401
2402static CPUReadMemoryFunc *subpage_read[] = {
2403 &subpage_readb,
2404 &subpage_readw,
2405 &subpage_readl,
2406};
2407
2408static CPUWriteMemoryFunc *subpage_write[] = {
2409 &subpage_writeb,
2410 &subpage_writew,
2411 &subpage_writel,
2412};
2413
2414static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
aurel3200f82b82008-04-27 21:12:55 +00002415 ram_addr_t memory)
blueswir1db7b5422007-05-26 17:36:03 +00002416{
2417 int idx, eidx;
blueswir14254fab2008-01-01 16:57:19 +00002418 unsigned int i;
blueswir1db7b5422007-05-26 17:36:03 +00002419
2420 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2421 return -1;
2422 idx = SUBPAGE_IDX(start);
2423 eidx = SUBPAGE_IDX(end);
2424#if defined(DEBUG_SUBPAGE)
2425 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2426 mmio, start, end, idx, eidx, memory);
2427#endif
2428 memory >>= IO_MEM_SHIFT;
2429 for (; idx <= eidx; idx++) {
blueswir14254fab2008-01-01 16:57:19 +00002430 for (i = 0; i < 4; i++) {
blueswir13ee89922008-01-02 19:45:26 +00002431 if (io_mem_read[memory][i]) {
2432 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2433 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
2434 }
2435 if (io_mem_write[memory][i]) {
2436 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2437 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
2438 }
blueswir14254fab2008-01-01 16:57:19 +00002439 }
blueswir1db7b5422007-05-26 17:36:03 +00002440 }
2441
2442 return 0;
2443}
2444
aurel3200f82b82008-04-27 21:12:55 +00002445static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2446 ram_addr_t orig_memory)
blueswir1db7b5422007-05-26 17:36:03 +00002447{
2448 subpage_t *mmio;
2449 int subpage_memory;
2450
2451 mmio = qemu_mallocz(sizeof(subpage_t));
2452 if (mmio != NULL) {
2453 mmio->base = base;
2454 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
2455#if defined(DEBUG_SUBPAGE)
2456 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2457 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
2458#endif
2459 *phys = subpage_memory | IO_MEM_SUBPAGE;
2460 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
2461 }
2462
2463 return mmio;
2464}
2465
bellard33417e72003-08-10 21:47:01 +00002466static void io_mem_init(void)
2467{
bellard3a7d9292005-08-21 09:26:42 +00002468 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
bellarda4193c82004-06-03 14:01:43 +00002469 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
bellard3a7d9292005-08-21 09:26:42 +00002470 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002471 io_mem_nb = 5;
2472
pbrook6658ffb2007-03-16 23:58:11 +00002473#if defined(CONFIG_SOFTMMU)
2474 io_mem_watch = cpu_register_io_memory(-1, watch_mem_read,
2475 watch_mem_write, NULL);
2476#endif
bellard1ccde1c2004-02-06 19:46:14 +00002477 /* alloc dirty bits array */
bellard0a962c02005-02-10 22:00:27 +00002478 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
bellard3a7d9292005-08-21 09:26:42 +00002479 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002480}
2481
2482/* mem_read and mem_write are arrays of functions containing the
2483 function to access byte (index 0), word (index 1) and dword (index
blueswir13ee89922008-01-02 19:45:26 +00002484 2). Functions can be omitted with a NULL function pointer. The
2485 registered functions may be modified dynamically later.
2486 If io_index is non zero, the corresponding io zone is
blueswir14254fab2008-01-01 16:57:19 +00002487 modified. If it is zero, a new io zone is allocated. The return
2488 value can be used with cpu_register_physical_memory(). (-1) is
2489 returned if error. */
bellard33417e72003-08-10 21:47:01 +00002490int cpu_register_io_memory(int io_index,
2491 CPUReadMemoryFunc **mem_read,
bellarda4193c82004-06-03 14:01:43 +00002492 CPUWriteMemoryFunc **mem_write,
2493 void *opaque)
bellard33417e72003-08-10 21:47:01 +00002494{
blueswir14254fab2008-01-01 16:57:19 +00002495 int i, subwidth = 0;
bellard33417e72003-08-10 21:47:01 +00002496
2497 if (io_index <= 0) {
bellardb5ff1b32005-11-26 10:38:39 +00002498 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
bellard33417e72003-08-10 21:47:01 +00002499 return -1;
2500 io_index = io_mem_nb++;
2501 } else {
2502 if (io_index >= IO_MEM_NB_ENTRIES)
2503 return -1;
2504 }
bellardb5ff1b32005-11-26 10:38:39 +00002505
bellard33417e72003-08-10 21:47:01 +00002506 for(i = 0;i < 3; i++) {
blueswir14254fab2008-01-01 16:57:19 +00002507 if (!mem_read[i] || !mem_write[i])
2508 subwidth = IO_MEM_SUBWIDTH;
bellard33417e72003-08-10 21:47:01 +00002509 io_mem_read[io_index][i] = mem_read[i];
2510 io_mem_write[io_index][i] = mem_write[i];
2511 }
bellarda4193c82004-06-03 14:01:43 +00002512 io_mem_opaque[io_index] = opaque;
blueswir14254fab2008-01-01 16:57:19 +00002513 return (io_index << IO_MEM_SHIFT) | subwidth;
bellard33417e72003-08-10 21:47:01 +00002514}
bellard61382a52003-10-27 21:22:23 +00002515
bellard8926b512004-10-10 15:14:20 +00002516CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2517{
2518 return io_mem_write[io_index >> IO_MEM_SHIFT];
2519}
2520
2521CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2522{
2523 return io_mem_read[io_index >> IO_MEM_SHIFT];
2524}
2525
bellard13eb76e2004-01-24 15:23:36 +00002526/* physical memory access (slow version, mainly for debug) */
2527#if defined(CONFIG_USER_ONLY)
ths5fafdf22007-09-16 21:08:06 +00002528void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002529 int len, int is_write)
2530{
2531 int l, flags;
2532 target_ulong page;
pbrook53a59602006-03-25 19:31:22 +00002533 void * p;
bellard13eb76e2004-01-24 15:23:36 +00002534
2535 while (len > 0) {
2536 page = addr & TARGET_PAGE_MASK;
2537 l = (page + TARGET_PAGE_SIZE) - addr;
2538 if (l > len)
2539 l = len;
2540 flags = page_get_flags(page);
2541 if (!(flags & PAGE_VALID))
2542 return;
2543 if (is_write) {
2544 if (!(flags & PAGE_WRITE))
2545 return;
bellard579a97f2007-11-11 14:26:47 +00002546 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002547 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
bellard579a97f2007-11-11 14:26:47 +00002548 /* FIXME - should this return an error rather than just fail? */
2549 return;
aurel3272fb7da2008-04-27 23:53:45 +00002550 memcpy(p, buf, l);
2551 unlock_user(p, addr, l);
bellard13eb76e2004-01-24 15:23:36 +00002552 } else {
2553 if (!(flags & PAGE_READ))
2554 return;
bellard579a97f2007-11-11 14:26:47 +00002555 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002556 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
bellard579a97f2007-11-11 14:26:47 +00002557 /* FIXME - should this return an error rather than just fail? */
2558 return;
aurel3272fb7da2008-04-27 23:53:45 +00002559 memcpy(buf, p, l);
aurel325b257572008-04-28 08:54:59 +00002560 unlock_user(p, addr, 0);
bellard13eb76e2004-01-24 15:23:36 +00002561 }
2562 len -= l;
2563 buf += l;
2564 addr += l;
2565 }
2566}
bellard8df1cd02005-01-28 22:37:22 +00002567
bellard13eb76e2004-01-24 15:23:36 +00002568#else
ths5fafdf22007-09-16 21:08:06 +00002569void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002570 int len, int is_write)
2571{
2572 int l, io_index;
2573 uint8_t *ptr;
2574 uint32_t val;
bellard2e126692004-04-25 21:28:44 +00002575 target_phys_addr_t page;
2576 unsigned long pd;
bellard92e873b2004-05-21 14:52:29 +00002577 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002578
bellard13eb76e2004-01-24 15:23:36 +00002579 while (len > 0) {
2580 page = addr & TARGET_PAGE_MASK;
2581 l = (page + TARGET_PAGE_SIZE) - addr;
2582 if (l > len)
2583 l = len;
bellard92e873b2004-05-21 14:52:29 +00002584 p = phys_page_find(page >> TARGET_PAGE_BITS);
bellard13eb76e2004-01-24 15:23:36 +00002585 if (!p) {
2586 pd = IO_MEM_UNASSIGNED;
2587 } else {
2588 pd = p->phys_offset;
2589 }
ths3b46e622007-09-17 08:09:54 +00002590
bellard13eb76e2004-01-24 15:23:36 +00002591 if (is_write) {
bellard3a7d9292005-08-21 09:26:42 +00002592 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard13eb76e2004-01-24 15:23:36 +00002593 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
bellard6a00d602005-11-21 23:25:50 +00002594 /* XXX: could force cpu_single_env to NULL to avoid
2595 potential bugs */
bellard13eb76e2004-01-24 15:23:36 +00002596 if (l >= 4 && ((addr & 3) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002597 /* 32 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002598 val = ldl_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002599 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002600 l = 4;
2601 } else if (l >= 2 && ((addr & 1) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002602 /* 16 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002603 val = lduw_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002604 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002605 l = 2;
2606 } else {
bellard1c213d12005-09-03 10:49:04 +00002607 /* 8 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002608 val = ldub_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002609 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002610 l = 1;
2611 }
2612 } else {
bellardb448f2f2004-02-25 23:24:04 +00002613 unsigned long addr1;
2614 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
bellard13eb76e2004-01-24 15:23:36 +00002615 /* RAM case */
bellardb448f2f2004-02-25 23:24:04 +00002616 ptr = phys_ram_base + addr1;
bellard13eb76e2004-01-24 15:23:36 +00002617 memcpy(ptr, buf, l);
bellard3a7d9292005-08-21 09:26:42 +00002618 if (!cpu_physical_memory_is_dirty(addr1)) {
2619 /* invalidate code */
2620 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
2621 /* set dirty bit */
ths5fafdf22007-09-16 21:08:06 +00002622 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
bellardf23db162005-08-21 19:12:28 +00002623 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00002624 }
bellard13eb76e2004-01-24 15:23:36 +00002625 }
2626 } else {
ths5fafdf22007-09-16 21:08:06 +00002627 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00002628 !(pd & IO_MEM_ROMD)) {
bellard13eb76e2004-01-24 15:23:36 +00002629 /* I/O case */
2630 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2631 if (l >= 4 && ((addr & 3) == 0)) {
2632 /* 32 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002633 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002634 stl_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002635 l = 4;
2636 } else if (l >= 2 && ((addr & 1) == 0)) {
2637 /* 16 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002638 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002639 stw_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002640 l = 2;
2641 } else {
bellard1c213d12005-09-03 10:49:04 +00002642 /* 8 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002643 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002644 stb_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002645 l = 1;
2646 }
2647 } else {
2648 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00002649 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard13eb76e2004-01-24 15:23:36 +00002650 (addr & ~TARGET_PAGE_MASK);
2651 memcpy(buf, ptr, l);
2652 }
2653 }
2654 len -= l;
2655 buf += l;
2656 addr += l;
2657 }
2658}
bellard8df1cd02005-01-28 22:37:22 +00002659
bellardd0ecd2a2006-04-23 17:14:48 +00002660/* used for ROM loading : can write in RAM and ROM */
ths5fafdf22007-09-16 21:08:06 +00002661void cpu_physical_memory_write_rom(target_phys_addr_t addr,
bellardd0ecd2a2006-04-23 17:14:48 +00002662 const uint8_t *buf, int len)
2663{
2664 int l;
2665 uint8_t *ptr;
2666 target_phys_addr_t page;
2667 unsigned long pd;
2668 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002669
bellardd0ecd2a2006-04-23 17:14:48 +00002670 while (len > 0) {
2671 page = addr & TARGET_PAGE_MASK;
2672 l = (page + TARGET_PAGE_SIZE) - addr;
2673 if (l > len)
2674 l = len;
2675 p = phys_page_find(page >> TARGET_PAGE_BITS);
2676 if (!p) {
2677 pd = IO_MEM_UNASSIGNED;
2678 } else {
2679 pd = p->phys_offset;
2680 }
ths3b46e622007-09-17 08:09:54 +00002681
bellardd0ecd2a2006-04-23 17:14:48 +00002682 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
bellard2a4188a2006-06-25 21:54:59 +00002683 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
2684 !(pd & IO_MEM_ROMD)) {
bellardd0ecd2a2006-04-23 17:14:48 +00002685 /* do nothing */
2686 } else {
2687 unsigned long addr1;
2688 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
2689 /* ROM/RAM case */
2690 ptr = phys_ram_base + addr1;
2691 memcpy(ptr, buf, l);
2692 }
2693 len -= l;
2694 buf += l;
2695 addr += l;
2696 }
2697}
2698
2699
bellard8df1cd02005-01-28 22:37:22 +00002700/* warning: addr must be aligned */
2701uint32_t ldl_phys(target_phys_addr_t addr)
2702{
2703 int io_index;
2704 uint8_t *ptr;
2705 uint32_t val;
2706 unsigned long pd;
2707 PhysPageDesc *p;
2708
2709 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2710 if (!p) {
2711 pd = IO_MEM_UNASSIGNED;
2712 } else {
2713 pd = p->phys_offset;
2714 }
ths3b46e622007-09-17 08:09:54 +00002715
ths5fafdf22007-09-16 21:08:06 +00002716 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00002717 !(pd & IO_MEM_ROMD)) {
bellard8df1cd02005-01-28 22:37:22 +00002718 /* I/O case */
2719 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2720 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
2721 } else {
2722 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00002723 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00002724 (addr & ~TARGET_PAGE_MASK);
2725 val = ldl_p(ptr);
2726 }
2727 return val;
2728}
2729
bellard84b7b8e2005-11-28 21:19:04 +00002730/* warning: addr must be aligned */
2731uint64_t ldq_phys(target_phys_addr_t addr)
2732{
2733 int io_index;
2734 uint8_t *ptr;
2735 uint64_t val;
2736 unsigned long pd;
2737 PhysPageDesc *p;
2738
2739 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2740 if (!p) {
2741 pd = IO_MEM_UNASSIGNED;
2742 } else {
2743 pd = p->phys_offset;
2744 }
ths3b46e622007-09-17 08:09:54 +00002745
bellard2a4188a2006-06-25 21:54:59 +00002746 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
2747 !(pd & IO_MEM_ROMD)) {
bellard84b7b8e2005-11-28 21:19:04 +00002748 /* I/O case */
2749 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2750#ifdef TARGET_WORDS_BIGENDIAN
2751 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
2752 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
2753#else
2754 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
2755 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
2756#endif
2757 } else {
2758 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00002759 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard84b7b8e2005-11-28 21:19:04 +00002760 (addr & ~TARGET_PAGE_MASK);
2761 val = ldq_p(ptr);
2762 }
2763 return val;
2764}
2765
bellardaab33092005-10-30 20:48:42 +00002766/* XXX: optimize */
2767uint32_t ldub_phys(target_phys_addr_t addr)
2768{
2769 uint8_t val;
2770 cpu_physical_memory_read(addr, &val, 1);
2771 return val;
2772}
2773
2774/* XXX: optimize */
2775uint32_t lduw_phys(target_phys_addr_t addr)
2776{
2777 uint16_t val;
2778 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
2779 return tswap16(val);
2780}
2781
bellard8df1cd02005-01-28 22:37:22 +00002782/* warning: addr must be aligned. The ram page is not masked as dirty
2783 and the code inside is not invalidated. It is useful if the dirty
2784 bits are used to track modified PTEs */
2785void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
2786{
2787 int io_index;
2788 uint8_t *ptr;
2789 unsigned long pd;
2790 PhysPageDesc *p;
2791
2792 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2793 if (!p) {
2794 pd = IO_MEM_UNASSIGNED;
2795 } else {
2796 pd = p->phys_offset;
2797 }
ths3b46e622007-09-17 08:09:54 +00002798
bellard3a7d9292005-08-21 09:26:42 +00002799 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00002800 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2801 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
2802 } else {
ths5fafdf22007-09-16 21:08:06 +00002803 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00002804 (addr & ~TARGET_PAGE_MASK);
2805 stl_p(ptr, val);
2806 }
2807}
2808
j_mayerbc98a7e2007-04-04 07:55:12 +00002809void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
2810{
2811 int io_index;
2812 uint8_t *ptr;
2813 unsigned long pd;
2814 PhysPageDesc *p;
2815
2816 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2817 if (!p) {
2818 pd = IO_MEM_UNASSIGNED;
2819 } else {
2820 pd = p->phys_offset;
2821 }
ths3b46e622007-09-17 08:09:54 +00002822
j_mayerbc98a7e2007-04-04 07:55:12 +00002823 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
2824 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2825#ifdef TARGET_WORDS_BIGENDIAN
2826 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
2827 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
2828#else
2829 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
2830 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
2831#endif
2832 } else {
ths5fafdf22007-09-16 21:08:06 +00002833 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
j_mayerbc98a7e2007-04-04 07:55:12 +00002834 (addr & ~TARGET_PAGE_MASK);
2835 stq_p(ptr, val);
2836 }
2837}
2838
bellard8df1cd02005-01-28 22:37:22 +00002839/* warning: addr must be aligned */
bellard8df1cd02005-01-28 22:37:22 +00002840void stl_phys(target_phys_addr_t addr, uint32_t val)
2841{
2842 int io_index;
2843 uint8_t *ptr;
2844 unsigned long pd;
2845 PhysPageDesc *p;
2846
2847 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2848 if (!p) {
2849 pd = IO_MEM_UNASSIGNED;
2850 } else {
2851 pd = p->phys_offset;
2852 }
ths3b46e622007-09-17 08:09:54 +00002853
bellard3a7d9292005-08-21 09:26:42 +00002854 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00002855 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2856 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
2857 } else {
2858 unsigned long addr1;
2859 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
2860 /* RAM case */
2861 ptr = phys_ram_base + addr1;
2862 stl_p(ptr, val);
bellard3a7d9292005-08-21 09:26:42 +00002863 if (!cpu_physical_memory_is_dirty(addr1)) {
2864 /* invalidate code */
2865 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
2866 /* set dirty bit */
bellardf23db162005-08-21 19:12:28 +00002867 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
2868 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00002869 }
bellard8df1cd02005-01-28 22:37:22 +00002870 }
2871}
2872
bellardaab33092005-10-30 20:48:42 +00002873/* XXX: optimize */
2874void stb_phys(target_phys_addr_t addr, uint32_t val)
2875{
2876 uint8_t v = val;
2877 cpu_physical_memory_write(addr, &v, 1);
2878}
2879
2880/* XXX: optimize */
2881void stw_phys(target_phys_addr_t addr, uint32_t val)
2882{
2883 uint16_t v = tswap16(val);
2884 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
2885}
2886
2887/* XXX: optimize */
2888void stq_phys(target_phys_addr_t addr, uint64_t val)
2889{
2890 val = tswap64(val);
2891 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
2892}
2893
bellard13eb76e2004-01-24 15:23:36 +00002894#endif
2895
2896/* virtual memory access for debug */
ths5fafdf22007-09-16 21:08:06 +00002897int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
bellardb448f2f2004-02-25 23:24:04 +00002898 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00002899{
2900 int l;
j_mayer9b3c35e2007-04-07 11:21:28 +00002901 target_phys_addr_t phys_addr;
2902 target_ulong page;
bellard13eb76e2004-01-24 15:23:36 +00002903
2904 while (len > 0) {
2905 page = addr & TARGET_PAGE_MASK;
2906 phys_addr = cpu_get_phys_page_debug(env, page);
2907 /* if no physical page mapped, return an error */
2908 if (phys_addr == -1)
2909 return -1;
2910 l = (page + TARGET_PAGE_SIZE) - addr;
2911 if (l > len)
2912 l = len;
ths5fafdf22007-09-16 21:08:06 +00002913 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
bellardb448f2f2004-02-25 23:24:04 +00002914 buf, l, is_write);
bellard13eb76e2004-01-24 15:23:36 +00002915 len -= l;
2916 buf += l;
2917 addr += l;
2918 }
2919 return 0;
2920}
2921
bellarde3db7222005-01-26 22:00:47 +00002922void dump_exec_info(FILE *f,
2923 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
2924{
2925 int i, target_code_size, max_target_code_size;
2926 int direct_jmp_count, direct_jmp2_count, cross_page;
2927 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +00002928
bellarde3db7222005-01-26 22:00:47 +00002929 target_code_size = 0;
2930 max_target_code_size = 0;
2931 cross_page = 0;
2932 direct_jmp_count = 0;
2933 direct_jmp2_count = 0;
2934 for(i = 0; i < nb_tbs; i++) {
2935 tb = &tbs[i];
2936 target_code_size += tb->size;
2937 if (tb->size > max_target_code_size)
2938 max_target_code_size = tb->size;
2939 if (tb->page_addr[1] != -1)
2940 cross_page++;
2941 if (tb->tb_next_offset[0] != 0xffff) {
2942 direct_jmp_count++;
2943 if (tb->tb_next_offset[1] != 0xffff) {
2944 direct_jmp2_count++;
2945 }
2946 }
2947 }
2948 /* XXX: avoid using doubles ? */
bellard57fec1f2008-02-01 10:50:11 +00002949 cpu_fprintf(f, "Translation buffer state:\n");
bellarde3db7222005-01-26 22:00:47 +00002950 cpu_fprintf(f, "TB count %d\n", nb_tbs);
ths5fafdf22007-09-16 21:08:06 +00002951 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
bellarde3db7222005-01-26 22:00:47 +00002952 nb_tbs ? target_code_size / nb_tbs : 0,
2953 max_target_code_size);
ths5fafdf22007-09-16 21:08:06 +00002954 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
bellarde3db7222005-01-26 22:00:47 +00002955 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
2956 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
ths5fafdf22007-09-16 21:08:06 +00002957 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
2958 cross_page,
bellarde3db7222005-01-26 22:00:47 +00002959 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
2960 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
ths5fafdf22007-09-16 21:08:06 +00002961 direct_jmp_count,
bellarde3db7222005-01-26 22:00:47 +00002962 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
2963 direct_jmp2_count,
2964 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
bellard57fec1f2008-02-01 10:50:11 +00002965 cpu_fprintf(f, "\nStatistics:\n");
bellarde3db7222005-01-26 22:00:47 +00002966 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
2967 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
2968 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
bellard57fec1f2008-02-01 10:50:11 +00002969#ifdef CONFIG_PROFILER
2970 {
2971 int64_t tot;
2972 tot = dyngen_interm_time + dyngen_code_time;
2973 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2974 tot, tot / 2.4e9);
2975 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2976 dyngen_tb_count,
2977 dyngen_tb_count1 - dyngen_tb_count,
2978 dyngen_tb_count1 ? (double)(dyngen_tb_count1 - dyngen_tb_count) / dyngen_tb_count1 * 100.0 : 0);
2979 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2980 dyngen_tb_count ? (double)dyngen_op_count / dyngen_tb_count : 0, dyngen_op_count_max);
2981 cpu_fprintf(f, "old ops/total ops %0.1f%%\n",
2982 dyngen_op_count ? (double)dyngen_old_op_count / dyngen_op_count * 100.0 : 0);
2983 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2984 dyngen_tb_count ?
2985 (double)dyngen_tcg_del_op_count / dyngen_tb_count : 0);
2986 cpu_fprintf(f, "cycles/op %0.1f\n",
2987 dyngen_op_count ? (double)tot / dyngen_op_count : 0);
2988 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2989 dyngen_code_in_len ? (double)tot / dyngen_code_in_len : 0);
2990 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2991 dyngen_code_out_len ? (double)tot / dyngen_code_out_len : 0);
2992 if (tot == 0)
2993 tot = 1;
2994 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2995 (double)dyngen_interm_time / tot * 100.0);
2996 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2997 (double)dyngen_code_time / tot * 100.0);
2998 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2999 dyngen_restore_count);
3000 cpu_fprintf(f, " avg cycles %0.1f\n",
3001 dyngen_restore_count ? (double)dyngen_restore_time / dyngen_restore_count : 0);
3002 {
3003 extern void dump_op_count(void);
3004 dump_op_count();
3005 }
3006 }
3007#endif
bellarde3db7222005-01-26 22:00:47 +00003008}
3009
ths5fafdf22007-09-16 21:08:06 +00003010#if !defined(CONFIG_USER_ONLY)
bellard61382a52003-10-27 21:22:23 +00003011
3012#define MMUSUFFIX _cmmu
3013#define GETPC() NULL
3014#define env cpu_single_env
bellardb769d8f2004-10-03 15:07:13 +00003015#define SOFTMMU_CODE_ACCESS
bellard61382a52003-10-27 21:22:23 +00003016
3017#define SHIFT 0
3018#include "softmmu_template.h"
3019
3020#define SHIFT 1
3021#include "softmmu_template.h"
3022
3023#define SHIFT 2
3024#include "softmmu_template.h"
3025
3026#define SHIFT 3
3027#include "softmmu_template.h"
3028
3029#undef env
3030
3031#endif