ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 1 | Unsolved issues/bugs in the mips/mipsel backend |
| 2 | ----------------------------------------------- |
| 3 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 4 | General |
| 5 | ------- |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 6 | - Unimplemented ASEs: |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 7 | - MDMX |
| 8 | - SmartMIPS |
Jia Liu | b30706d | 2012-10-24 22:17:14 +0800 | [diff] [blame] | 9 | - microMIPS DSP r1 & r2 encodings |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 10 | - MT ASE only partially implemented and not functional |
| 11 | - Shadow register support only partially implemented, |
| 12 | lacks set switching on interrupt/exception. |
| 13 | - 34K ITC not implemented. |
| 14 | - A general lack of documentation, especially for technical internals. |
| 15 | Existing documentation is x86-centric. |
| 16 | - Reverse endianness bit not implemented |
| 17 | - The TLB emulation is very inefficient: |
Stefan Weil | 6576b74 | 2012-04-07 09:23:37 +0200 | [diff] [blame] | 18 | QEMU's softmmu implements a x86-style MMU, with separate entries |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 19 | for read/write/execute, a TLB index which is just a modulo of the |
| 20 | virtual address, and a set of TLBs for each user/kernel/supervisor |
| 21 | MMU mode. |
| 22 | MIPS has a single entry for read/write/execute and only one MMU mode. |
| 23 | But it is fully associative with randomized entry indices, and uses |
| 24 | up to 256 ASID tags as additional matching criterion (which roughly |
| 25 | equates to 256 MMU modes). It also has a global flag which causes |
| 26 | entries to match regardless of ASID. |
Stefan Weil | 6576b74 | 2012-04-07 09:23:37 +0200 | [diff] [blame] | 27 | To cope with these differences, QEMU currently flushes the TLB at |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 28 | each ASID change. Using the MMU modes to implement ASIDs hinges on |
| 29 | implementing the global bit efficiently. |
ths | bec19c0 | 2008-05-07 15:39:12 +0000 | [diff] [blame] | 30 | - save/restore of the CPU state is not implemented (see machine.c). |
ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 31 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 32 | MIPS64 |
| 33 | ------ |
ths | 540635b | 2007-09-30 01:58:33 +0000 | [diff] [blame] | 34 | - Userland emulation (both n32 and n64) not functional. |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 35 | |
| 36 | "Generic" 4Kc system emulation |
| 37 | ------------------------------ |
ths | ebbd0ff | 2008-06-24 22:04:41 +0000 | [diff] [blame] | 38 | - Doesn't correspond to any real hardware. Should be removed some day, |
| 39 | U-Boot is the last remaining user. |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 40 | |
ths | 509b8ab | 2007-04-28 21:44:04 +0000 | [diff] [blame] | 41 | PICA 61 system emulation |
| 42 | ------------------------ |
| 43 | - No framebuffer support yet. |
| 44 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 45 | MALTA system emulation |
| 46 | ---------------------- |
ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 47 | - We fake firmware support instead of doing the real thing |
ths | ebbd0ff | 2008-06-24 22:04:41 +0000 | [diff] [blame] | 48 | - Real firmware (YAMON) falls over when trying to init RAM, presumably |
| 49 | due to lacking system controller emulation. |
ths | 0300e3f | 2007-12-17 03:53:42 +0000 | [diff] [blame] | 50 | - Bonito system controller not implemented |
| 51 | - MSC1 system controller not implemented |