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ths2c52c812007-01-17 20:03:15 +00001Unsolved issues/bugs in the mips/mipsel backend
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ths15dcf5a2007-01-19 17:56:23 +00004General
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thsd0f48072007-10-13 19:00:52 +00006- Unimplemented ASEs:
thsd0f48072007-10-13 19:00:52 +00007 - MDMX
8 - SmartMIPS
Jia Liub30706d2012-10-24 22:17:14 +08009 - microMIPS DSP r1 & r2 encodings
thsd0f48072007-10-13 19:00:52 +000010- MT ASE only partially implemented and not functional
11- Shadow register support only partially implemented,
12 lacks set switching on interrupt/exception.
13- 34K ITC not implemented.
14- A general lack of documentation, especially for technical internals.
15 Existing documentation is x86-centric.
16- Reverse endianness bit not implemented
17- The TLB emulation is very inefficient:
Stefan Weil6576b742012-04-07 09:23:37 +020018 QEMU's softmmu implements a x86-style MMU, with separate entries
thsd0f48072007-10-13 19:00:52 +000019 for read/write/execute, a TLB index which is just a modulo of the
20 virtual address, and a set of TLBs for each user/kernel/supervisor
21 MMU mode.
22 MIPS has a single entry for read/write/execute and only one MMU mode.
23 But it is fully associative with randomized entry indices, and uses
24 up to 256 ASID tags as additional matching criterion (which roughly
25 equates to 256 MMU modes). It also has a global flag which causes
26 entries to match regardless of ASID.
Stefan Weil6576b742012-04-07 09:23:37 +020027 To cope with these differences, QEMU currently flushes the TLB at
thsd0f48072007-10-13 19:00:52 +000028 each ASID change. Using the MMU modes to implement ASIDs hinges on
29 implementing the global bit efficiently.
thsbec19c02008-05-07 15:39:12 +000030- save/restore of the CPU state is not implemented (see machine.c).
ths2c52c812007-01-17 20:03:15 +000031
ths15dcf5a2007-01-19 17:56:23 +000032MIPS64
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ths540635b2007-09-30 01:58:33 +000034- Userland emulation (both n32 and n64) not functional.
ths15dcf5a2007-01-19 17:56:23 +000035
36"Generic" 4Kc system emulation
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thsebbd0ff2008-06-24 22:04:41 +000038- Doesn't correspond to any real hardware. Should be removed some day,
39 U-Boot is the last remaining user.
ths15dcf5a2007-01-19 17:56:23 +000040
ths509b8ab2007-04-28 21:44:04 +000041PICA 61 system emulation
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43- No framebuffer support yet.
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ths15dcf5a2007-01-19 17:56:23 +000045MALTA system emulation
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ths2c52c812007-01-17 20:03:15 +000047- We fake firmware support instead of doing the real thing
thsebbd0ff2008-06-24 22:04:41 +000048- Real firmware (YAMON) falls over when trying to init RAM, presumably
49 due to lacking system controller emulation.
ths0300e3f2007-12-17 03:53:42 +000050- Bonito system controller not implemented
51- MSC1 system controller not implemented