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balrogadb86c32007-05-23 22:04:23 +00001/*
2 * WM8750 audio CODEC.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This file is licensed under GNU GPL.
8 */
9
pbrook87ecb682007-11-17 17:14:51 +000010#include "hw.h"
11#include "i2c.h"
12#include "audio/audio.h"
balrogadb86c32007-05-23 22:04:23 +000013
14#define IN_PORT_N 3
15#define OUT_PORT_N 3
16
17#define CODEC "wm8750"
18
Paul Brookbc24a222009-05-10 01:44:56 +010019typedef struct {
20 int adc;
21 int adc_hz;
22 int dac;
23 int dac_hz;
24} WMRate;
25
26typedef struct {
Anthony Liguori9e07bdf2011-12-04 20:28:27 -060027 I2CSlave i2c;
balrogadb86c32007-05-23 22:04:23 +000028 uint8_t i2c_data[2];
29 int i2c_len;
30 QEMUSoundCard card;
31 SWVoiceIn *adc_voice[IN_PORT_N];
32 SWVoiceOut *dac_voice[OUT_PORT_N];
33 int enable;
34 void (*data_req)(void *, int, int);
35 void *opaque;
36 uint8_t data_in[4096];
37 uint8_t data_out[4096];
38 int idx_in, req_in;
39 int idx_out, req_out;
40
41 SWVoiceOut **out[2];
42 uint8_t outvol[7], outmute[2];
43 SWVoiceIn **in[2];
44 uint8_t invol[4], inmute[2];
45
46 uint8_t diff[2], pol, ds, monomix[2], alc, mute;
47 uint8_t path[4], mpath[2], power, format;
Paul Brookbc24a222009-05-10 01:44:56 +010048 const WMRate *rate;
Juan Quintelac1d803b2009-09-29 22:48:31 +020049 uint8_t rate_vmstate;
balrogaf83e092008-05-04 12:15:51 +000050 int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master;
Paul Brookbc24a222009-05-10 01:44:56 +010051} WM8750State;
balrogadb86c32007-05-23 22:04:23 +000052
balrogdb502b62008-05-04 10:55:25 +000053/* pow(10.0, -i / 20.0) * 255, i = 0..42 */
balrog683efdc2008-05-04 10:21:03 +000054static const uint8_t wm8750_vol_db_table[] = {
55 255, 227, 203, 181, 161, 143, 128, 114, 102, 90, 81, 72, 64, 57, 51, 45,
56 40, 36, 32, 29, 26, 23, 20, 18, 16, 14, 13, 11, 10, 9, 8, 7, 6, 6, 5, 5,
57 4, 4, 3, 3, 3, 2, 2
58};
59
balrogdb502b62008-05-04 10:55:25 +000060#define WM8750_OUTVOL_TRANSFORM(x) wm8750_vol_db_table[(0x7f - x) / 3]
61#define WM8750_INVOL_TRANSFORM(x) (x << 2)
balrog683efdc2008-05-04 10:21:03 +000062
Paul Brookbc24a222009-05-10 01:44:56 +010063static inline void wm8750_in_load(WM8750State *s)
balrogadb86c32007-05-23 22:04:23 +000064{
balrogadb86c32007-05-23 22:04:23 +000065 if (s->idx_in + s->req_in <= sizeof(s->data_in))
66 return;
67 s->idx_in = audio_MAX(0, (int) sizeof(s->data_in) - s->req_in);
Blue Swirl22ed1d32010-04-25 19:31:06 +000068 AUD_read(*s->in[0], s->data_in + s->idx_in,
69 sizeof(s->data_in) - s->idx_in);
balrogadb86c32007-05-23 22:04:23 +000070}
71
Paul Brookbc24a222009-05-10 01:44:56 +010072static inline void wm8750_out_flush(WM8750State *s)
balrogadb86c32007-05-23 22:04:23 +000073{
balrog523111e2008-04-24 21:01:40 +000074 int sent = 0;
75 while (sent < s->idx_out)
76 sent += AUD_write(*s->out[0], s->data_out + sent, s->idx_out - sent)
77 ?: s->idx_out;
balrogadb86c32007-05-23 22:04:23 +000078 s->idx_out = 0;
79}
80
81static void wm8750_audio_in_cb(void *opaque, int avail_b)
82{
Paul Brookbc24a222009-05-10 01:44:56 +010083 WM8750State *s = (WM8750State *) opaque;
balrogadb86c32007-05-23 22:04:23 +000084 s->req_in = avail_b;
85 s->data_req(s->opaque, s->req_out >> 2, avail_b >> 2);
balrogadb86c32007-05-23 22:04:23 +000086}
87
88static void wm8750_audio_out_cb(void *opaque, int free_b)
89{
Paul Brookbc24a222009-05-10 01:44:56 +010090 WM8750State *s = (WM8750State *) opaque;
balrogadb86c32007-05-23 22:04:23 +000091
balrog523111e2008-04-24 21:01:40 +000092 if (s->idx_out >= free_b) {
93 s->idx_out = free_b;
94 s->req_out = 0;
95 wm8750_out_flush(s);
96 } else
97 s->req_out = free_b - s->idx_out;
98
99 s->data_req(s->opaque, s->req_out >> 2, s->req_in >> 2);
balrogadb86c32007-05-23 22:04:23 +0000100}
101
Paul Brookbc24a222009-05-10 01:44:56 +0100102static const WMRate wm_rate_table[] = {
balrogadb86c32007-05-23 22:04:23 +0000103 { 256, 48000, 256, 48000 }, /* SR: 00000 */
104 { 384, 48000, 384, 48000 }, /* SR: 00001 */
105 { 256, 48000, 1536, 8000 }, /* SR: 00010 */
106 { 384, 48000, 2304, 8000 }, /* SR: 00011 */
107 { 1536, 8000, 256, 48000 }, /* SR: 00100 */
108 { 2304, 8000, 384, 48000 }, /* SR: 00101 */
109 { 1536, 8000, 1536, 8000 }, /* SR: 00110 */
110 { 2304, 8000, 2304, 8000 }, /* SR: 00111 */
111 { 1024, 12000, 1024, 12000 }, /* SR: 01000 */
112 { 1526, 12000, 1536, 12000 }, /* SR: 01001 */
113 { 768, 16000, 768, 16000 }, /* SR: 01010 */
114 { 1152, 16000, 1152, 16000 }, /* SR: 01011 */
115 { 384, 32000, 384, 32000 }, /* SR: 01100 */
116 { 576, 32000, 576, 32000 }, /* SR: 01101 */
117 { 128, 96000, 128, 96000 }, /* SR: 01110 */
118 { 192, 96000, 192, 96000 }, /* SR: 01111 */
119 { 256, 44100, 256, 44100 }, /* SR: 10000 */
120 { 384, 44100, 384, 44100 }, /* SR: 10001 */
121 { 256, 44100, 1408, 8018 }, /* SR: 10010 */
122 { 384, 44100, 2112, 8018 }, /* SR: 10011 */
123 { 1408, 8018, 256, 44100 }, /* SR: 10100 */
124 { 2112, 8018, 384, 44100 }, /* SR: 10101 */
125 { 1408, 8018, 1408, 8018 }, /* SR: 10110 */
126 { 2112, 8018, 2112, 8018 }, /* SR: 10111 */
127 { 1024, 11025, 1024, 11025 }, /* SR: 11000 */
128 { 1536, 11025, 1536, 11025 }, /* SR: 11001 */
129 { 512, 22050, 512, 22050 }, /* SR: 11010 */
130 { 768, 22050, 768, 22050 }, /* SR: 11011 */
131 { 512, 24000, 512, 24000 }, /* SR: 11100 */
132 { 768, 24000, 768, 24000 }, /* SR: 11101 */
133 { 128, 88200, 128, 88200 }, /* SR: 11110 */
balrog523111e2008-04-24 21:01:40 +0000134 { 192, 88200, 192, 88200 }, /* SR: 11111 */
balrogadb86c32007-05-23 22:04:23 +0000135};
136
Paul Brookbc24a222009-05-10 01:44:56 +0100137static void wm8750_vol_update(WM8750State *s)
balrog683efdc2008-05-04 10:21:03 +0000138{
139 /* FIXME: multiply all volumes by s->invol[2], s->invol[3] */
140
balrogdb502b62008-05-04 10:55:25 +0000141 AUD_set_volume_in(s->adc_voice[0], s->mute,
142 s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]),
143 s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1]));
144 AUD_set_volume_in(s->adc_voice[1], s->mute,
145 s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]),
146 s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1]));
147 AUD_set_volume_in(s->adc_voice[2], s->mute,
148 s->inmute[0] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[0]),
149 s->inmute[1] ? 0 : WM8750_INVOL_TRANSFORM(s->invol[1]));
balrog683efdc2008-05-04 10:21:03 +0000150
151 /* FIXME: multiply all volumes by s->outvol[0], s->outvol[1] */
152
153 /* Speaker: LOUT2VOL ROUT2VOL */
154 AUD_set_volume_out(s->dac_voice[0], s->mute,
balrogdb502b62008-05-04 10:55:25 +0000155 s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[4]),
156 s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[5]));
balrog683efdc2008-05-04 10:21:03 +0000157
balrogdb502b62008-05-04 10:55:25 +0000158 /* Headphone: LOUT1VOL ROUT1VOL */
balrog683efdc2008-05-04 10:21:03 +0000159 AUD_set_volume_out(s->dac_voice[1], s->mute,
balrogdb502b62008-05-04 10:55:25 +0000160 s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[2]),
161 s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[3]));
balrog683efdc2008-05-04 10:21:03 +0000162
163 /* MONOOUT: MONOVOL MONOVOL */
164 AUD_set_volume_out(s->dac_voice[2], s->mute,
balrogdb502b62008-05-04 10:55:25 +0000165 s->outmute[0] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[6]),
166 s->outmute[1] ? 0 : WM8750_OUTVOL_TRANSFORM(s->outvol[6]));
balrog683efdc2008-05-04 10:21:03 +0000167}
168
Paul Brookbc24a222009-05-10 01:44:56 +0100169static void wm8750_set_format(WM8750State *s)
balrogadb86c32007-05-23 22:04:23 +0000170{
171 int i;
malc1ea879e2008-12-03 22:48:44 +0000172 struct audsettings in_fmt;
173 struct audsettings out_fmt;
balrogadb86c32007-05-23 22:04:23 +0000174
175 wm8750_out_flush(s);
176
177 if (s->in[0] && *s->in[0])
178 AUD_set_active_in(*s->in[0], 0);
179 if (s->out[0] && *s->out[0])
180 AUD_set_active_out(*s->out[0], 0);
181
182 for (i = 0; i < IN_PORT_N; i ++)
183 if (s->adc_voice[i]) {
184 AUD_close_in(&s->card, s->adc_voice[i]);
blueswir1511d2b12009-03-07 15:32:56 +0000185 s->adc_voice[i] = NULL;
balrogadb86c32007-05-23 22:04:23 +0000186 }
187 for (i = 0; i < OUT_PORT_N; i ++)
188 if (s->dac_voice[i]) {
189 AUD_close_out(&s->card, s->dac_voice[i]);
blueswir1511d2b12009-03-07 15:32:56 +0000190 s->dac_voice[i] = NULL;
balrogadb86c32007-05-23 22:04:23 +0000191 }
192
193 if (!s->enable)
194 return;
195
196 /* Setup input */
197 in_fmt.endianness = 0;
198 in_fmt.nchannels = 2;
balrogaf83e092008-05-04 12:15:51 +0000199 in_fmt.freq = s->adc_hz;
balrogadb86c32007-05-23 22:04:23 +0000200 in_fmt.fmt = AUD_FMT_S16;
201
202 s->adc_voice[0] = AUD_open_in(&s->card, s->adc_voice[0],
203 CODEC ".input1", s, wm8750_audio_in_cb, &in_fmt);
204 s->adc_voice[1] = AUD_open_in(&s->card, s->adc_voice[1],
205 CODEC ".input2", s, wm8750_audio_in_cb, &in_fmt);
206 s->adc_voice[2] = AUD_open_in(&s->card, s->adc_voice[2],
207 CODEC ".input3", s, wm8750_audio_in_cb, &in_fmt);
208
209 /* Setup output */
210 out_fmt.endianness = 0;
211 out_fmt.nchannels = 2;
balrogaf83e092008-05-04 12:15:51 +0000212 out_fmt.freq = s->dac_hz;
balrogadb86c32007-05-23 22:04:23 +0000213 out_fmt.fmt = AUD_FMT_S16;
balrogadb86c32007-05-23 22:04:23 +0000214
215 s->dac_voice[0] = AUD_open_out(&s->card, s->dac_voice[0],
216 CODEC ".speaker", s, wm8750_audio_out_cb, &out_fmt);
217 s->dac_voice[1] = AUD_open_out(&s->card, s->dac_voice[1],
218 CODEC ".headphone", s, wm8750_audio_out_cb, &out_fmt);
219 /* MONOMIX is also in stereo for simplicity */
220 s->dac_voice[2] = AUD_open_out(&s->card, s->dac_voice[2],
221 CODEC ".monomix", s, wm8750_audio_out_cb, &out_fmt);
222 /* no sense emulating OUT3 which is a mix of other outputs */
223
balrog683efdc2008-05-04 10:21:03 +0000224 wm8750_vol_update(s);
225
balrogadb86c32007-05-23 22:04:23 +0000226 /* We should connect the left and right channels to their
227 * respective inputs/outputs but we have completely no need
228 * for mixing or combining paths to different ports, so we
229 * connect both channels to where the left channel is routed. */
230 if (s->in[0] && *s->in[0])
231 AUD_set_active_in(*s->in[0], 1);
232 if (s->out[0] && *s->out[0])
233 AUD_set_active_out(*s->out[0], 1);
234}
235
Paul Brookbc24a222009-05-10 01:44:56 +0100236static void wm8750_clk_update(WM8750State *s, int ext)
balrogaf83e092008-05-04 12:15:51 +0000237{
238 if (s->master || !s->ext_dac_hz)
239 s->dac_hz = s->rate->dac_hz;
240 else
241 s->dac_hz = s->ext_dac_hz;
242
243 if (s->master || !s->ext_adc_hz)
244 s->adc_hz = s->rate->adc_hz;
245 else
246 s->adc_hz = s->ext_adc_hz;
247
248 if (s->master || (!s->ext_dac_hz && !s->ext_adc_hz)) {
249 if (!ext)
250 wm8750_set_format(s);
251 } else {
252 if (ext)
253 wm8750_set_format(s);
254 }
255}
256
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600257static void wm8750_reset(I2CSlave *i2c)
balrogadb86c32007-05-23 22:04:23 +0000258{
Paul Brookbc24a222009-05-10 01:44:56 +0100259 WM8750State *s = (WM8750State *) i2c;
balrogeb69b502008-04-20 03:40:20 +0000260 s->rate = &wm_rate_table[0];
balrogadb86c32007-05-23 22:04:23 +0000261 s->enable = 0;
balrogaf83e092008-05-04 12:15:51 +0000262 wm8750_clk_update(s, 1);
balrogadb86c32007-05-23 22:04:23 +0000263 s->diff[0] = 0;
264 s->diff[1] = 0;
265 s->ds = 0;
266 s->alc = 0;
267 s->in[0] = &s->adc_voice[0];
268 s->invol[0] = 0x17;
269 s->invol[1] = 0x17;
270 s->invol[2] = 0xc3;
271 s->invol[3] = 0xc3;
272 s->out[0] = &s->dac_voice[0];
273 s->outvol[0] = 0xff;
274 s->outvol[1] = 0xff;
275 s->outvol[2] = 0x79;
276 s->outvol[3] = 0x79;
277 s->outvol[4] = 0x79;
278 s->outvol[5] = 0x79;
balrogdb502b62008-05-04 10:55:25 +0000279 s->outvol[6] = 0x79;
balrogadb86c32007-05-23 22:04:23 +0000280 s->inmute[0] = 0;
281 s->inmute[1] = 0;
282 s->outmute[0] = 0;
283 s->outmute[1] = 0;
284 s->mute = 1;
285 s->path[0] = 0;
286 s->path[1] = 0;
287 s->path[2] = 0;
288 s->path[3] = 0;
289 s->mpath[0] = 0;
290 s->mpath[1] = 0;
291 s->format = 0x0a;
292 s->idx_in = sizeof(s->data_in);
293 s->req_in = 0;
294 s->idx_out = 0;
295 s->req_out = 0;
balrog683efdc2008-05-04 10:21:03 +0000296 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000297 s->i2c_len = 0;
298}
299
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600300static void wm8750_event(I2CSlave *i2c, enum i2c_event event)
balrogadb86c32007-05-23 22:04:23 +0000301{
Paul Brookbc24a222009-05-10 01:44:56 +0100302 WM8750State *s = (WM8750State *) i2c;
balrogadb86c32007-05-23 22:04:23 +0000303
304 switch (event) {
305 case I2C_START_SEND:
306 s->i2c_len = 0;
307 break;
308 case I2C_FINISH:
309#ifdef VERBOSE
310 if (s->i2c_len < 2)
311 printf("%s: message too short (%i bytes)\n",
312 __FUNCTION__, s->i2c_len);
313#endif
314 break;
315 default:
316 break;
317 }
318}
319
320#define WM8750_LINVOL 0x00
321#define WM8750_RINVOL 0x01
322#define WM8750_LOUT1V 0x02
323#define WM8750_ROUT1V 0x03
324#define WM8750_ADCDAC 0x05
325#define WM8750_IFACE 0x07
326#define WM8750_SRATE 0x08
327#define WM8750_LDAC 0x0a
328#define WM8750_RDAC 0x0b
329#define WM8750_BASS 0x0c
330#define WM8750_TREBLE 0x0d
331#define WM8750_RESET 0x0f
332#define WM8750_3D 0x10
333#define WM8750_ALC1 0x11
334#define WM8750_ALC2 0x12
335#define WM8750_ALC3 0x13
336#define WM8750_NGATE 0x14
337#define WM8750_LADC 0x15
338#define WM8750_RADC 0x16
339#define WM8750_ADCTL1 0x17
340#define WM8750_ADCTL2 0x18
341#define WM8750_PWR1 0x19
342#define WM8750_PWR2 0x1a
343#define WM8750_ADCTL3 0x1b
344#define WM8750_ADCIN 0x1f
345#define WM8750_LADCIN 0x20
346#define WM8750_RADCIN 0x21
347#define WM8750_LOUTM1 0x22
348#define WM8750_LOUTM2 0x23
349#define WM8750_ROUTM1 0x24
350#define WM8750_ROUTM2 0x25
351#define WM8750_MOUTM1 0x26
352#define WM8750_MOUTM2 0x27
353#define WM8750_LOUT2V 0x28
354#define WM8750_ROUT2V 0x29
355#define WM8750_MOUTV 0x2a
356
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600357static int wm8750_tx(I2CSlave *i2c, uint8_t data)
balrogadb86c32007-05-23 22:04:23 +0000358{
Paul Brookbc24a222009-05-10 01:44:56 +0100359 WM8750State *s = (WM8750State *) i2c;
balrogadb86c32007-05-23 22:04:23 +0000360 uint8_t cmd;
361 uint16_t value;
362
363 if (s->i2c_len >= 2) {
balrogadb86c32007-05-23 22:04:23 +0000364#ifdef VERBOSE
Stefan Weil149eeb52012-09-03 22:56:00 +0200365 printf("%s: long message (%i bytes)\n", __func__, s->i2c_len);
balrogadb86c32007-05-23 22:04:23 +0000366#endif
Stefan Weil149eeb52012-09-03 22:56:00 +0200367 return 1;
balrogadb86c32007-05-23 22:04:23 +0000368 }
369 s->i2c_data[s->i2c_len ++] = data;
370 if (s->i2c_len != 2)
371 return 0;
372
373 cmd = s->i2c_data[0] >> 1;
374 value = ((s->i2c_data[0] << 8) | s->i2c_data[1]) & 0x1ff;
375
376 switch (cmd) {
377 case WM8750_LADCIN: /* ADC Signal Path Control (Left) */
378 s->diff[0] = (((value >> 6) & 3) == 3); /* LINSEL */
379 if (s->diff[0])
380 s->in[0] = &s->adc_voice[0 + s->ds * 1];
381 else
382 s->in[0] = &s->adc_voice[((value >> 6) & 3) * 1 + 0];
383 break;
384
385 case WM8750_RADCIN: /* ADC Signal Path Control (Right) */
386 s->diff[1] = (((value >> 6) & 3) == 3); /* RINSEL */
387 if (s->diff[1])
388 s->in[1] = &s->adc_voice[0 + s->ds * 1];
389 else
390 s->in[1] = &s->adc_voice[((value >> 6) & 3) * 1 + 0];
391 break;
392
393 case WM8750_ADCIN: /* ADC Input Mode */
394 s->ds = (value >> 8) & 1; /* DS */
395 if (s->diff[0])
396 s->in[0] = &s->adc_voice[0 + s->ds * 1];
397 if (s->diff[1])
398 s->in[1] = &s->adc_voice[0 + s->ds * 1];
399 s->monomix[0] = (value >> 6) & 3; /* MONOMIX */
400 break;
401
402 case WM8750_ADCTL1: /* Additional Control (1) */
403 s->monomix[1] = (value >> 1) & 1; /* DMONOMIX */
404 break;
405
406 case WM8750_PWR1: /* Power Management (1) */
407 s->enable = ((value >> 6) & 7) == 3; /* VMIDSEL, VREF */
408 wm8750_set_format(s);
409 break;
410
411 case WM8750_LINVOL: /* Left Channel PGA */
412 s->invol[0] = value & 0x3f; /* LINVOL */
413 s->inmute[0] = (value >> 7) & 1; /* LINMUTE */
balrog683efdc2008-05-04 10:21:03 +0000414 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000415 break;
416
417 case WM8750_RINVOL: /* Right Channel PGA */
418 s->invol[1] = value & 0x3f; /* RINVOL */
419 s->inmute[1] = (value >> 7) & 1; /* RINMUTE */
balrog683efdc2008-05-04 10:21:03 +0000420 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000421 break;
422
423 case WM8750_ADCDAC: /* ADC and DAC Control */
424 s->pol = (value >> 5) & 3; /* ADCPOL */
425 s->mute = (value >> 3) & 1; /* DACMU */
balrog683efdc2008-05-04 10:21:03 +0000426 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000427 break;
428
429 case WM8750_ADCTL3: /* Additional Control (3) */
430 break;
431
432 case WM8750_LADC: /* Left ADC Digital Volume */
433 s->invol[2] = value & 0xff; /* LADCVOL */
balrogdb502b62008-05-04 10:55:25 +0000434 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000435 break;
436
437 case WM8750_RADC: /* Right ADC Digital Volume */
438 s->invol[3] = value & 0xff; /* RADCVOL */
balrogdb502b62008-05-04 10:55:25 +0000439 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000440 break;
441
442 case WM8750_ALC1: /* ALC Control (1) */
443 s->alc = (value >> 7) & 3; /* ALCSEL */
444 break;
445
446 case WM8750_NGATE: /* Noise Gate Control */
447 case WM8750_3D: /* 3D enhance */
448 break;
449
450 case WM8750_LDAC: /* Left Channel Digital Volume */
451 s->outvol[0] = value & 0xff; /* LDACVOL */
balrogdb502b62008-05-04 10:55:25 +0000452 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000453 break;
454
455 case WM8750_RDAC: /* Right Channel Digital Volume */
456 s->outvol[1] = value & 0xff; /* RDACVOL */
balrogdb502b62008-05-04 10:55:25 +0000457 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000458 break;
459
460 case WM8750_BASS: /* Bass Control */
461 break;
462
463 case WM8750_LOUTM1: /* Left Mixer Control (1) */
464 s->path[0] = (value >> 8) & 1; /* LD2LO */
balrogdb502b62008-05-04 10:55:25 +0000465 /* TODO: mute/unmute respective paths */
466 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000467 break;
468
469 case WM8750_LOUTM2: /* Left Mixer Control (2) */
470 s->path[1] = (value >> 8) & 1; /* RD2LO */
balrogdb502b62008-05-04 10:55:25 +0000471 /* TODO: mute/unmute respective paths */
472 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000473 break;
474
475 case WM8750_ROUTM1: /* Right Mixer Control (1) */
476 s->path[2] = (value >> 8) & 1; /* LD2RO */
balrogdb502b62008-05-04 10:55:25 +0000477 /* TODO: mute/unmute respective paths */
478 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000479 break;
480
481 case WM8750_ROUTM2: /* Right Mixer Control (2) */
482 s->path[3] = (value >> 8) & 1; /* RD2RO */
balrogdb502b62008-05-04 10:55:25 +0000483 /* TODO: mute/unmute respective paths */
484 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000485 break;
486
487 case WM8750_MOUTM1: /* Mono Mixer Control (1) */
488 s->mpath[0] = (value >> 8) & 1; /* LD2MO */
balrogdb502b62008-05-04 10:55:25 +0000489 /* TODO: mute/unmute respective paths */
490 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000491 break;
492
493 case WM8750_MOUTM2: /* Mono Mixer Control (2) */
494 s->mpath[1] = (value >> 8) & 1; /* RD2MO */
balrogdb502b62008-05-04 10:55:25 +0000495 /* TODO: mute/unmute respective paths */
496 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000497 break;
498
499 case WM8750_LOUT1V: /* LOUT1 Volume */
balrog683efdc2008-05-04 10:21:03 +0000500 s->outvol[2] = value & 0x7f; /* LOUT1VOL */
balrogdb502b62008-05-04 10:55:25 +0000501 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000502 break;
503
504 case WM8750_LOUT2V: /* LOUT2 Volume */
505 s->outvol[4] = value & 0x7f; /* LOUT2VOL */
balrog683efdc2008-05-04 10:21:03 +0000506 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000507 break;
508
509 case WM8750_ROUT1V: /* ROUT1 Volume */
balrog683efdc2008-05-04 10:21:03 +0000510 s->outvol[3] = value & 0x7f; /* ROUT1VOL */
balrogdb502b62008-05-04 10:55:25 +0000511 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000512 break;
513
514 case WM8750_ROUT2V: /* ROUT2 Volume */
515 s->outvol[5] = value & 0x7f; /* ROUT2VOL */
balrog683efdc2008-05-04 10:21:03 +0000516 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000517 break;
518
519 case WM8750_MOUTV: /* MONOOUT Volume */
520 s->outvol[6] = value & 0x7f; /* MONOOUTVOL */
balrogdb502b62008-05-04 10:55:25 +0000521 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000522 break;
523
524 case WM8750_ADCTL2: /* Additional Control (2) */
525 break;
526
527 case WM8750_PWR2: /* Power Management (2) */
528 s->power = value & 0x7e;
balrogdb502b62008-05-04 10:55:25 +0000529 /* TODO: mute/unmute respective paths */
530 wm8750_vol_update(s);
balrogadb86c32007-05-23 22:04:23 +0000531 break;
532
533 case WM8750_IFACE: /* Digital Audio Interface Format */
balrogadb86c32007-05-23 22:04:23 +0000534 s->format = value;
balrogaf83e092008-05-04 12:15:51 +0000535 s->master = (value >> 6) & 1; /* MS */
536 wm8750_clk_update(s, s->master);
balrogadb86c32007-05-23 22:04:23 +0000537 break;
538
539 case WM8750_SRATE: /* Clocking and Sample Rate Control */
540 s->rate = &wm_rate_table[(value >> 1) & 0x1f];
balrogaf83e092008-05-04 12:15:51 +0000541 wm8750_clk_update(s, 0);
balrogadb86c32007-05-23 22:04:23 +0000542 break;
543
544 case WM8750_RESET: /* Reset */
545 wm8750_reset(&s->i2c);
546 break;
547
548#ifdef VERBOSE
549 default:
550 printf("%s: unknown register %02x\n", __FUNCTION__, cmd);
551#endif
552 }
553
554 return 0;
555}
556
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600557static int wm8750_rx(I2CSlave *i2c)
balrogadb86c32007-05-23 22:04:23 +0000558{
559 return 0x00;
560}
561
Juan Quintelac1d803b2009-09-29 22:48:31 +0200562static void wm8750_pre_save(void *opaque)
balrogaa941b92007-05-24 18:50:09 +0000563{
Juan Quintelac1d803b2009-09-29 22:48:31 +0200564 WM8750State *s = opaque;
balrogaa941b92007-05-24 18:50:09 +0000565
Stefan Weil9841aee2012-01-09 19:32:04 +0100566 s->rate_vmstate = s->rate - wm_rate_table;
balrogaa941b92007-05-24 18:50:09 +0000567}
568
Juan Quintelac1d803b2009-09-29 22:48:31 +0200569static int wm8750_post_load(void *opaque, int version_id)
balrogaa941b92007-05-24 18:50:09 +0000570{
Juan Quintelac1d803b2009-09-29 22:48:31 +0200571 WM8750State *s = opaque;
balrogaa941b92007-05-24 18:50:09 +0000572
Juan Quintelac1d803b2009-09-29 22:48:31 +0200573 s->rate = &wm_rate_table[s->rate_vmstate & 0x1f];
balrogaa941b92007-05-24 18:50:09 +0000574 return 0;
575}
576
Juan Quintelac1d803b2009-09-29 22:48:31 +0200577static const VMStateDescription vmstate_wm8750 = {
578 .name = CODEC,
579 .version_id = 0,
580 .minimum_version_id = 0,
581 .minimum_version_id_old = 0,
582 .pre_save = wm8750_pre_save,
583 .post_load = wm8750_post_load,
584 .fields = (VMStateField []) {
585 VMSTATE_UINT8_ARRAY(i2c_data, WM8750State, 2),
586 VMSTATE_INT32(i2c_len, WM8750State),
587 VMSTATE_INT32(enable, WM8750State),
588 VMSTATE_INT32(idx_in, WM8750State),
589 VMSTATE_INT32(req_in, WM8750State),
590 VMSTATE_INT32(idx_out, WM8750State),
591 VMSTATE_INT32(req_out, WM8750State),
592 VMSTATE_UINT8_ARRAY(outvol, WM8750State, 7),
593 VMSTATE_UINT8_ARRAY(outmute, WM8750State, 2),
594 VMSTATE_UINT8_ARRAY(invol, WM8750State, 4),
595 VMSTATE_UINT8_ARRAY(inmute, WM8750State, 2),
596 VMSTATE_UINT8_ARRAY(diff, WM8750State, 2),
597 VMSTATE_UINT8(pol, WM8750State),
598 VMSTATE_UINT8(ds, WM8750State),
599 VMSTATE_UINT8_ARRAY(monomix, WM8750State, 2),
600 VMSTATE_UINT8(alc, WM8750State),
601 VMSTATE_UINT8(mute, WM8750State),
602 VMSTATE_UINT8_ARRAY(path, WM8750State, 4),
603 VMSTATE_UINT8_ARRAY(mpath, WM8750State, 2),
604 VMSTATE_UINT8(format, WM8750State),
605 VMSTATE_UINT8(power, WM8750State),
606 VMSTATE_UINT8(rate_vmstate, WM8750State),
607 VMSTATE_I2C_SLAVE(i2c, WM8750State),
608 VMSTATE_END_OF_LIST()
609 }
610};
611
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600612static int wm8750_init(I2CSlave *i2c)
balrogadb86c32007-05-23 22:04:23 +0000613{
Paul Brookcdbe40c2009-05-14 22:35:08 +0100614 WM8750State *s = FROM_I2C_SLAVE(WM8750State, i2c);
balrogadb86c32007-05-23 22:04:23 +0000615
malc1a7dafc2009-05-14 03:11:35 +0400616 AUD_register_card(CODEC, &s->card);
balrogadb86c32007-05-23 22:04:23 +0000617 wm8750_reset(&s->i2c);
618
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200619 return 0;
balrogadb86c32007-05-23 22:04:23 +0000620}
621
balrog523111e2008-04-24 21:01:40 +0000622#if 0
Anthony Liguori9e07bdf2011-12-04 20:28:27 -0600623static void wm8750_fini(I2CSlave *i2c)
balrogadb86c32007-05-23 22:04:23 +0000624{
Paul Brookbc24a222009-05-10 01:44:56 +0100625 WM8750State *s = (WM8750State *) i2c;
balrogadb86c32007-05-23 22:04:23 +0000626 wm8750_reset(&s->i2c);
627 AUD_remove_card(&s->card);
Anthony Liguori7267c092011-08-20 22:09:37 -0500628 g_free(s);
balrogadb86c32007-05-23 22:04:23 +0000629}
balrog523111e2008-04-24 21:01:40 +0000630#endif
balrogadb86c32007-05-23 22:04:23 +0000631
Paul Brookcdbe40c2009-05-14 22:35:08 +0100632void wm8750_data_req_set(DeviceState *dev,
balrogadb86c32007-05-23 22:04:23 +0000633 void (*data_req)(void *, int, int), void *opaque)
634{
Andreas Färber8aae84a2013-01-25 09:12:54 +0100635 WM8750State *s = FROM_I2C_SLAVE(WM8750State, I2C_SLAVE(dev));
balrogadb86c32007-05-23 22:04:23 +0000636 s->data_req = data_req;
637 s->opaque = opaque;
638}
639
640void wm8750_dac_dat(void *opaque, uint32_t sample)
641{
Paul Brookbc24a222009-05-10 01:44:56 +0100642 WM8750State *s = (WM8750State *) opaque;
balrogaf83e092008-05-04 12:15:51 +0000643
balrog683efdc2008-05-04 10:21:03 +0000644 *(uint32_t *) &s->data_out[s->idx_out] = sample;
balrogadb86c32007-05-23 22:04:23 +0000645 s->req_out -= 4;
646 s->idx_out += 4;
647 if (s->idx_out >= sizeof(s->data_out) || s->req_out <= 0)
648 wm8750_out_flush(s);
649}
650
balrog662caa62008-04-26 12:00:18 +0000651void *wm8750_dac_buffer(void *opaque, int samples)
652{
Paul Brookbc24a222009-05-10 01:44:56 +0100653 WM8750State *s = (WM8750State *) opaque;
balrog662caa62008-04-26 12:00:18 +0000654 /* XXX: Should check if there are <i>samples</i> free samples available */
655 void *ret = s->data_out + s->idx_out;
656
657 s->idx_out += samples << 2;
658 s->req_out -= samples << 2;
659 return ret;
660}
661
662void wm8750_dac_commit(void *opaque)
663{
Paul Brookbc24a222009-05-10 01:44:56 +0100664 WM8750State *s = (WM8750State *) opaque;
balrog662caa62008-04-26 12:00:18 +0000665
blueswir174425112009-04-07 18:22:35 +0000666 wm8750_out_flush(s);
balrog662caa62008-04-26 12:00:18 +0000667}
668
balrogadb86c32007-05-23 22:04:23 +0000669uint32_t wm8750_adc_dat(void *opaque)
670{
Paul Brookbc24a222009-05-10 01:44:56 +0100671 WM8750State *s = (WM8750State *) opaque;
balrogadb86c32007-05-23 22:04:23 +0000672 uint32_t *data;
balrogaf83e092008-05-04 12:15:51 +0000673
balrogadb86c32007-05-23 22:04:23 +0000674 if (s->idx_in >= sizeof(s->data_in))
675 wm8750_in_load(s);
balrogaf83e092008-05-04 12:15:51 +0000676
balrogadb86c32007-05-23 22:04:23 +0000677 data = (uint32_t *) &s->data_in[s->idx_in];
678 s->req_in -= 4;
679 s->idx_in += 4;
balrog683efdc2008-05-04 10:21:03 +0000680 return *data;
balrogadb86c32007-05-23 22:04:23 +0000681}
balrogaf83e092008-05-04 12:15:51 +0000682
balrogb0f74c82008-11-12 17:36:08 +0000683void wm8750_set_bclk_in(void *opaque, int new_hz)
balrogaf83e092008-05-04 12:15:51 +0000684{
Paul Brookbc24a222009-05-10 01:44:56 +0100685 WM8750State *s = (WM8750State *) opaque;
balrogaf83e092008-05-04 12:15:51 +0000686
balrogb0f74c82008-11-12 17:36:08 +0000687 s->ext_adc_hz = new_hz;
688 s->ext_dac_hz = new_hz;
balrogaf83e092008-05-04 12:15:51 +0000689 wm8750_clk_update(s, 1);
690}
Paul Brookcdbe40c2009-05-14 22:35:08 +0100691
Anthony Liguorib5ea9322011-12-04 20:39:20 -0600692static void wm8750_class_init(ObjectClass *klass, void *data)
693{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600694 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguorib5ea9322011-12-04 20:39:20 -0600695 I2CSlaveClass *sc = I2C_SLAVE_CLASS(klass);
696
697 sc->init = wm8750_init;
698 sc->event = wm8750_event;
699 sc->recv = wm8750_rx;
700 sc->send = wm8750_tx;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600701 dc->vmsd = &vmstate_wm8750;
Anthony Liguorib5ea9322011-12-04 20:39:20 -0600702}
703
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100704static const TypeInfo wm8750_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600705 .name = "wm8750",
706 .parent = TYPE_I2C_SLAVE,
707 .instance_size = sizeof(WM8750State),
708 .class_init = wm8750_class_init,
Paul Brookcdbe40c2009-05-14 22:35:08 +0100709};
710
Andreas Färber83f7d432012-02-09 15:20:55 +0100711static void wm8750_register_types(void)
Paul Brookcdbe40c2009-05-14 22:35:08 +0100712{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600713 type_register_static(&wm8750_info);
Paul Brookcdbe40c2009-05-14 22:35:08 +0100714}
715
Andreas Färber83f7d432012-02-09 15:20:55 +0100716type_init(wm8750_register_types)