bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1 | /* |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 2 | * QEMU generic PowerPC hardware System Emulator |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 24 | #include "vl.h" |
| 25 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 26 | //#define PPC_DEBUG_IRQ |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 27 | //#define PPC_DEBUG_TB |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 28 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 29 | extern FILE *logfile; |
| 30 | extern int loglevel; |
| 31 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 32 | static void cpu_ppc_tb_stop (CPUState *env); |
| 33 | static void cpu_ppc_tb_start (CPUState *env); |
| 34 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 35 | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 36 | { |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 37 | if (level) { |
| 38 | env->pending_interrupts |= 1 << n_IRQ; |
| 39 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 40 | } else { |
| 41 | env->pending_interrupts &= ~(1 << n_IRQ); |
| 42 | if (env->pending_interrupts == 0) |
| 43 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 44 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 45 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 46 | if (loglevel & CPU_LOG_INT) { |
| 47 | fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n", |
| 48 | __func__, env, n_IRQ, level, |
| 49 | env->pending_interrupts, env->interrupt_request); |
| 50 | } |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 51 | #endif |
| 52 | } |
| 53 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 54 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
| 55 | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 56 | { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 57 | CPUState *env = opaque; |
| 58 | int cur_level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 59 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 60 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 61 | if (loglevel & CPU_LOG_INT) { |
| 62 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
| 63 | env, pin, level); |
| 64 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 65 | #endif |
| 66 | cur_level = (env->irq_input_state >> pin) & 1; |
| 67 | /* Don't generate spurious events */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 68 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 69 | switch (pin) { |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 70 | case PPC6xx_INPUT_TBEN: |
| 71 | /* Level sensitive - active high */ |
| 72 | #if defined(PPC_DEBUG_IRQ) |
| 73 | if (loglevel & CPU_LOG_INT) { |
| 74 | fprintf(logfile, "%s: %s the time base\n", |
| 75 | __func__, level ? "start" : "stop"); |
| 76 | } |
| 77 | #endif |
| 78 | if (level) { |
| 79 | cpu_ppc_tb_start(env); |
| 80 | } else { |
| 81 | cpu_ppc_tb_stop(env); |
| 82 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 83 | case PPC6xx_INPUT_INT: |
| 84 | /* Level sensitive - active high */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 85 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 86 | if (loglevel & CPU_LOG_INT) { |
| 87 | fprintf(logfile, "%s: set the external IRQ state to %d\n", |
| 88 | __func__, level); |
| 89 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 90 | #endif |
| 91 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 92 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 93 | case PPC6xx_INPUT_SMI: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 94 | /* Level sensitive - active high */ |
| 95 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 96 | if (loglevel & CPU_LOG_INT) { |
| 97 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", |
| 98 | __func__, level); |
| 99 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 100 | #endif |
| 101 | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
| 102 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 103 | case PPC6xx_INPUT_MCP: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 104 | /* Negative edge sensitive */ |
| 105 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 106 | * 603/604/740/750: check HID0[EMCP] |
| 107 | */ |
| 108 | if (cur_level == 1 && level == 0) { |
| 109 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 110 | if (loglevel & CPU_LOG_INT) { |
| 111 | fprintf(logfile, "%s: raise machine check state\n", |
| 112 | __func__); |
| 113 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 114 | #endif |
| 115 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
| 116 | } |
| 117 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 118 | case PPC6xx_INPUT_CKSTP_IN: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 119 | /* Level sensitive - active low */ |
| 120 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
j_mayer | e63ecc6 | 2007-10-14 08:48:23 +0000 | [diff] [blame] | 121 | /* XXX: Note that the only way to restart the CPU is to reset it */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 122 | if (level) { |
| 123 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 124 | if (loglevel & CPU_LOG_INT) { |
| 125 | fprintf(logfile, "%s: stop the CPU\n", __func__); |
| 126 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 127 | #endif |
| 128 | env->halted = 1; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 129 | } |
| 130 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 131 | case PPC6xx_INPUT_HRESET: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 132 | /* Level sensitive - active low */ |
| 133 | if (level) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 134 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 135 | if (loglevel & CPU_LOG_INT) { |
| 136 | fprintf(logfile, "%s: reset the CPU\n", __func__); |
| 137 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 138 | #endif |
j_mayer | ef397e8 | 2007-10-29 10:22:58 +0000 | [diff] [blame] | 139 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 140 | /* XXX: TOFIX */ |
| 141 | #if 0 |
| 142 | cpu_ppc_reset(env); |
| 143 | #else |
| 144 | qemu_system_reset_request(); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 145 | #endif |
| 146 | } |
| 147 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 148 | case PPC6xx_INPUT_SRESET: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 149 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 150 | if (loglevel & CPU_LOG_INT) { |
| 151 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", |
| 152 | __func__, level); |
| 153 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 154 | #endif |
| 155 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
| 156 | break; |
| 157 | default: |
| 158 | /* Unknown pin - do nothing */ |
| 159 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 160 | if (loglevel & CPU_LOG_INT) { |
| 161 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
| 162 | } |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 163 | #endif |
| 164 | return; |
| 165 | } |
| 166 | if (level) |
| 167 | env->irq_input_state |= 1 << pin; |
| 168 | else |
| 169 | env->irq_input_state &= ~(1 << pin); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 170 | } |
| 171 | } |
| 172 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 173 | void ppc6xx_irq_init (CPUState *env) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 174 | { |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame^] | 175 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, |
| 176 | PPC6xx_INPUT_NB); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 177 | } |
| 178 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 179 | #if defined(TARGET_PPC64) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 180 | /* PowerPC 970 internal IRQ controller */ |
| 181 | static void ppc970_set_irq (void *opaque, int pin, int level) |
| 182 | { |
| 183 | CPUState *env = opaque; |
| 184 | int cur_level; |
| 185 | |
| 186 | #if defined(PPC_DEBUG_IRQ) |
| 187 | if (loglevel & CPU_LOG_INT) { |
| 188 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
| 189 | env, pin, level); |
| 190 | } |
| 191 | #endif |
| 192 | cur_level = (env->irq_input_state >> pin) & 1; |
| 193 | /* Don't generate spurious events */ |
| 194 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 195 | switch (pin) { |
| 196 | case PPC970_INPUT_INT: |
| 197 | /* Level sensitive - active high */ |
| 198 | #if defined(PPC_DEBUG_IRQ) |
| 199 | if (loglevel & CPU_LOG_INT) { |
| 200 | fprintf(logfile, "%s: set the external IRQ state to %d\n", |
| 201 | __func__, level); |
| 202 | } |
| 203 | #endif |
| 204 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 205 | break; |
| 206 | case PPC970_INPUT_THINT: |
| 207 | /* Level sensitive - active high */ |
| 208 | #if defined(PPC_DEBUG_IRQ) |
| 209 | if (loglevel & CPU_LOG_INT) { |
| 210 | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, |
| 211 | level); |
| 212 | } |
| 213 | #endif |
| 214 | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
| 215 | break; |
| 216 | case PPC970_INPUT_MCP: |
| 217 | /* Negative edge sensitive */ |
| 218 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 219 | * 603/604/740/750: check HID0[EMCP] |
| 220 | */ |
| 221 | if (cur_level == 1 && level == 0) { |
| 222 | #if defined(PPC_DEBUG_IRQ) |
| 223 | if (loglevel & CPU_LOG_INT) { |
| 224 | fprintf(logfile, "%s: raise machine check state\n", |
| 225 | __func__); |
| 226 | } |
| 227 | #endif |
| 228 | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
| 229 | } |
| 230 | break; |
| 231 | case PPC970_INPUT_CKSTP: |
| 232 | /* Level sensitive - active low */ |
| 233 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
| 234 | if (level) { |
| 235 | #if defined(PPC_DEBUG_IRQ) |
| 236 | if (loglevel & CPU_LOG_INT) { |
| 237 | fprintf(logfile, "%s: stop the CPU\n", __func__); |
| 238 | } |
| 239 | #endif |
| 240 | env->halted = 1; |
| 241 | } else { |
| 242 | #if defined(PPC_DEBUG_IRQ) |
| 243 | if (loglevel & CPU_LOG_INT) { |
| 244 | fprintf(logfile, "%s: restart the CPU\n", __func__); |
| 245 | } |
| 246 | #endif |
| 247 | env->halted = 0; |
| 248 | } |
| 249 | break; |
| 250 | case PPC970_INPUT_HRESET: |
| 251 | /* Level sensitive - active low */ |
| 252 | if (level) { |
| 253 | #if 0 // XXX: TOFIX |
| 254 | #if defined(PPC_DEBUG_IRQ) |
| 255 | if (loglevel & CPU_LOG_INT) { |
| 256 | fprintf(logfile, "%s: reset the CPU\n", __func__); |
| 257 | } |
| 258 | #endif |
| 259 | cpu_reset(env); |
| 260 | #endif |
| 261 | } |
| 262 | break; |
| 263 | case PPC970_INPUT_SRESET: |
| 264 | #if defined(PPC_DEBUG_IRQ) |
| 265 | if (loglevel & CPU_LOG_INT) { |
| 266 | fprintf(logfile, "%s: set the RESET IRQ state to %d\n", |
| 267 | __func__, level); |
| 268 | } |
| 269 | #endif |
| 270 | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
| 271 | break; |
| 272 | case PPC970_INPUT_TBEN: |
| 273 | #if defined(PPC_DEBUG_IRQ) |
| 274 | if (loglevel & CPU_LOG_INT) { |
| 275 | fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, |
| 276 | level); |
| 277 | } |
| 278 | #endif |
| 279 | /* XXX: TODO */ |
| 280 | break; |
| 281 | default: |
| 282 | /* Unknown pin - do nothing */ |
| 283 | #if defined(PPC_DEBUG_IRQ) |
| 284 | if (loglevel & CPU_LOG_INT) { |
| 285 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
| 286 | } |
| 287 | #endif |
| 288 | return; |
| 289 | } |
| 290 | if (level) |
| 291 | env->irq_input_state |= 1 << pin; |
| 292 | else |
| 293 | env->irq_input_state &= ~(1 << pin); |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | void ppc970_irq_init (CPUState *env) |
| 298 | { |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame^] | 299 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, |
| 300 | PPC970_INPUT_NB); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 301 | } |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 302 | #endif /* defined(TARGET_PPC64) */ |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 303 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 304 | /* PowerPC 40x internal IRQ controller */ |
| 305 | static void ppc40x_set_irq (void *opaque, int pin, int level) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 306 | { |
| 307 | CPUState *env = opaque; |
| 308 | int cur_level; |
| 309 | |
| 310 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 311 | if (loglevel & CPU_LOG_INT) { |
| 312 | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
| 313 | env, pin, level); |
| 314 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 315 | #endif |
| 316 | cur_level = (env->irq_input_state >> pin) & 1; |
| 317 | /* Don't generate spurious events */ |
| 318 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 319 | switch (pin) { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 320 | case PPC40x_INPUT_RESET_SYS: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 321 | if (level) { |
| 322 | #if defined(PPC_DEBUG_IRQ) |
| 323 | if (loglevel & CPU_LOG_INT) { |
| 324 | fprintf(logfile, "%s: reset the PowerPC system\n", |
| 325 | __func__); |
| 326 | } |
| 327 | #endif |
| 328 | ppc40x_system_reset(env); |
| 329 | } |
| 330 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 331 | case PPC40x_INPUT_RESET_CHIP: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 332 | if (level) { |
| 333 | #if defined(PPC_DEBUG_IRQ) |
| 334 | if (loglevel & CPU_LOG_INT) { |
| 335 | fprintf(logfile, "%s: reset the PowerPC chip\n", __func__); |
| 336 | } |
| 337 | #endif |
| 338 | ppc40x_chip_reset(env); |
| 339 | } |
| 340 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 341 | case PPC40x_INPUT_RESET_CORE: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 342 | /* XXX: TODO: update DBSR[MRR] */ |
| 343 | if (level) { |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 344 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 345 | if (loglevel & CPU_LOG_INT) { |
| 346 | fprintf(logfile, "%s: reset the PowerPC core\n", __func__); |
| 347 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 348 | #endif |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 349 | ppc40x_core_reset(env); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 350 | } |
| 351 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 352 | case PPC40x_INPUT_CINT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 353 | /* Level sensitive - active high */ |
| 354 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 355 | if (loglevel & CPU_LOG_INT) { |
| 356 | fprintf(logfile, "%s: set the critical IRQ state to %d\n", |
| 357 | __func__, level); |
| 358 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 359 | #endif |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 360 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 361 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 362 | case PPC40x_INPUT_INT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 363 | /* Level sensitive - active high */ |
| 364 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 365 | if (loglevel & CPU_LOG_INT) { |
| 366 | fprintf(logfile, "%s: set the external IRQ state to %d\n", |
| 367 | __func__, level); |
| 368 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 369 | #endif |
| 370 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 371 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 372 | case PPC40x_INPUT_HALT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 373 | /* Level sensitive - active low */ |
| 374 | if (level) { |
| 375 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 376 | if (loglevel & CPU_LOG_INT) { |
| 377 | fprintf(logfile, "%s: stop the CPU\n", __func__); |
| 378 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 379 | #endif |
| 380 | env->halted = 1; |
| 381 | } else { |
| 382 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 383 | if (loglevel & CPU_LOG_INT) { |
| 384 | fprintf(logfile, "%s: restart the CPU\n", __func__); |
| 385 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 386 | #endif |
| 387 | env->halted = 0; |
| 388 | } |
| 389 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 390 | case PPC40x_INPUT_DEBUG: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 391 | /* Level sensitive - active high */ |
| 392 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 393 | if (loglevel & CPU_LOG_INT) { |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 394 | fprintf(logfile, "%s: set the debug pin state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 395 | __func__, level); |
| 396 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 397 | #endif |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 398 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 399 | break; |
| 400 | default: |
| 401 | /* Unknown pin - do nothing */ |
| 402 | #if defined(PPC_DEBUG_IRQ) |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 403 | if (loglevel & CPU_LOG_INT) { |
| 404 | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
| 405 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 406 | #endif |
| 407 | return; |
| 408 | } |
| 409 | if (level) |
| 410 | env->irq_input_state |= 1 << pin; |
| 411 | else |
| 412 | env->irq_input_state &= ~(1 << pin); |
| 413 | } |
| 414 | } |
| 415 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 416 | void ppc40x_irq_init (CPUState *env) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 417 | { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 418 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
| 419 | env, PPC40x_INPUT_NB); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 420 | } |
| 421 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 422 | /*****************************************************************************/ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 423 | /* PowerPC time base and decrementer emulation */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 424 | struct ppc_tb_t { |
| 425 | /* Time base management */ |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 426 | int64_t tb_offset; /* Compensation */ |
| 427 | int64_t atb_offset; /* Compensation */ |
| 428 | uint32_t tb_freq; /* TB frequency */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 429 | /* Decrementer management */ |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 430 | uint64_t decr_next; /* Tick for next decr interrupt */ |
| 431 | uint32_t decr_freq; /* decrementer frequency */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 432 | struct QEMUTimer *decr_timer; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 433 | /* Hypervisor decrementer management */ |
| 434 | uint64_t hdecr_next; /* Tick for next hdecr interrupt */ |
| 435 | struct QEMUTimer *hdecr_timer; |
| 436 | uint64_t purr_load; |
| 437 | uint64_t purr_start; |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 438 | void *opaque; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 439 | }; |
| 440 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 441 | static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 442 | int64_t tb_offset) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 443 | { |
| 444 | /* TB time in tb periods */ |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 445 | return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 446 | } |
| 447 | |
| 448 | uint32_t cpu_ppc_load_tbl (CPUState *env) |
| 449 | { |
| 450 | ppc_tb_t *tb_env = env->tb_env; |
| 451 | uint64_t tb; |
| 452 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 453 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 454 | #if defined(PPC_DEBUG_TB) |
| 455 | if (loglevel != 0) { |
| 456 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 457 | } |
| 458 | #endif |
| 459 | |
| 460 | return tb & 0xFFFFFFFF; |
| 461 | } |
| 462 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 463 | static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 464 | { |
| 465 | ppc_tb_t *tb_env = env->tb_env; |
| 466 | uint64_t tb; |
| 467 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 468 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 469 | #if defined(PPC_DEBUG_TB) |
| 470 | if (loglevel != 0) { |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 471 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); |
| 472 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 473 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 474 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 475 | return tb >> 32; |
| 476 | } |
| 477 | |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 478 | uint32_t cpu_ppc_load_tbu (CPUState *env) |
| 479 | { |
| 480 | return _cpu_ppc_load_tbu(env); |
| 481 | } |
| 482 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 483 | static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 484 | int64_t *tb_offsetp, |
| 485 | uint64_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 486 | { |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 487 | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 488 | #ifdef PPC_DEBUG_TB |
| 489 | if (loglevel != 0) { |
| 490 | fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value, |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 491 | *tb_offsetp); |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 492 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 493 | #endif |
| 494 | } |
| 495 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 496 | void cpu_ppc_store_tbl (CPUState *env, uint32_t value) |
| 497 | { |
| 498 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 499 | uint64_t tb; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 500 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 501 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 502 | tb &= 0xFFFFFFFF00000000ULL; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 503 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
| 504 | &tb_env->tb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 505 | } |
| 506 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 507 | static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 508 | { |
| 509 | ppc_tb_t *tb_env = env->tb_env; |
| 510 | uint64_t tb; |
| 511 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 512 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 513 | tb &= 0x00000000FFFFFFFFULL; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 514 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
| 515 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 516 | } |
| 517 | |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 518 | void cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
| 519 | { |
| 520 | _cpu_ppc_store_tbu(env, value); |
| 521 | } |
| 522 | |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 523 | uint32_t cpu_ppc_load_atbl (CPUState *env) |
| 524 | { |
| 525 | ppc_tb_t *tb_env = env->tb_env; |
| 526 | uint64_t tb; |
| 527 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 528 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 529 | #if defined(PPC_DEBUG_TB) |
| 530 | if (loglevel != 0) { |
| 531 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); |
| 532 | } |
| 533 | #endif |
| 534 | |
| 535 | return tb & 0xFFFFFFFF; |
| 536 | } |
| 537 | |
| 538 | uint32_t cpu_ppc_load_atbu (CPUState *env) |
| 539 | { |
| 540 | ppc_tb_t *tb_env = env->tb_env; |
| 541 | uint64_t tb; |
| 542 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 543 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 544 | #if defined(PPC_DEBUG_TB) |
| 545 | if (loglevel != 0) { |
| 546 | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb); |
| 547 | } |
| 548 | #endif |
| 549 | |
| 550 | return tb >> 32; |
| 551 | } |
| 552 | |
| 553 | void cpu_ppc_store_atbl (CPUState *env, uint32_t value) |
| 554 | { |
| 555 | ppc_tb_t *tb_env = env->tb_env; |
| 556 | uint64_t tb; |
| 557 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 558 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 559 | tb &= 0xFFFFFFFF00000000ULL; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 560 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
| 561 | &tb_env->atb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | void cpu_ppc_store_atbu (CPUState *env, uint32_t value) |
| 565 | { |
| 566 | ppc_tb_t *tb_env = env->tb_env; |
| 567 | uint64_t tb; |
| 568 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 569 | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 570 | tb &= 0x00000000FFFFFFFFULL; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 571 | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
| 572 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); |
| 573 | } |
| 574 | |
| 575 | static void cpu_ppc_tb_stop (CPUState *env) |
| 576 | { |
| 577 | ppc_tb_t *tb_env = env->tb_env; |
| 578 | uint64_t tb, atb, vmclk; |
| 579 | |
| 580 | /* If the time base is already frozen, do nothing */ |
| 581 | if (tb_env->tb_freq != 0) { |
| 582 | vmclk = qemu_get_clock(vm_clock); |
| 583 | /* Get the time base */ |
| 584 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
| 585 | /* Get the alternate time base */ |
| 586 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
| 587 | /* Store the time base value (ie compute the current offset) */ |
| 588 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 589 | /* Store the alternate time base value (compute the current offset) */ |
| 590 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 591 | /* Set the time base frequency to zero */ |
| 592 | tb_env->tb_freq = 0; |
| 593 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | static void cpu_ppc_tb_start (CPUState *env) |
| 598 | { |
| 599 | ppc_tb_t *tb_env = env->tb_env; |
| 600 | uint64_t tb, atb, vmclk; |
| 601 | |
| 602 | /* If the time base is not frozen, do nothing */ |
| 603 | if (tb_env->tb_freq == 0) { |
| 604 | vmclk = qemu_get_clock(vm_clock); |
| 605 | /* Get the time base from tb_offset */ |
| 606 | tb = tb_env->tb_offset; |
| 607 | /* Get the alternate time base from atb_offset */ |
| 608 | atb = tb_env->atb_offset; |
| 609 | /* Restore the tb frequency from the decrementer frequency */ |
| 610 | tb_env->tb_freq = tb_env->decr_freq; |
| 611 | /* Store the time base value */ |
| 612 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 613 | /* Store the alternate time base value */ |
| 614 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 615 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 616 | } |
| 617 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 618 | static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, |
| 619 | uint64_t *next) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 620 | { |
| 621 | ppc_tb_t *tb_env = env->tb_env; |
| 622 | uint32_t decr; |
bellard | 4e588a4 | 2005-07-07 21:46:29 +0000 | [diff] [blame] | 623 | int64_t diff; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 624 | |
bellard | 4e588a4 | 2005-07-07 21:46:29 +0000 | [diff] [blame] | 625 | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
| 626 | if (diff >= 0) |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 627 | decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); |
bellard | 4e588a4 | 2005-07-07 21:46:29 +0000 | [diff] [blame] | 628 | else |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 629 | decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 630 | #if defined(PPC_DEBUG_TB) |
| 631 | if (loglevel != 0) { |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 632 | fprintf(logfile, "%s: 0x%08x\n", __func__, decr); |
| 633 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 634 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 635 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 636 | return decr; |
| 637 | } |
| 638 | |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 639 | uint32_t cpu_ppc_load_decr (CPUState *env) |
| 640 | { |
| 641 | ppc_tb_t *tb_env = env->tb_env; |
| 642 | |
| 643 | return _cpu_ppc_load_decr(env, &tb_env->decr_next); |
| 644 | } |
| 645 | |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 646 | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
| 647 | { |
| 648 | ppc_tb_t *tb_env = env->tb_env; |
| 649 | |
| 650 | return _cpu_ppc_load_decr(env, &tb_env->hdecr_next); |
| 651 | } |
| 652 | |
| 653 | uint64_t cpu_ppc_load_purr (CPUState *env) |
| 654 | { |
| 655 | ppc_tb_t *tb_env = env->tb_env; |
| 656 | uint64_t diff; |
| 657 | |
| 658 | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; |
j_mayer | b33c17e | 2007-10-07 17:30:34 +0000 | [diff] [blame] | 659 | |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 660 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
| 661 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 662 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 663 | /* When decrementer expires, |
| 664 | * all we need to do is generate or queue a CPU exception |
| 665 | */ |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 666 | static always_inline void cpu_ppc_decr_excp (CPUState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 667 | { |
| 668 | /* Raise it */ |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 669 | #ifdef PPC_DEBUG_TB |
| 670 | if (loglevel != 0) { |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 671 | fprintf(logfile, "raise decrementer exception\n"); |
| 672 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 673 | #endif |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 674 | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 675 | } |
| 676 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 677 | static always_inline void cpu_ppc_hdecr_excp (CPUState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 678 | { |
| 679 | /* Raise it */ |
| 680 | #ifdef PPC_DEBUG_TB |
| 681 | if (loglevel != 0) { |
| 682 | fprintf(logfile, "raise decrementer exception\n"); |
| 683 | } |
| 684 | #endif |
| 685 | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); |
| 686 | } |
| 687 | |
| 688 | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
j_mayer | b33c17e | 2007-10-07 17:30:34 +0000 | [diff] [blame] | 689 | struct QEMUTimer *timer, |
| 690 | void (*raise_excp)(CPUState *), |
| 691 | uint32_t decr, uint32_t value, |
| 692 | int is_excp) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 693 | { |
| 694 | ppc_tb_t *tb_env = env->tb_env; |
| 695 | uint64_t now, next; |
| 696 | |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 697 | #ifdef PPC_DEBUG_TB |
| 698 | if (loglevel != 0) { |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 699 | fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value); |
| 700 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 701 | #endif |
| 702 | now = qemu_get_clock(vm_clock); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 703 | next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 704 | if (is_excp) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 705 | next += *nextp - now; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 706 | if (next == now) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 707 | next++; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 708 | *nextp = next; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 709 | /* Adjust timer */ |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 710 | qemu_mod_timer(timer, next); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 711 | /* If we set a negative value and the decrementer was positive, |
| 712 | * raise an exception. |
| 713 | */ |
| 714 | if ((value & 0x80000000) && !(decr & 0x80000000)) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 715 | (*raise_excp)(env); |
| 716 | } |
| 717 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 718 | static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
| 719 | uint32_t value, int is_excp) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 720 | { |
| 721 | ppc_tb_t *tb_env = env->tb_env; |
| 722 | |
| 723 | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
| 724 | &cpu_ppc_decr_excp, decr, value, is_excp); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 725 | } |
| 726 | |
| 727 | void cpu_ppc_store_decr (CPUState *env, uint32_t value) |
| 728 | { |
| 729 | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0); |
| 730 | } |
| 731 | |
| 732 | static void cpu_ppc_decr_cb (void *opaque) |
| 733 | { |
| 734 | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
| 735 | } |
| 736 | |
j_mayer | b068d6a | 2007-10-07 17:13:44 +0000 | [diff] [blame] | 737 | static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, |
| 738 | uint32_t value, int is_excp) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 739 | { |
| 740 | ppc_tb_t *tb_env = env->tb_env; |
| 741 | |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 742 | if (tb_env->hdecr_timer != NULL) { |
| 743 | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
| 744 | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
| 745 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 746 | } |
| 747 | |
| 748 | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value) |
| 749 | { |
| 750 | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0); |
| 751 | } |
| 752 | |
| 753 | static void cpu_ppc_hdecr_cb (void *opaque) |
| 754 | { |
| 755 | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
| 756 | } |
| 757 | |
| 758 | void cpu_ppc_store_purr (CPUState *env, uint64_t value) |
| 759 | { |
| 760 | ppc_tb_t *tb_env = env->tb_env; |
| 761 | |
| 762 | tb_env->purr_load = value; |
| 763 | tb_env->purr_start = qemu_get_clock(vm_clock); |
| 764 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 765 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 766 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
| 767 | { |
| 768 | CPUState *env = opaque; |
| 769 | ppc_tb_t *tb_env = env->tb_env; |
| 770 | |
| 771 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 772 | tb_env->decr_freq = freq; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 773 | /* There is a bug in Linux 2.4 kernels: |
| 774 | * if a decrementer exception is pending when it enables msr_ee at startup, |
| 775 | * it's not ready to handle it... |
| 776 | */ |
| 777 | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 778 | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
| 779 | cpu_ppc_store_purr(env, 0x0000000000000000ULL); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 780 | } |
| 781 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 782 | /* Set up (once) timebase frequency (in Hz) */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 783 | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 784 | { |
| 785 | ppc_tb_t *tb_env; |
| 786 | |
| 787 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); |
| 788 | if (tb_env == NULL) |
| 789 | return NULL; |
| 790 | env->tb_env = tb_env; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 791 | /* Create new timer */ |
| 792 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 793 | if (0) { |
| 794 | /* XXX: find a suitable condition to enable the hypervisor decrementer |
| 795 | */ |
| 796 | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); |
| 797 | } else { |
| 798 | tb_env->hdecr_timer = NULL; |
| 799 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 800 | cpu_ppc_set_tb_clk(env, freq); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 801 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 802 | return &cpu_ppc_set_tb_clk; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 803 | } |
| 804 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 805 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 806 | clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 807 | { |
| 808 | return cpu_ppc_tb_init(env, 7812500); |
| 809 | } |
| 810 | |
| 811 | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 812 | { |
| 813 | _cpu_ppc_store_tbu(env, value); |
| 814 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 815 | |
| 816 | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 817 | { |
| 818 | return _cpu_ppc_load_tbu(env); |
| 819 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 820 | |
| 821 | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value) |
| 822 | { |
| 823 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); |
| 824 | } |
| 825 | |
| 826 | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
| 827 | { |
| 828 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
| 829 | } |
| 830 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 831 | /*****************************************************************************/ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 832 | /* Embedded PowerPC timers */ |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 833 | |
| 834 | /* PIT, FIT & WDT */ |
| 835 | typedef struct ppcemb_timer_t ppcemb_timer_t; |
| 836 | struct ppcemb_timer_t { |
| 837 | uint64_t pit_reload; /* PIT auto-reload value */ |
| 838 | uint64_t fit_next; /* Tick for next FIT interrupt */ |
| 839 | struct QEMUTimer *fit_timer; |
| 840 | uint64_t wdt_next; /* Tick for next WDT interrupt */ |
| 841 | struct QEMUTimer *wdt_timer; |
| 842 | }; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 843 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 844 | /* Fixed interval timer */ |
| 845 | static void cpu_4xx_fit_cb (void *opaque) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 846 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 847 | CPUState *env; |
| 848 | ppc_tb_t *tb_env; |
| 849 | ppcemb_timer_t *ppcemb_timer; |
| 850 | uint64_t now, next; |
| 851 | |
| 852 | env = opaque; |
| 853 | tb_env = env->tb_env; |
| 854 | ppcemb_timer = tb_env->opaque; |
| 855 | now = qemu_get_clock(vm_clock); |
| 856 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
| 857 | case 0: |
| 858 | next = 1 << 9; |
| 859 | break; |
| 860 | case 1: |
| 861 | next = 1 << 13; |
| 862 | break; |
| 863 | case 2: |
| 864 | next = 1 << 17; |
| 865 | break; |
| 866 | case 3: |
| 867 | next = 1 << 21; |
| 868 | break; |
| 869 | default: |
| 870 | /* Cannot occur, but makes gcc happy */ |
| 871 | return; |
| 872 | } |
| 873 | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
| 874 | if (next == now) |
| 875 | next++; |
| 876 | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 877 | env->spr[SPR_40x_TSR] |= 1 << 26; |
| 878 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
| 879 | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 880 | #ifdef PPC_DEBUG_TB |
| 881 | if (loglevel != 0) { |
j_mayer | e96efcf | 2007-04-14 12:17:09 +0000 | [diff] [blame] | 882 | fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
| 883 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 884 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 885 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 886 | #endif |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 887 | } |
| 888 | |
| 889 | /* Programmable interval timer */ |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 890 | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 891 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 892 | ppcemb_timer_t *ppcemb_timer; |
| 893 | uint64_t now, next; |
| 894 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 895 | ppcemb_timer = tb_env->opaque; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 896 | if (ppcemb_timer->pit_reload <= 1 || |
| 897 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
| 898 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
| 899 | /* Stop PIT */ |
| 900 | #ifdef PPC_DEBUG_TB |
| 901 | if (loglevel != 0) { |
| 902 | fprintf(logfile, "%s: stop PIT\n", __func__); |
| 903 | } |
| 904 | #endif |
| 905 | qemu_del_timer(tb_env->decr_timer); |
| 906 | } else { |
| 907 | #ifdef PPC_DEBUG_TB |
| 908 | if (loglevel != 0) { |
| 909 | fprintf(logfile, "%s: start PIT 0x" REGX "\n", |
| 910 | __func__, ppcemb_timer->pit_reload); |
| 911 | } |
| 912 | #endif |
| 913 | now = qemu_get_clock(vm_clock); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 914 | next = now + muldiv64(ppcemb_timer->pit_reload, |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 915 | ticks_per_sec, tb_env->decr_freq); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 916 | if (is_excp) |
| 917 | next += tb_env->decr_next - now; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 918 | if (next == now) |
| 919 | next++; |
| 920 | qemu_mod_timer(tb_env->decr_timer, next); |
| 921 | tb_env->decr_next = next; |
| 922 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 923 | } |
| 924 | |
| 925 | static void cpu_4xx_pit_cb (void *opaque) |
| 926 | { |
| 927 | CPUState *env; |
| 928 | ppc_tb_t *tb_env; |
| 929 | ppcemb_timer_t *ppcemb_timer; |
| 930 | |
| 931 | env = opaque; |
| 932 | tb_env = env->tb_env; |
| 933 | ppcemb_timer = tb_env->opaque; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 934 | env->spr[SPR_40x_TSR] |= 1 << 27; |
| 935 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
| 936 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 937 | start_stop_pit(env, tb_env, 1); |
| 938 | #ifdef PPC_DEBUG_TB |
| 939 | if (loglevel != 0) { |
j_mayer | e96efcf | 2007-04-14 12:17:09 +0000 | [diff] [blame] | 940 | fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
| 941 | "%016" PRIx64 "\n", __func__, |
| 942 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
| 943 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 944 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
| 945 | ppcemb_timer->pit_reload); |
| 946 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 947 | #endif |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 948 | } |
| 949 | |
| 950 | /* Watchdog timer */ |
| 951 | static void cpu_4xx_wdt_cb (void *opaque) |
| 952 | { |
| 953 | CPUState *env; |
| 954 | ppc_tb_t *tb_env; |
| 955 | ppcemb_timer_t *ppcemb_timer; |
| 956 | uint64_t now, next; |
| 957 | |
| 958 | env = opaque; |
| 959 | tb_env = env->tb_env; |
| 960 | ppcemb_timer = tb_env->opaque; |
| 961 | now = qemu_get_clock(vm_clock); |
| 962 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
| 963 | case 0: |
| 964 | next = 1 << 17; |
| 965 | break; |
| 966 | case 1: |
| 967 | next = 1 << 21; |
| 968 | break; |
| 969 | case 2: |
| 970 | next = 1 << 25; |
| 971 | break; |
| 972 | case 3: |
| 973 | next = 1 << 29; |
| 974 | break; |
| 975 | default: |
| 976 | /* Cannot occur, but makes gcc happy */ |
| 977 | return; |
| 978 | } |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 979 | next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 980 | if (next == now) |
| 981 | next++; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 982 | #ifdef PPC_DEBUG_TB |
| 983 | if (loglevel != 0) { |
j_mayer | e96efcf | 2007-04-14 12:17:09 +0000 | [diff] [blame] | 984 | fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 985 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 986 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 987 | #endif |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 988 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
| 989 | case 0x0: |
| 990 | case 0x1: |
| 991 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
| 992 | ppcemb_timer->wdt_next = next; |
| 993 | env->spr[SPR_40x_TSR] |= 1 << 31; |
| 994 | break; |
| 995 | case 0x2: |
| 996 | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
| 997 | ppcemb_timer->wdt_next = next; |
| 998 | env->spr[SPR_40x_TSR] |= 1 << 30; |
| 999 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
| 1000 | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1); |
| 1001 | break; |
| 1002 | case 0x3: |
| 1003 | env->spr[SPR_40x_TSR] &= ~0x30000000; |
| 1004 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; |
| 1005 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
| 1006 | case 0x0: |
| 1007 | /* No reset */ |
| 1008 | break; |
| 1009 | case 0x1: /* Core reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1010 | ppc40x_core_reset(env); |
| 1011 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1012 | case 0x2: /* Chip reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1013 | ppc40x_chip_reset(env); |
| 1014 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1015 | case 0x3: /* System reset */ |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1016 | ppc40x_system_reset(env); |
| 1017 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1018 | } |
| 1019 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1020 | } |
| 1021 | |
| 1022 | void store_40x_pit (CPUState *env, target_ulong val) |
| 1023 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1024 | ppc_tb_t *tb_env; |
| 1025 | ppcemb_timer_t *ppcemb_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1026 | |
| 1027 | tb_env = env->tb_env; |
| 1028 | ppcemb_timer = tb_env->opaque; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1029 | #ifdef PPC_DEBUG_TB |
| 1030 | if (loglevel != 0) { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1031 | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer); |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 1032 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1033 | #endif |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1034 | ppcemb_timer->pit_reload = val; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1035 | start_stop_pit(env, tb_env, 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1036 | } |
| 1037 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1038 | target_ulong load_40x_pit (CPUState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1039 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1040 | return cpu_ppc_load_decr(env); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1041 | } |
| 1042 | |
| 1043 | void store_booke_tsr (CPUState *env, target_ulong val) |
| 1044 | { |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1045 | #ifdef PPC_DEBUG_TB |
| 1046 | if (loglevel != 0) { |
| 1047 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); |
| 1048 | } |
| 1049 | #endif |
| 1050 | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); |
| 1051 | if (val & 0x80000000) |
| 1052 | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1053 | } |
| 1054 | |
| 1055 | void store_booke_tcr (CPUState *env, target_ulong val) |
| 1056 | { |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1057 | ppc_tb_t *tb_env; |
| 1058 | |
| 1059 | tb_env = env->tb_env; |
| 1060 | #ifdef PPC_DEBUG_TB |
| 1061 | if (loglevel != 0) { |
| 1062 | fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val); |
| 1063 | } |
| 1064 | #endif |
| 1065 | env->spr[SPR_40x_TCR] = val & 0xFFC00000; |
| 1066 | start_stop_pit(env, tb_env, 1); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1067 | cpu_4xx_wdt_cb(env); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1068 | } |
| 1069 | |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1070 | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
| 1071 | { |
| 1072 | CPUState *env = opaque; |
| 1073 | ppc_tb_t *tb_env = env->tb_env; |
| 1074 | |
| 1075 | #ifdef PPC_DEBUG_TB |
| 1076 | if (loglevel != 0) { |
| 1077 | fprintf(logfile, "%s set new frequency to %u\n", __func__, freq); |
| 1078 | } |
| 1079 | #endif |
| 1080 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1081 | tb_env->decr_freq = freq; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1082 | /* XXX: we should also update all timers */ |
| 1083 | } |
| 1084 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1085 | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1086 | { |
| 1087 | ppc_tb_t *tb_env; |
| 1088 | ppcemb_timer_t *ppcemb_timer; |
| 1089 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1090 | tb_env = qemu_mallocz(sizeof(ppc_tb_t)); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1091 | if (tb_env == NULL) { |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1092 | return NULL; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1093 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1094 | env->tb_env = tb_env; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1095 | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t)); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1096 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1097 | tb_env->decr_freq = freq; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1098 | tb_env->opaque = ppcemb_timer; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1099 | #ifdef PPC_DEBUG_TB |
| 1100 | if (loglevel != 0) { |
| 1101 | fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer, |
| 1102 | &ppc_emb_set_tb_clk); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1103 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1104 | #endif |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1105 | if (ppcemb_timer != NULL) { |
| 1106 | /* We use decr timer for PIT */ |
| 1107 | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
| 1108 | ppcemb_timer->fit_timer = |
| 1109 | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
| 1110 | ppcemb_timer->wdt_timer = |
| 1111 | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
| 1112 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1113 | |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1114 | return &ppc_emb_set_tb_clk; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1115 | } |
| 1116 | |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1117 | /*****************************************************************************/ |
| 1118 | /* Embedded PowerPC Device Control Registers */ |
| 1119 | typedef struct ppc_dcrn_t ppc_dcrn_t; |
| 1120 | struct ppc_dcrn_t { |
| 1121 | dcr_read_cb dcr_read; |
| 1122 | dcr_write_cb dcr_write; |
| 1123 | void *opaque; |
| 1124 | }; |
| 1125 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1126 | /* XXX: on 460, DCR addresses are 32 bits wide, |
| 1127 | * using DCRIPR to get the 22 upper bits of the DCR address |
| 1128 | */ |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1129 | #define DCRN_NB 1024 |
| 1130 | struct ppc_dcr_t { |
| 1131 | ppc_dcrn_t dcrn[DCRN_NB]; |
| 1132 | int (*read_error)(int dcrn); |
| 1133 | int (*write_error)(int dcrn); |
| 1134 | }; |
| 1135 | |
| 1136 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
| 1137 | { |
| 1138 | ppc_dcrn_t *dcr; |
| 1139 | |
| 1140 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1141 | goto error; |
| 1142 | dcr = &dcr_env->dcrn[dcrn]; |
| 1143 | if (dcr->dcr_read == NULL) |
| 1144 | goto error; |
| 1145 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
| 1146 | |
| 1147 | return 0; |
| 1148 | |
| 1149 | error: |
| 1150 | if (dcr_env->read_error != NULL) |
| 1151 | return (*dcr_env->read_error)(dcrn); |
| 1152 | |
| 1153 | return -1; |
| 1154 | } |
| 1155 | |
| 1156 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
| 1157 | { |
| 1158 | ppc_dcrn_t *dcr; |
| 1159 | |
| 1160 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1161 | goto error; |
| 1162 | dcr = &dcr_env->dcrn[dcrn]; |
| 1163 | if (dcr->dcr_write == NULL) |
| 1164 | goto error; |
| 1165 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
| 1166 | |
| 1167 | return 0; |
| 1168 | |
| 1169 | error: |
| 1170 | if (dcr_env->write_error != NULL) |
| 1171 | return (*dcr_env->write_error)(dcrn); |
| 1172 | |
| 1173 | return -1; |
| 1174 | } |
| 1175 | |
| 1176 | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
| 1177 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
| 1178 | { |
| 1179 | ppc_dcr_t *dcr_env; |
| 1180 | ppc_dcrn_t *dcr; |
| 1181 | |
| 1182 | dcr_env = env->dcr_env; |
| 1183 | if (dcr_env == NULL) |
| 1184 | return -1; |
| 1185 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1186 | return -1; |
| 1187 | dcr = &dcr_env->dcrn[dcrn]; |
| 1188 | if (dcr->opaque != NULL || |
| 1189 | dcr->dcr_read != NULL || |
| 1190 | dcr->dcr_write != NULL) |
| 1191 | return -1; |
| 1192 | dcr->opaque = opaque; |
| 1193 | dcr->dcr_read = dcr_read; |
| 1194 | dcr->dcr_write = dcr_write; |
| 1195 | |
| 1196 | return 0; |
| 1197 | } |
| 1198 | |
| 1199 | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
| 1200 | int (*write_error)(int dcrn)) |
| 1201 | { |
| 1202 | ppc_dcr_t *dcr_env; |
| 1203 | |
| 1204 | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t)); |
| 1205 | if (dcr_env == NULL) |
| 1206 | return -1; |
| 1207 | dcr_env->read_error = read_error; |
| 1208 | dcr_env->write_error = write_error; |
| 1209 | env->dcr_env = dcr_env; |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1214 | #if 0 |
| 1215 | /*****************************************************************************/ |
| 1216 | /* Handle system reset (for now, just stop emulation) */ |
| 1217 | void cpu_ppc_reset (CPUState *env) |
| 1218 | { |
| 1219 | printf("Reset asked... Stop emulation\n"); |
| 1220 | abort(); |
| 1221 | } |
| 1222 | #endif |
| 1223 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1224 | /*****************************************************************************/ |
| 1225 | /* Debug port */ |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1226 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1227 | { |
| 1228 | addr &= 0xF; |
| 1229 | switch (addr) { |
| 1230 | case 0: |
| 1231 | printf("%c", val); |
| 1232 | break; |
| 1233 | case 1: |
| 1234 | printf("\n"); |
| 1235 | fflush(stdout); |
| 1236 | break; |
| 1237 | case 2: |
| 1238 | printf("Set loglevel to %04x\n", val); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1239 | cpu_set_log(val | 0x100); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1240 | break; |
| 1241 | } |
| 1242 | } |
| 1243 | |
| 1244 | /*****************************************************************************/ |
| 1245 | /* NVRAM helpers */ |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1246 | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1247 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1248 | return (*nvram->read_fn)(nvram->opaque, addr);; |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1249 | } |
| 1250 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1251 | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1252 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1253 | (*nvram->write_fn)(nvram->opaque, addr, val); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1254 | } |
| 1255 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1256 | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1257 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1258 | nvram_write(nvram, addr, value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1259 | } |
| 1260 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1261 | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
| 1262 | { |
| 1263 | return nvram_read(nvram, addr); |
| 1264 | } |
| 1265 | |
| 1266 | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) |
| 1267 | { |
| 1268 | nvram_write(nvram, addr, value >> 8); |
| 1269 | nvram_write(nvram, addr + 1, value & 0xFF); |
| 1270 | } |
| 1271 | |
| 1272 | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1273 | { |
| 1274 | uint16_t tmp; |
| 1275 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1276 | tmp = nvram_read(nvram, addr) << 8; |
| 1277 | tmp |= nvram_read(nvram, addr + 1); |
| 1278 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1279 | return tmp; |
| 1280 | } |
| 1281 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1282 | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1283 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1284 | nvram_write(nvram, addr, value >> 24); |
| 1285 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| 1286 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
| 1287 | nvram_write(nvram, addr + 3, value & 0xFF); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1290 | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1291 | { |
| 1292 | uint32_t tmp; |
| 1293 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1294 | tmp = nvram_read(nvram, addr) << 24; |
| 1295 | tmp |= nvram_read(nvram, addr + 1) << 16; |
| 1296 | tmp |= nvram_read(nvram, addr + 2) << 8; |
| 1297 | tmp |= nvram_read(nvram, addr + 3); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1298 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1299 | return tmp; |
| 1300 | } |
| 1301 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1302 | void NVRAM_set_string (nvram_t *nvram, uint32_t addr, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1303 | const unsigned char *str, uint32_t max) |
| 1304 | { |
| 1305 | int i; |
| 1306 | |
| 1307 | for (i = 0; i < max && str[i] != '\0'; i++) { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1308 | nvram_write(nvram, addr + i, str[i]); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1309 | } |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1310 | nvram_write(nvram, addr + i, str[i]); |
| 1311 | nvram_write(nvram, addr + max - 1, '\0'); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1312 | } |
| 1313 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1314 | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1315 | { |
| 1316 | int i; |
| 1317 | |
| 1318 | memset(dst, 0, max); |
| 1319 | for (i = 0; i < max; i++) { |
| 1320 | dst[i] = NVRAM_get_byte(nvram, addr + i); |
| 1321 | if (dst[i] == '\0') |
| 1322 | break; |
| 1323 | } |
| 1324 | |
| 1325 | return i; |
| 1326 | } |
| 1327 | |
| 1328 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) |
| 1329 | { |
| 1330 | uint16_t tmp; |
| 1331 | uint16_t pd, pd1, pd2; |
| 1332 | |
| 1333 | tmp = prev >> 8; |
| 1334 | pd = prev ^ value; |
| 1335 | pd1 = pd & 0x000F; |
| 1336 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
| 1337 | tmp ^= (pd1 << 3) | (pd1 << 8); |
| 1338 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
| 1339 | |
| 1340 | return tmp; |
| 1341 | } |
| 1342 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1343 | uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1344 | { |
| 1345 | uint32_t i; |
| 1346 | uint16_t crc = 0xFFFF; |
| 1347 | int odd; |
| 1348 | |
| 1349 | odd = count & 1; |
| 1350 | count &= ~1; |
| 1351 | for (i = 0; i != count; i++) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1352 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1353 | } |
| 1354 | if (odd) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1355 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | return crc; |
| 1359 | } |
| 1360 | |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1361 | #define CMDLINE_ADDR 0x017ff000 |
| 1362 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1363 | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1364 | const unsigned char *arch, |
| 1365 | uint32_t RAM_size, int boot_device, |
| 1366 | uint32_t kernel_image, uint32_t kernel_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1367 | const char *cmdline, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1368 | uint32_t initrd_image, uint32_t initrd_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1369 | uint32_t NVRAM_image, |
| 1370 | int width, int height, int depth) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1371 | { |
| 1372 | uint16_t crc; |
| 1373 | |
| 1374 | /* Set parameters for Open Hack'Ware BIOS */ |
| 1375 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 1376 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
| 1377 | NVRAM_set_word(nvram, 0x14, NVRAM_size); |
| 1378 | NVRAM_set_string(nvram, 0x20, arch, 16); |
| 1379 | NVRAM_set_lword(nvram, 0x30, RAM_size); |
| 1380 | NVRAM_set_byte(nvram, 0x34, boot_device); |
| 1381 | NVRAM_set_lword(nvram, 0x38, kernel_image); |
| 1382 | NVRAM_set_lword(nvram, 0x3C, kernel_size); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1383 | if (cmdline) { |
| 1384 | /* XXX: put the cmdline in NVRAM too ? */ |
| 1385 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
| 1386 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
| 1387 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); |
| 1388 | } else { |
| 1389 | NVRAM_set_lword(nvram, 0x40, 0); |
| 1390 | NVRAM_set_lword(nvram, 0x44, 0); |
| 1391 | } |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1392 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
| 1393 | NVRAM_set_lword(nvram, 0x4C, initrd_size); |
| 1394 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1395 | |
| 1396 | NVRAM_set_word(nvram, 0x54, width); |
| 1397 | NVRAM_set_word(nvram, 0x56, height); |
| 1398 | NVRAM_set_word(nvram, 0x58, depth); |
| 1399 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1400 | NVRAM_set_word(nvram, 0xFC, crc); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1401 | |
| 1402 | return 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1403 | } |