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bellardb4608c02003-06-27 17:34:32 +00001/*
2 * gdb server stub
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard34751872005-07-02 14:31:34 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellardb4608c02003-06-27 17:34:32 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardb4608c02003-06-27 17:34:32 +000018 */
pbrook978efd62006-06-17 18:30:42 +000019#include "config.h"
pbrook56aebc82008-10-11 17:55:29 +000020#include "qemu-common.h"
bellard1fddef42005-04-17 19:16:13 +000021#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
pbrook978efd62006-06-17 18:30:42 +000028#include <fcntl.h>
bellard1fddef42005-04-17 19:16:13 +000029
30#include "qemu.h"
31#else
Paolo Bonzini83c90892012-12-17 18:19:49 +010032#include "monitor/monitor.h"
Paolo Bonzini927d4872012-12-17 18:20:05 +010033#include "char/char.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010034#include "sysemu/sysemu.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010035#include "exec/gdbstub.h"
bellard1fddef42005-04-17 19:16:13 +000036#endif
bellard67b915a2004-03-31 23:37:16 +000037
pbrook56aebc82008-10-11 17:55:29 +000038#define MAX_PACKET_LENGTH 4096
39
Blue Swirl2b41f102011-06-19 20:38:22 +000040#include "cpu.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010041#include "qemu/sockets.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010042#include "sysemu/kvm.h"
Richard Henderson6ee77b12012-08-23 10:44:45 -070043#include "qemu/bitops.h"
aurel32ca587a82008-12-18 22:44:13 +000044
Fabien Chouteau44520db2011-09-08 12:48:16 +020045#ifndef TARGET_CPU_MEMORY_RW_DEBUG
Andreas Färber9349b4f2012-03-14 01:38:32 +010046static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
Fabien Chouteau44520db2011-09-08 12:48:16 +020047 uint8_t *buf, int len, int is_write)
48{
49 return cpu_memory_rw_debug(env, addr, buf, len, is_write);
50}
51#else
52/* target_memory_rw_debug() defined in cpu.h */
53#endif
aurel32ca587a82008-12-18 22:44:13 +000054
55enum {
56 GDB_SIGNAL_0 = 0,
57 GDB_SIGNAL_INT = 2,
Jan Kiszka425189a2011-03-22 11:02:09 +010058 GDB_SIGNAL_QUIT = 3,
aurel32ca587a82008-12-18 22:44:13 +000059 GDB_SIGNAL_TRAP = 5,
Jan Kiszka425189a2011-03-22 11:02:09 +010060 GDB_SIGNAL_ABRT = 6,
61 GDB_SIGNAL_ALRM = 14,
62 GDB_SIGNAL_IO = 23,
63 GDB_SIGNAL_XCPU = 24,
aurel32ca587a82008-12-18 22:44:13 +000064 GDB_SIGNAL_UNKNOWN = 143
65};
66
67#ifdef CONFIG_USER_ONLY
68
69/* Map target signal numbers to GDB protocol signal numbers and vice
70 * versa. For user emulation's currently supported systems, we can
71 * assume most signals are defined.
72 */
73
74static int gdb_signal_table[] = {
75 0,
76 TARGET_SIGHUP,
77 TARGET_SIGINT,
78 TARGET_SIGQUIT,
79 TARGET_SIGILL,
80 TARGET_SIGTRAP,
81 TARGET_SIGABRT,
82 -1, /* SIGEMT */
83 TARGET_SIGFPE,
84 TARGET_SIGKILL,
85 TARGET_SIGBUS,
86 TARGET_SIGSEGV,
87 TARGET_SIGSYS,
88 TARGET_SIGPIPE,
89 TARGET_SIGALRM,
90 TARGET_SIGTERM,
91 TARGET_SIGURG,
92 TARGET_SIGSTOP,
93 TARGET_SIGTSTP,
94 TARGET_SIGCONT,
95 TARGET_SIGCHLD,
96 TARGET_SIGTTIN,
97 TARGET_SIGTTOU,
98 TARGET_SIGIO,
99 TARGET_SIGXCPU,
100 TARGET_SIGXFSZ,
101 TARGET_SIGVTALRM,
102 TARGET_SIGPROF,
103 TARGET_SIGWINCH,
104 -1, /* SIGLOST */
105 TARGET_SIGUSR1,
106 TARGET_SIGUSR2,
blueswir1c72d5bf2009-01-15 17:27:45 +0000107#ifdef TARGET_SIGPWR
aurel32ca587a82008-12-18 22:44:13 +0000108 TARGET_SIGPWR,
blueswir1c72d5bf2009-01-15 17:27:45 +0000109#else
110 -1,
111#endif
aurel32ca587a82008-12-18 22:44:13 +0000112 -1, /* SIGPOLL */
113 -1,
114 -1,
115 -1,
116 -1,
117 -1,
118 -1,
119 -1,
120 -1,
121 -1,
122 -1,
123 -1,
blueswir1c72d5bf2009-01-15 17:27:45 +0000124#ifdef __SIGRTMIN
aurel32ca587a82008-12-18 22:44:13 +0000125 __SIGRTMIN + 1,
126 __SIGRTMIN + 2,
127 __SIGRTMIN + 3,
128 __SIGRTMIN + 4,
129 __SIGRTMIN + 5,
130 __SIGRTMIN + 6,
131 __SIGRTMIN + 7,
132 __SIGRTMIN + 8,
133 __SIGRTMIN + 9,
134 __SIGRTMIN + 10,
135 __SIGRTMIN + 11,
136 __SIGRTMIN + 12,
137 __SIGRTMIN + 13,
138 __SIGRTMIN + 14,
139 __SIGRTMIN + 15,
140 __SIGRTMIN + 16,
141 __SIGRTMIN + 17,
142 __SIGRTMIN + 18,
143 __SIGRTMIN + 19,
144 __SIGRTMIN + 20,
145 __SIGRTMIN + 21,
146 __SIGRTMIN + 22,
147 __SIGRTMIN + 23,
148 __SIGRTMIN + 24,
149 __SIGRTMIN + 25,
150 __SIGRTMIN + 26,
151 __SIGRTMIN + 27,
152 __SIGRTMIN + 28,
153 __SIGRTMIN + 29,
154 __SIGRTMIN + 30,
155 __SIGRTMIN + 31,
156 -1, /* SIGCANCEL */
157 __SIGRTMIN,
158 __SIGRTMIN + 32,
159 __SIGRTMIN + 33,
160 __SIGRTMIN + 34,
161 __SIGRTMIN + 35,
162 __SIGRTMIN + 36,
163 __SIGRTMIN + 37,
164 __SIGRTMIN + 38,
165 __SIGRTMIN + 39,
166 __SIGRTMIN + 40,
167 __SIGRTMIN + 41,
168 __SIGRTMIN + 42,
169 __SIGRTMIN + 43,
170 __SIGRTMIN + 44,
171 __SIGRTMIN + 45,
172 __SIGRTMIN + 46,
173 __SIGRTMIN + 47,
174 __SIGRTMIN + 48,
175 __SIGRTMIN + 49,
176 __SIGRTMIN + 50,
177 __SIGRTMIN + 51,
178 __SIGRTMIN + 52,
179 __SIGRTMIN + 53,
180 __SIGRTMIN + 54,
181 __SIGRTMIN + 55,
182 __SIGRTMIN + 56,
183 __SIGRTMIN + 57,
184 __SIGRTMIN + 58,
185 __SIGRTMIN + 59,
186 __SIGRTMIN + 60,
187 __SIGRTMIN + 61,
188 __SIGRTMIN + 62,
189 __SIGRTMIN + 63,
190 __SIGRTMIN + 64,
191 __SIGRTMIN + 65,
192 __SIGRTMIN + 66,
193 __SIGRTMIN + 67,
194 __SIGRTMIN + 68,
195 __SIGRTMIN + 69,
196 __SIGRTMIN + 70,
197 __SIGRTMIN + 71,
198 __SIGRTMIN + 72,
199 __SIGRTMIN + 73,
200 __SIGRTMIN + 74,
201 __SIGRTMIN + 75,
202 __SIGRTMIN + 76,
203 __SIGRTMIN + 77,
204 __SIGRTMIN + 78,
205 __SIGRTMIN + 79,
206 __SIGRTMIN + 80,
207 __SIGRTMIN + 81,
208 __SIGRTMIN + 82,
209 __SIGRTMIN + 83,
210 __SIGRTMIN + 84,
211 __SIGRTMIN + 85,
212 __SIGRTMIN + 86,
213 __SIGRTMIN + 87,
214 __SIGRTMIN + 88,
215 __SIGRTMIN + 89,
216 __SIGRTMIN + 90,
217 __SIGRTMIN + 91,
218 __SIGRTMIN + 92,
219 __SIGRTMIN + 93,
220 __SIGRTMIN + 94,
221 __SIGRTMIN + 95,
222 -1, /* SIGINFO */
223 -1, /* UNKNOWN */
224 -1, /* DEFAULT */
225 -1,
226 -1,
227 -1,
228 -1,
229 -1,
230 -1
blueswir1c72d5bf2009-01-15 17:27:45 +0000231#endif
aurel32ca587a82008-12-18 22:44:13 +0000232};
bellard8f447cc2006-06-14 15:21:14 +0000233#else
aurel32ca587a82008-12-18 22:44:13 +0000234/* In system mode we only need SIGINT and SIGTRAP; other signals
235 are not yet supported. */
236
237enum {
238 TARGET_SIGINT = 2,
239 TARGET_SIGTRAP = 5
240};
241
242static int gdb_signal_table[] = {
243 -1,
244 -1,
245 TARGET_SIGINT,
246 -1,
247 -1,
248 TARGET_SIGTRAP
249};
bellard8f447cc2006-06-14 15:21:14 +0000250#endif
bellardb4608c02003-06-27 17:34:32 +0000251
aurel32ca587a82008-12-18 22:44:13 +0000252#ifdef CONFIG_USER_ONLY
253static int target_signal_to_gdb (int sig)
254{
255 int i;
256 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
257 if (gdb_signal_table[i] == sig)
258 return i;
259 return GDB_SIGNAL_UNKNOWN;
260}
261#endif
262
263static int gdb_signal_to_target (int sig)
264{
265 if (sig < ARRAY_SIZE (gdb_signal_table))
266 return gdb_signal_table[sig];
267 else
268 return -1;
269}
270
bellard4abe6152003-07-26 18:01:58 +0000271//#define DEBUG_GDB
bellardb4608c02003-06-27 17:34:32 +0000272
pbrook56aebc82008-10-11 17:55:29 +0000273typedef struct GDBRegisterState {
274 int base_reg;
275 int num_regs;
276 gdb_reg_cb get_reg;
277 gdb_reg_cb set_reg;
278 const char *xml;
279 struct GDBRegisterState *next;
280} GDBRegisterState;
281
bellard858693c2004-03-31 18:52:07 +0000282enum RSState {
aliguori36556b22009-03-28 18:05:53 +0000283 RS_INACTIVE,
bellard858693c2004-03-31 18:52:07 +0000284 RS_IDLE,
285 RS_GETLINE,
286 RS_CHKSUM1,
287 RS_CHKSUM2,
288};
bellard858693c2004-03-31 18:52:07 +0000289typedef struct GDBState {
Andreas Färber9349b4f2012-03-14 01:38:32 +0100290 CPUArchState *c_cpu; /* current CPU for step/continue ops */
291 CPUArchState *g_cpu; /* current CPU for other ops */
292 CPUArchState *query_cpu; /* for q{f|s}ThreadInfo */
bellard41625032005-04-24 10:07:11 +0000293 enum RSState state; /* parsing state */
pbrook56aebc82008-10-11 17:55:29 +0000294 char line_buf[MAX_PACKET_LENGTH];
bellard858693c2004-03-31 18:52:07 +0000295 int line_buf_index;
296 int line_csum;
pbrook56aebc82008-10-11 17:55:29 +0000297 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
pbrook4046d912007-01-28 01:53:16 +0000298 int last_packet_len;
edgar_igl1f487ee2008-05-17 22:20:53 +0000299 int signal;
bellard41625032005-04-24 10:07:11 +0000300#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +0000301 int fd;
bellard41625032005-04-24 10:07:11 +0000302 int running_state;
pbrook4046d912007-01-28 01:53:16 +0000303#else
304 CharDriverState *chr;
aliguori8a34a0f2009-03-05 23:01:55 +0000305 CharDriverState *mon_chr;
bellard41625032005-04-24 10:07:11 +0000306#endif
Meador Ingecdb432b2012-03-15 17:49:45 +0000307 char syscall_buf[256];
308 gdb_syscall_complete_cb current_syscall_cb;
bellard858693c2004-03-31 18:52:07 +0000309} GDBState;
bellardb4608c02003-06-27 17:34:32 +0000310
edgar_igl60897d32008-05-09 08:25:14 +0000311/* By default use no IRQs and no timers while single stepping so as to
312 * make single stepping like an ICE HW step.
313 */
314static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
315
aliguori880a7572008-11-18 20:30:24 +0000316static GDBState *gdbserver_state;
317
pbrook56aebc82008-10-11 17:55:29 +0000318/* This is an ugly hack to cope with both new and old gdb.
319 If gdb sends qXfer:features:read then assume we're talking to a newish
320 gdb that understands target descriptions. */
321static int gdb_has_xml;
322
bellard1fddef42005-04-17 19:16:13 +0000323#ifdef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +0000324/* XXX: This is not thread safe. Do we care? */
325static int gdbserver_fd = -1;
326
bellard858693c2004-03-31 18:52:07 +0000327static int get_char(GDBState *s)
bellardb4608c02003-06-27 17:34:32 +0000328{
329 uint8_t ch;
330 int ret;
331
332 for(;;) {
Blue Swirl00aa0042011-07-23 20:04:29 +0000333 ret = qemu_recv(s->fd, &ch, 1, 0);
bellardb4608c02003-06-27 17:34:32 +0000334 if (ret < 0) {
edgar_igl1f487ee2008-05-17 22:20:53 +0000335 if (errno == ECONNRESET)
336 s->fd = -1;
bellardb4608c02003-06-27 17:34:32 +0000337 if (errno != EINTR && errno != EAGAIN)
338 return -1;
339 } else if (ret == 0) {
edgar_igl1f487ee2008-05-17 22:20:53 +0000340 close(s->fd);
341 s->fd = -1;
bellardb4608c02003-06-27 17:34:32 +0000342 return -1;
343 } else {
344 break;
345 }
346 }
347 return ch;
348}
pbrook4046d912007-01-28 01:53:16 +0000349#endif
bellardb4608c02003-06-27 17:34:32 +0000350
blueswir1654efcf2009-04-18 07:29:59 +0000351static enum {
pbrooka2d1eba2007-01-28 03:10:55 +0000352 GDB_SYS_UNKNOWN,
353 GDB_SYS_ENABLED,
354 GDB_SYS_DISABLED,
355} gdb_syscall_mode;
356
357/* If gdb is connected when the first semihosting syscall occurs then use
358 remote gdb syscalls. Otherwise use native file IO. */
359int use_gdb_syscalls(void)
360{
361 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
aliguori880a7572008-11-18 20:30:24 +0000362 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
363 : GDB_SYS_DISABLED);
pbrooka2d1eba2007-01-28 03:10:55 +0000364 }
365 return gdb_syscall_mode == GDB_SYS_ENABLED;
366}
367
edgar_iglba70a622008-03-14 06:10:42 +0000368/* Resume execution. */
369static inline void gdb_continue(GDBState *s)
370{
371#ifdef CONFIG_USER_ONLY
372 s->running_state = 1;
373#else
374 vm_start();
375#endif
376}
377
bellard858693c2004-03-31 18:52:07 +0000378static void put_buffer(GDBState *s, const uint8_t *buf, int len)
bellardb4608c02003-06-27 17:34:32 +0000379{
pbrook4046d912007-01-28 01:53:16 +0000380#ifdef CONFIG_USER_ONLY
bellardb4608c02003-06-27 17:34:32 +0000381 int ret;
382
383 while (len > 0) {
bellard8f447cc2006-06-14 15:21:14 +0000384 ret = send(s->fd, buf, len, 0);
bellardb4608c02003-06-27 17:34:32 +0000385 if (ret < 0) {
386 if (errno != EINTR && errno != EAGAIN)
387 return;
388 } else {
389 buf += ret;
390 len -= ret;
391 }
392 }
pbrook4046d912007-01-28 01:53:16 +0000393#else
Anthony Liguori2cc6e0a2011-08-15 11:17:28 -0500394 qemu_chr_fe_write(s->chr, buf, len);
pbrook4046d912007-01-28 01:53:16 +0000395#endif
bellardb4608c02003-06-27 17:34:32 +0000396}
397
398static inline int fromhex(int v)
399{
400 if (v >= '0' && v <= '9')
401 return v - '0';
402 else if (v >= 'A' && v <= 'F')
403 return v - 'A' + 10;
404 else if (v >= 'a' && v <= 'f')
405 return v - 'a' + 10;
406 else
407 return 0;
408}
409
410static inline int tohex(int v)
411{
412 if (v < 10)
413 return v + '0';
414 else
415 return v - 10 + 'a';
416}
417
418static void memtohex(char *buf, const uint8_t *mem, int len)
419{
420 int i, c;
421 char *q;
422 q = buf;
423 for(i = 0; i < len; i++) {
424 c = mem[i];
425 *q++ = tohex(c >> 4);
426 *q++ = tohex(c & 0xf);
427 }
428 *q = '\0';
429}
430
431static void hextomem(uint8_t *mem, const char *buf, int len)
432{
433 int i;
434
435 for(i = 0; i < len; i++) {
436 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
437 buf += 2;
438 }
439}
440
bellardb4608c02003-06-27 17:34:32 +0000441/* return -1 if error, 0 if OK */
pbrook56aebc82008-10-11 17:55:29 +0000442static int put_packet_binary(GDBState *s, const char *buf, int len)
bellardb4608c02003-06-27 17:34:32 +0000443{
pbrook56aebc82008-10-11 17:55:29 +0000444 int csum, i;
ths60fe76f2007-12-16 03:02:09 +0000445 uint8_t *p;
bellardb4608c02003-06-27 17:34:32 +0000446
bellardb4608c02003-06-27 17:34:32 +0000447 for(;;) {
pbrook4046d912007-01-28 01:53:16 +0000448 p = s->last_packet;
449 *(p++) = '$';
pbrook4046d912007-01-28 01:53:16 +0000450 memcpy(p, buf, len);
451 p += len;
bellardb4608c02003-06-27 17:34:32 +0000452 csum = 0;
453 for(i = 0; i < len; i++) {
454 csum += buf[i];
455 }
pbrook4046d912007-01-28 01:53:16 +0000456 *(p++) = '#';
457 *(p++) = tohex((csum >> 4) & 0xf);
458 *(p++) = tohex((csum) & 0xf);
bellardb4608c02003-06-27 17:34:32 +0000459
pbrook4046d912007-01-28 01:53:16 +0000460 s->last_packet_len = p - s->last_packet;
thsffe8ab82007-12-16 03:16:05 +0000461 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
bellardb4608c02003-06-27 17:34:32 +0000462
pbrook4046d912007-01-28 01:53:16 +0000463#ifdef CONFIG_USER_ONLY
464 i = get_char(s);
465 if (i < 0)
bellardb4608c02003-06-27 17:34:32 +0000466 return -1;
pbrook4046d912007-01-28 01:53:16 +0000467 if (i == '+')
bellardb4608c02003-06-27 17:34:32 +0000468 break;
pbrook4046d912007-01-28 01:53:16 +0000469#else
470 break;
471#endif
bellardb4608c02003-06-27 17:34:32 +0000472 }
473 return 0;
474}
475
pbrook56aebc82008-10-11 17:55:29 +0000476/* return -1 if error, 0 if OK */
477static int put_packet(GDBState *s, const char *buf)
478{
479#ifdef DEBUG_GDB
480 printf("reply='%s'\n", buf);
481#endif
482
483 return put_packet_binary(s, buf, strlen(buf));
484}
485
486/* The GDB remote protocol transfers values in target byte order. This means
487 we can use the raw memory access routines to access the value buffer.
488 Conveniently, these also handle the case where the buffer is mis-aligned.
489 */
490#define GET_REG8(val) do { \
491 stb_p(mem_buf, val); \
492 return 1; \
493 } while(0)
494#define GET_REG16(val) do { \
495 stw_p(mem_buf, val); \
496 return 2; \
497 } while(0)
498#define GET_REG32(val) do { \
499 stl_p(mem_buf, val); \
500 return 4; \
501 } while(0)
502#define GET_REG64(val) do { \
503 stq_p(mem_buf, val); \
504 return 8; \
505 } while(0)
506
507#if TARGET_LONG_BITS == 64
508#define GET_REGL(val) GET_REG64(val)
509#define ldtul_p(addr) ldq_p(addr)
510#else
511#define GET_REGL(val) GET_REG32(val)
512#define ldtul_p(addr) ldl_p(addr)
513#endif
514
edgar_iglfde3fd62008-05-09 08:50:01 +0000515#if defined(TARGET_I386)
balrog5ad265e2007-10-31 00:21:35 +0000516
517#ifdef TARGET_X86_64
pbrook56aebc82008-10-11 17:55:29 +0000518static const int gpr_map[16] = {
bellard79808572008-05-09 14:40:22 +0000519 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
pbrook56aebc82008-10-11 17:55:29 +0000520 8, 9, 10, 11, 12, 13, 14, 15
bellard79808572008-05-09 14:40:22 +0000521};
bellard79808572008-05-09 14:40:22 +0000522#else
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200523#define gpr_map gpr_map32
bellard79808572008-05-09 14:40:22 +0000524#endif
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200525static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
pbrook56aebc82008-10-11 17:55:29 +0000526
527#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
528
Jan Kiszkab1631e72009-06-27 09:53:51 +0200529#define IDX_IP_REG CPU_NB_REGS
530#define IDX_FLAGS_REG (IDX_IP_REG + 1)
531#define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
532#define IDX_FP_REGS (IDX_SEG_REGS + 6)
533#define IDX_XMM_REGS (IDX_FP_REGS + 16)
534#define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
535
Andreas Färberf3840912012-02-20 06:44:56 +0100536static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
pbrook56aebc82008-10-11 17:55:29 +0000537{
538 if (n < CPU_NB_REGS) {
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200539 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
540 GET_REG64(env->regs[gpr_map[n]]);
541 } else if (n < CPU_NB_REGS32) {
542 GET_REG32(env->regs[gpr_map32[n]]);
543 }
Jan Kiszkab1631e72009-06-27 09:53:51 +0200544 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
pbrook56aebc82008-10-11 17:55:29 +0000545#ifdef USE_X86LDOUBLE
Jan Kiszkab1631e72009-06-27 09:53:51 +0200546 /* FIXME: byteswap float values - after fixing fpregs layout. */
547 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
pbrook56aebc82008-10-11 17:55:29 +0000548#else
549 memset(mem_buf, 0, 10);
550#endif
551 return 10;
Jan Kiszkab1631e72009-06-27 09:53:51 +0200552 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
553 n -= IDX_XMM_REGS;
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200554 if (n < CPU_NB_REGS32 ||
555 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
556 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
557 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
558 return 16;
559 }
pbrook56aebc82008-10-11 17:55:29 +0000560 } else {
pbrook56aebc82008-10-11 17:55:29 +0000561 switch (n) {
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200562 case IDX_IP_REG:
563 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
564 GET_REG64(env->eip);
565 } else {
566 GET_REG32(env->eip);
567 }
Jan Kiszkab1631e72009-06-27 09:53:51 +0200568 case IDX_FLAGS_REG: GET_REG32(env->eflags);
569
570 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
571 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
572 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
573 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
574 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
575 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
576
577 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
578 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
579 (env->fpstt & 0x7) << 11);
580 case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
581 case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
582 case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
583 case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
584 case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
585 case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
586
587 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
pbrook56aebc82008-10-11 17:55:29 +0000588 }
bellard79808572008-05-09 14:40:22 +0000589 }
pbrook56aebc82008-10-11 17:55:29 +0000590 return 0;
bellard79808572008-05-09 14:40:22 +0000591}
592
Andreas Färberf3840912012-02-20 06:44:56 +0100593static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
Jan Kiszka84273172009-06-27 09:53:51 +0200594{
595 uint16_t selector = ldl_p(mem_buf);
596
597 if (selector != env->segs[sreg].selector) {
598#if defined(CONFIG_USER_ONLY)
599 cpu_x86_load_seg(env, sreg, selector);
600#else
601 unsigned int limit, flags;
602 target_ulong base;
603
604 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
605 base = selector << 4;
606 limit = 0xffff;
607 flags = 0;
608 } else {
609 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
610 return 4;
611 }
612 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
613#endif
614 }
615 return 4;
616}
617
Andreas Färberf3840912012-02-20 06:44:56 +0100618static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
bellard79808572008-05-09 14:40:22 +0000619{
pbrook56aebc82008-10-11 17:55:29 +0000620 uint32_t tmp;
621
Jan Kiszkab1631e72009-06-27 09:53:51 +0200622 if (n < CPU_NB_REGS) {
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200623 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
624 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
625 return sizeof(target_ulong);
626 } else if (n < CPU_NB_REGS32) {
627 n = gpr_map32[n];
628 env->regs[n] &= ~0xffffffffUL;
629 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
630 return 4;
631 }
Jan Kiszkab1631e72009-06-27 09:53:51 +0200632 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
pbrook56aebc82008-10-11 17:55:29 +0000633#ifdef USE_X86LDOUBLE
Jan Kiszkab1631e72009-06-27 09:53:51 +0200634 /* FIXME: byteswap float values - after fixing fpregs layout. */
635 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
pbrook56aebc82008-10-11 17:55:29 +0000636#endif
637 return 10;
Jan Kiszkab1631e72009-06-27 09:53:51 +0200638 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
639 n -= IDX_XMM_REGS;
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200640 if (n < CPU_NB_REGS32 ||
641 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
642 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
643 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
644 return 16;
645 }
pbrook56aebc82008-10-11 17:55:29 +0000646 } else {
Jan Kiszkab1631e72009-06-27 09:53:51 +0200647 switch (n) {
648 case IDX_IP_REG:
Jan Kiszka5f30fa12009-09-17 18:14:13 +0200649 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
650 env->eip = ldq_p(mem_buf);
651 return 8;
652 } else {
653 env->eip &= ~0xffffffffUL;
654 env->eip |= (uint32_t)ldl_p(mem_buf);
655 return 4;
656 }
Jan Kiszkab1631e72009-06-27 09:53:51 +0200657 case IDX_FLAGS_REG:
658 env->eflags = ldl_p(mem_buf);
659 return 4;
660
Jan Kiszka84273172009-06-27 09:53:51 +0200661 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
662 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
663 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
664 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
665 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
666 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
Jan Kiszkab1631e72009-06-27 09:53:51 +0200667
668 case IDX_FP_REGS + 8:
669 env->fpuc = ldl_p(mem_buf);
670 return 4;
671 case IDX_FP_REGS + 9:
672 tmp = ldl_p(mem_buf);
673 env->fpstt = (tmp >> 11) & 7;
674 env->fpus = tmp & ~0x3800;
675 return 4;
676 case IDX_FP_REGS + 10: /* ftag */ return 4;
677 case IDX_FP_REGS + 11: /* fiseg */ return 4;
678 case IDX_FP_REGS + 12: /* fioff */ return 4;
679 case IDX_FP_REGS + 13: /* foseg */ return 4;
680 case IDX_FP_REGS + 14: /* fooff */ return 4;
681 case IDX_FP_REGS + 15: /* fop */ return 4;
682
683 case IDX_MXCSR_REG:
684 env->mxcsr = ldl_p(mem_buf);
685 return 4;
bellard79808572008-05-09 14:40:22 +0000686 }
bellard79808572008-05-09 14:40:22 +0000687 }
pbrook56aebc82008-10-11 17:55:29 +0000688 /* Unrecognised register. */
689 return 0;
bellard6da41ea2004-01-04 15:48:38 +0000690}
691
bellard9e62fd72004-01-05 22:49:06 +0000692#elif defined (TARGET_PPC)
pbrook56aebc82008-10-11 17:55:29 +0000693
aurel32e571cb42009-01-24 15:07:42 +0000694/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
695 expects whatever the target description contains. Due to a
696 historical mishap the FP registers appear in between core integer
697 regs and PC, MSR, CR, and so forth. We hack round this by giving the
698 FP regs zero size when talking to a newer gdb. */
pbrook56aebc82008-10-11 17:55:29 +0000699#define NUM_CORE_REGS 71
aurel32e571cb42009-01-24 15:07:42 +0000700#if defined (TARGET_PPC64)
701#define GDB_CORE_XML "power64-core.xml"
702#else
703#define GDB_CORE_XML "power-core.xml"
704#endif
pbrook56aebc82008-10-11 17:55:29 +0000705
Andreas Färberf3840912012-02-20 06:44:56 +0100706static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
bellard9e62fd72004-01-05 22:49:06 +0000707{
pbrook56aebc82008-10-11 17:55:29 +0000708 if (n < 32) {
709 /* gprs */
710 GET_REGL(env->gpr[n]);
711 } else if (n < 64) {
712 /* fprs */
aurel32e571cb42009-01-24 15:07:42 +0000713 if (gdb_has_xml)
714 return 0;
aurel328d4acf92008-11-30 16:23:18 +0000715 stfq_p(mem_buf, env->fpr[n-32]);
pbrook56aebc82008-10-11 17:55:29 +0000716 return 8;
717 } else {
718 switch (n) {
719 case 64: GET_REGL(env->nip);
720 case 65: GET_REGL(env->msr);
721 case 66:
722 {
723 uint32_t cr = 0;
724 int i;
725 for (i = 0; i < 8; i++)
726 cr |= env->crf[i] << (32 - ((i + 1) * 4));
727 GET_REG32(cr);
728 }
729 case 67: GET_REGL(env->lr);
730 case 68: GET_REGL(env->ctr);
aurel323d7b4172008-10-21 11:28:46 +0000731 case 69: GET_REGL(env->xer);
aurel32e571cb42009-01-24 15:07:42 +0000732 case 70:
733 {
734 if (gdb_has_xml)
735 return 0;
Fabien Chouteau5a576fb2011-09-01 04:56:00 +0000736 GET_REG32(env->fpscr);
aurel32e571cb42009-01-24 15:07:42 +0000737 }
pbrook56aebc82008-10-11 17:55:29 +0000738 }
bellard9e62fd72004-01-05 22:49:06 +0000739 }
pbrook56aebc82008-10-11 17:55:29 +0000740 return 0;
bellard9e62fd72004-01-05 22:49:06 +0000741}
742
Andreas Färberf3840912012-02-20 06:44:56 +0100743static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
bellard9e62fd72004-01-05 22:49:06 +0000744{
pbrook56aebc82008-10-11 17:55:29 +0000745 if (n < 32) {
746 /* gprs */
747 env->gpr[n] = ldtul_p(mem_buf);
748 return sizeof(target_ulong);
749 } else if (n < 64) {
750 /* fprs */
aurel32e571cb42009-01-24 15:07:42 +0000751 if (gdb_has_xml)
752 return 0;
aurel328d4acf92008-11-30 16:23:18 +0000753 env->fpr[n-32] = ldfq_p(mem_buf);
pbrook56aebc82008-10-11 17:55:29 +0000754 return 8;
755 } else {
756 switch (n) {
757 case 64:
758 env->nip = ldtul_p(mem_buf);
759 return sizeof(target_ulong);
760 case 65:
761 ppc_store_msr(env, ldtul_p(mem_buf));
762 return sizeof(target_ulong);
763 case 66:
764 {
765 uint32_t cr = ldl_p(mem_buf);
766 int i;
767 for (i = 0; i < 8; i++)
768 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
769 return 4;
770 }
771 case 67:
772 env->lr = ldtul_p(mem_buf);
773 return sizeof(target_ulong);
774 case 68:
775 env->ctr = ldtul_p(mem_buf);
776 return sizeof(target_ulong);
777 case 69:
aurel323d7b4172008-10-21 11:28:46 +0000778 env->xer = ldtul_p(mem_buf);
779 return sizeof(target_ulong);
pbrook56aebc82008-10-11 17:55:29 +0000780 case 70:
781 /* fpscr */
aurel32e571cb42009-01-24 15:07:42 +0000782 if (gdb_has_xml)
783 return 0;
pbrook56aebc82008-10-11 17:55:29 +0000784 return 4;
785 }
bellard9e62fd72004-01-05 22:49:06 +0000786 }
pbrook56aebc82008-10-11 17:55:29 +0000787 return 0;
bellarde95c8d52004-09-30 22:22:08 +0000788}
pbrook56aebc82008-10-11 17:55:29 +0000789
bellarde95c8d52004-09-30 22:22:08 +0000790#elif defined (TARGET_SPARC)
bellarde95c8d52004-09-30 22:22:08 +0000791
pbrook56aebc82008-10-11 17:55:29 +0000792#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
793#define NUM_CORE_REGS 86
794#else
blueswir15a377912009-01-13 16:28:01 +0000795#define NUM_CORE_REGS 72
pbrook56aebc82008-10-11 17:55:29 +0000796#endif
797
798#ifdef TARGET_ABI32
799#define GET_REGA(val) GET_REG32(val)
800#else
801#define GET_REGA(val) GET_REGL(val)
802#endif
803
Andreas Färberf3840912012-02-20 06:44:56 +0100804static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
pbrook56aebc82008-10-11 17:55:29 +0000805{
806 if (n < 8) {
807 /* g0..g7 */
808 GET_REGA(env->gregs[n]);
bellarde95c8d52004-09-30 22:22:08 +0000809 }
pbrook56aebc82008-10-11 17:55:29 +0000810 if (n < 32) {
811 /* register window */
812 GET_REGA(env->regwptr[n - 8]);
bellarde95c8d52004-09-30 22:22:08 +0000813 }
pbrook56aebc82008-10-11 17:55:29 +0000814#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
815 if (n < 64) {
816 /* fprs */
Richard Henderson30038fd2011-10-17 10:42:49 -0700817 if (n & 1) {
818 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
819 } else {
820 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
821 }
bellarde95c8d52004-09-30 22:22:08 +0000822 }
823 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
pbrook56aebc82008-10-11 17:55:29 +0000824 switch (n) {
825 case 64: GET_REGA(env->y);
Blue Swirl5a834bb2010-05-09 20:19:04 +0000826 case 65: GET_REGA(cpu_get_psr(env));
pbrook56aebc82008-10-11 17:55:29 +0000827 case 66: GET_REGA(env->wim);
828 case 67: GET_REGA(env->tbr);
829 case 68: GET_REGA(env->pc);
830 case 69: GET_REGA(env->npc);
831 case 70: GET_REGA(env->fsr);
832 case 71: GET_REGA(0); /* csr */
blueswir15a377912009-01-13 16:28:01 +0000833 default: GET_REGA(0);
bellard34751872005-07-02 14:31:34 +0000834 }
bellard34751872005-07-02 14:31:34 +0000835#else
pbrook56aebc82008-10-11 17:55:29 +0000836 if (n < 64) {
837 /* f0-f31 */
Richard Henderson30038fd2011-10-17 10:42:49 -0700838 if (n & 1) {
839 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
840 } else {
841 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
842 }
bellard34751872005-07-02 14:31:34 +0000843 }
pbrook56aebc82008-10-11 17:55:29 +0000844 if (n < 80) {
845 /* f32-f62 (double width, even numbers only) */
Richard Henderson30038fd2011-10-17 10:42:49 -0700846 GET_REG64(env->fpr[(n - 32) / 2].ll);
pbrook56aebc82008-10-11 17:55:29 +0000847 }
848 switch (n) {
849 case 80: GET_REGL(env->pc);
850 case 81: GET_REGL(env->npc);
Blue Swirl5a834bb2010-05-09 20:19:04 +0000851 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
852 ((env->asi & 0xff) << 24) |
853 ((env->pstate & 0xfff) << 8) |
854 cpu_get_cwp64(env));
pbrook56aebc82008-10-11 17:55:29 +0000855 case 83: GET_REGL(env->fsr);
856 case 84: GET_REGL(env->fprs);
857 case 85: GET_REGL(env->y);
858 }
bellard34751872005-07-02 14:31:34 +0000859#endif
pbrook56aebc82008-10-11 17:55:29 +0000860 return 0;
bellarde95c8d52004-09-30 22:22:08 +0000861}
862
Andreas Färberf3840912012-02-20 06:44:56 +0100863static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
bellarde95c8d52004-09-30 22:22:08 +0000864{
pbrook56aebc82008-10-11 17:55:29 +0000865#if defined(TARGET_ABI32)
866 abi_ulong tmp;
867
868 tmp = ldl_p(mem_buf);
blueswir196d19122008-06-07 08:03:05 +0000869#else
pbrook56aebc82008-10-11 17:55:29 +0000870 target_ulong tmp;
871
872 tmp = ldtul_p(mem_buf);
blueswir196d19122008-06-07 08:03:05 +0000873#endif
bellarde95c8d52004-09-30 22:22:08 +0000874
pbrook56aebc82008-10-11 17:55:29 +0000875 if (n < 8) {
876 /* g0..g7 */
877 env->gregs[n] = tmp;
878 } else if (n < 32) {
879 /* register window */
880 env->regwptr[n - 8] = tmp;
bellarde95c8d52004-09-30 22:22:08 +0000881 }
pbrook56aebc82008-10-11 17:55:29 +0000882#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
883 else if (n < 64) {
884 /* fprs */
Richard Henderson30038fd2011-10-17 10:42:49 -0700885 /* f0-f31 */
886 if (n & 1) {
887 env->fpr[(n - 32) / 2].l.lower = tmp;
888 } else {
889 env->fpr[(n - 32) / 2].l.upper = tmp;
890 }
pbrook56aebc82008-10-11 17:55:29 +0000891 } else {
892 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
893 switch (n) {
894 case 64: env->y = tmp; break;
Blue Swirl5a834bb2010-05-09 20:19:04 +0000895 case 65: cpu_put_psr(env, tmp); break;
pbrook56aebc82008-10-11 17:55:29 +0000896 case 66: env->wim = tmp; break;
897 case 67: env->tbr = tmp; break;
898 case 68: env->pc = tmp; break;
899 case 69: env->npc = tmp; break;
900 case 70: env->fsr = tmp; break;
901 default: return 0;
902 }
bellarde95c8d52004-09-30 22:22:08 +0000903 }
pbrook56aebc82008-10-11 17:55:29 +0000904 return 4;
bellard34751872005-07-02 14:31:34 +0000905#else
pbrook56aebc82008-10-11 17:55:29 +0000906 else if (n < 64) {
907 /* f0-f31 */
Richard Henderson30038fd2011-10-17 10:42:49 -0700908 tmp = ldl_p(mem_buf);
909 if (n & 1) {
910 env->fpr[(n - 32) / 2].l.lower = tmp;
911 } else {
912 env->fpr[(n - 32) / 2].l.upper = tmp;
913 }
pbrook56aebc82008-10-11 17:55:29 +0000914 return 4;
915 } else if (n < 80) {
916 /* f32-f62 (double width, even numbers only) */
Richard Henderson30038fd2011-10-17 10:42:49 -0700917 env->fpr[(n - 32) / 2].ll = tmp;
pbrook56aebc82008-10-11 17:55:29 +0000918 } else {
919 switch (n) {
920 case 80: env->pc = tmp; break;
921 case 81: env->npc = tmp; break;
922 case 82:
Blue Swirl5a834bb2010-05-09 20:19:04 +0000923 cpu_put_ccr(env, tmp >> 32);
pbrook56aebc82008-10-11 17:55:29 +0000924 env->asi = (tmp >> 24) & 0xff;
925 env->pstate = (tmp >> 8) & 0xfff;
Blue Swirl5a834bb2010-05-09 20:19:04 +0000926 cpu_put_cwp64(env, tmp & 0xff);
pbrook56aebc82008-10-11 17:55:29 +0000927 break;
928 case 83: env->fsr = tmp; break;
929 case 84: env->fprs = tmp; break;
930 case 85: env->y = tmp; break;
931 default: return 0;
932 }
bellard34751872005-07-02 14:31:34 +0000933 }
pbrook56aebc82008-10-11 17:55:29 +0000934 return 8;
bellard34751872005-07-02 14:31:34 +0000935#endif
bellard9e62fd72004-01-05 22:49:06 +0000936}
bellard1fddef42005-04-17 19:16:13 +0000937#elif defined (TARGET_ARM)
pbrook56aebc82008-10-11 17:55:29 +0000938
939/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
940 whatever the target description contains. Due to a historical mishap
941 the FPA registers appear in between core integer regs and the CPSR.
942 We hack round this by giving the FPA regs zero size when talking to a
943 newer gdb. */
944#define NUM_CORE_REGS 26
945#define GDB_CORE_XML "arm-core.xml"
946
Andreas Färberf3840912012-02-20 06:44:56 +0100947static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
bellard1fddef42005-04-17 19:16:13 +0000948{
pbrook56aebc82008-10-11 17:55:29 +0000949 if (n < 16) {
950 /* Core integer register. */
951 GET_REG32(env->regs[n]);
952 }
953 if (n < 24) {
954 /* FPA registers. */
955 if (gdb_has_xml)
956 return 0;
957 memset(mem_buf, 0, 12);
958 return 12;
959 }
960 switch (n) {
961 case 24:
962 /* FPA status register. */
963 if (gdb_has_xml)
964 return 0;
965 GET_REG32(0);
966 case 25:
967 /* CPSR */
968 GET_REG32(cpsr_read(env));
969 }
970 /* Unknown register. */
971 return 0;
bellard1fddef42005-04-17 19:16:13 +0000972}
973
Andreas Färberf3840912012-02-20 06:44:56 +0100974static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
bellard1fddef42005-04-17 19:16:13 +0000975{
pbrook56aebc82008-10-11 17:55:29 +0000976 uint32_t tmp;
bellard1fddef42005-04-17 19:16:13 +0000977
pbrook56aebc82008-10-11 17:55:29 +0000978 tmp = ldl_p(mem_buf);
979
980 /* Mask out low bit of PC to workaround gdb bugs. This will probably
981 cause problems if we ever implement the Jazelle DBX extensions. */
982 if (n == 15)
983 tmp &= ~1;
984
985 if (n < 16) {
986 /* Core integer register. */
987 env->regs[n] = tmp;
988 return 4;
989 }
990 if (n < 24) { /* 16-23 */
991 /* FPA registers (ignored). */
992 if (gdb_has_xml)
993 return 0;
994 return 12;
995 }
996 switch (n) {
997 case 24:
998 /* FPA status register (ignored). */
999 if (gdb_has_xml)
1000 return 0;
1001 return 4;
1002 case 25:
1003 /* CPSR */
1004 cpsr_write (env, tmp, 0xffffffff);
1005 return 4;
1006 }
1007 /* Unknown register. */
1008 return 0;
bellard1fddef42005-04-17 19:16:13 +00001009}
pbrook56aebc82008-10-11 17:55:29 +00001010
pbrooke6e59062006-10-22 00:18:54 +00001011#elif defined (TARGET_M68K)
pbrook56aebc82008-10-11 17:55:29 +00001012
1013#define NUM_CORE_REGS 18
1014
1015#define GDB_CORE_XML "cf-core.xml"
1016
Andreas Färberf3840912012-02-20 06:44:56 +01001017static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
pbrooke6e59062006-10-22 00:18:54 +00001018{
pbrook56aebc82008-10-11 17:55:29 +00001019 if (n < 8) {
1020 /* D0-D7 */
1021 GET_REG32(env->dregs[n]);
1022 } else if (n < 16) {
1023 /* A0-A7 */
1024 GET_REG32(env->aregs[n - 8]);
1025 } else {
1026 switch (n) {
1027 case 16: GET_REG32(env->sr);
1028 case 17: GET_REG32(env->pc);
1029 }
pbrooke6e59062006-10-22 00:18:54 +00001030 }
pbrook56aebc82008-10-11 17:55:29 +00001031 /* FP registers not included here because they vary between
1032 ColdFire and m68k. Use XML bits for these. */
1033 return 0;
pbrooke6e59062006-10-22 00:18:54 +00001034}
1035
Andreas Färberf3840912012-02-20 06:44:56 +01001036static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
pbrooke6e59062006-10-22 00:18:54 +00001037{
pbrook56aebc82008-10-11 17:55:29 +00001038 uint32_t tmp;
pbrooke6e59062006-10-22 00:18:54 +00001039
pbrook56aebc82008-10-11 17:55:29 +00001040 tmp = ldl_p(mem_buf);
1041
1042 if (n < 8) {
1043 /* D0-D7 */
1044 env->dregs[n] = tmp;
Kazu Hiratab3d6b952010-01-14 09:08:00 -08001045 } else if (n < 16) {
pbrook56aebc82008-10-11 17:55:29 +00001046 /* A0-A7 */
1047 env->aregs[n - 8] = tmp;
1048 } else {
1049 switch (n) {
1050 case 16: env->sr = tmp; break;
1051 case 17: env->pc = tmp; break;
1052 default: return 0;
1053 }
pbrooke6e59062006-10-22 00:18:54 +00001054 }
pbrook56aebc82008-10-11 17:55:29 +00001055 return 4;
pbrooke6e59062006-10-22 00:18:54 +00001056}
bellard6f970bd2005-12-05 19:55:19 +00001057#elif defined (TARGET_MIPS)
pbrook56aebc82008-10-11 17:55:29 +00001058
1059#define NUM_CORE_REGS 73
1060
Andreas Färberf3840912012-02-20 06:44:56 +01001061static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
bellard6f970bd2005-12-05 19:55:19 +00001062{
pbrook56aebc82008-10-11 17:55:29 +00001063 if (n < 32) {
1064 GET_REGL(env->active_tc.gpr[n]);
1065 }
1066 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1067 if (n >= 38 && n < 70) {
ths7ac256b2007-10-25 21:30:37 +00001068 if (env->CP0_Status & (1 << CP0St_FR))
pbrook56aebc82008-10-11 17:55:29 +00001069 GET_REGL(env->active_fpu.fpr[n - 38].d);
ths7ac256b2007-10-25 21:30:37 +00001070 else
pbrook56aebc82008-10-11 17:55:29 +00001071 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1072 }
1073 switch (n) {
1074 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1075 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1076 }
1077 }
1078 switch (n) {
1079 case 32: GET_REGL((int32_t)env->CP0_Status);
1080 case 33: GET_REGL(env->active_tc.LO[0]);
1081 case 34: GET_REGL(env->active_tc.HI[0]);
1082 case 35: GET_REGL(env->CP0_BadVAddr);
1083 case 36: GET_REGL((int32_t)env->CP0_Cause);
Nathan Froydff1d1972009-12-08 08:06:30 -08001084 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
pbrook56aebc82008-10-11 17:55:29 +00001085 case 72: GET_REGL(0); /* fp */
1086 case 89: GET_REGL((int32_t)env->CP0_PRid);
1087 }
1088 if (n >= 73 && n <= 88) {
1089 /* 16 embedded regs. */
1090 GET_REGL(0);
1091 }
ths36d23952007-02-28 22:37:42 +00001092
pbrook56aebc82008-10-11 17:55:29 +00001093 return 0;
bellard6f970bd2005-12-05 19:55:19 +00001094}
1095
ths8e33c082006-12-11 19:22:27 +00001096/* convert MIPS rounding mode in FCR31 to IEEE library */
1097static unsigned int ieee_rm[] =
1098 {
1099 float_round_nearest_even,
1100 float_round_to_zero,
1101 float_round_up,
1102 float_round_down
1103 };
1104#define RESTORE_ROUNDING_MODE \
thsf01be152008-09-18 11:57:27 +00001105 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
ths8e33c082006-12-11 19:22:27 +00001106
Andreas Färberf3840912012-02-20 06:44:56 +01001107static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
bellard6f970bd2005-12-05 19:55:19 +00001108{
pbrook56aebc82008-10-11 17:55:29 +00001109 target_ulong tmp;
bellard6f970bd2005-12-05 19:55:19 +00001110
pbrook56aebc82008-10-11 17:55:29 +00001111 tmp = ldtul_p(mem_buf);
bellard6f970bd2005-12-05 19:55:19 +00001112
pbrook56aebc82008-10-11 17:55:29 +00001113 if (n < 32) {
1114 env->active_tc.gpr[n] = tmp;
1115 return sizeof(target_ulong);
1116 }
1117 if (env->CP0_Config1 & (1 << CP0C1_FP)
1118 && n >= 38 && n < 73) {
1119 if (n < 70) {
ths7ac256b2007-10-25 21:30:37 +00001120 if (env->CP0_Status & (1 << CP0St_FR))
pbrook56aebc82008-10-11 17:55:29 +00001121 env->active_fpu.fpr[n - 38].d = tmp;
ths7ac256b2007-10-25 21:30:37 +00001122 else
pbrook56aebc82008-10-11 17:55:29 +00001123 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1124 }
1125 switch (n) {
1126 case 70:
1127 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1128 /* set rounding mode */
1129 RESTORE_ROUNDING_MODE;
pbrook56aebc82008-10-11 17:55:29 +00001130 break;
1131 case 71: env->active_fpu.fcr0 = tmp; break;
1132 }
1133 return sizeof(target_ulong);
1134 }
1135 switch (n) {
1136 case 32: env->CP0_Status = tmp; break;
1137 case 33: env->active_tc.LO[0] = tmp; break;
1138 case 34: env->active_tc.HI[0] = tmp; break;
1139 case 35: env->CP0_BadVAddr = tmp; break;
1140 case 36: env->CP0_Cause = tmp; break;
Nathan Froydff1d1972009-12-08 08:06:30 -08001141 case 37:
1142 env->active_tc.PC = tmp & ~(target_ulong)1;
1143 if (tmp & 1) {
1144 env->hflags |= MIPS_HFLAG_M16;
1145 } else {
1146 env->hflags &= ~(MIPS_HFLAG_M16);
1147 }
1148 break;
pbrook56aebc82008-10-11 17:55:29 +00001149 case 72: /* fp, ignored */ break;
1150 default:
1151 if (n > 89)
1152 return 0;
1153 /* Other registers are readonly. Ignore writes. */
1154 break;
1155 }
1156
1157 return sizeof(target_ulong);
bellard6f970bd2005-12-05 19:55:19 +00001158}
Jia Liufc043552012-07-20 15:50:50 +08001159#elif defined(TARGET_OPENRISC)
1160
1161#define NUM_CORE_REGS (32 + 3)
1162
1163static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
1164{
1165 if (n < 32) {
1166 GET_REG32(env->gpr[n]);
1167 } else {
1168 switch (n) {
1169 case 32: /* PPC */
1170 GET_REG32(env->ppc);
1171 break;
1172
1173 case 33: /* NPC */
1174 GET_REG32(env->npc);
1175 break;
1176
1177 case 34: /* SR */
1178 GET_REG32(env->sr);
1179 break;
1180
1181 default:
1182 break;
1183 }
1184 }
1185 return 0;
1186}
1187
1188static int cpu_gdb_write_register(CPUOpenRISCState *env,
1189 uint8_t *mem_buf, int n)
1190{
1191 uint32_t tmp;
1192
1193 if (n > NUM_CORE_REGS) {
1194 return 0;
1195 }
1196
1197 tmp = ldl_p(mem_buf);
1198
1199 if (n < 32) {
1200 env->gpr[n] = tmp;
1201 } else {
1202 switch (n) {
1203 case 32: /* PPC */
1204 env->ppc = tmp;
1205 break;
1206
1207 case 33: /* NPC */
1208 env->npc = tmp;
1209 break;
1210
1211 case 34: /* SR */
1212 env->sr = tmp;
1213 break;
1214
1215 default:
1216 break;
1217 }
1218 }
1219 return 4;
1220}
bellardfdf9b3e2006-04-27 21:07:38 +00001221#elif defined (TARGET_SH4)
ths6ef99fc2007-05-13 16:36:24 +00001222
1223/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
pbrook56aebc82008-10-11 17:55:29 +00001224/* FIXME: We should use XML for this. */
ths6ef99fc2007-05-13 16:36:24 +00001225
pbrook56aebc82008-10-11 17:55:29 +00001226#define NUM_CORE_REGS 59
1227
Andreas Färberf3840912012-02-20 06:44:56 +01001228static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
bellardfdf9b3e2006-04-27 21:07:38 +00001229{
Aurelien Jarnoeca5c302012-09-16 13:12:21 +02001230 switch (n) {
1231 case 0 ... 7:
pbrook56aebc82008-10-11 17:55:29 +00001232 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1233 GET_REGL(env->gregs[n + 16]);
1234 } else {
1235 GET_REGL(env->gregs[n]);
1236 }
Aurelien Jarnoeca5c302012-09-16 13:12:21 +02001237 case 8 ... 15:
takasi-y@ops.dti.ne.jpe192a452010-02-18 00:53:29 +09001238 GET_REGL(env->gregs[n]);
Aurelien Jarnoeca5c302012-09-16 13:12:21 +02001239 case 16:
1240 GET_REGL(env->pc);
1241 case 17:
1242 GET_REGL(env->pr);
1243 case 18:
1244 GET_REGL(env->gbr);
1245 case 19:
1246 GET_REGL(env->vbr);
1247 case 20:
1248 GET_REGL(env->mach);
1249 case 21:
1250 GET_REGL(env->macl);
1251 case 22:
1252 GET_REGL(env->sr);
1253 case 23:
1254 GET_REGL(env->fpul);
1255 case 24:
1256 GET_REGL(env->fpscr);
1257 case 25 ... 40:
1258 if (env->fpscr & FPSCR_FR) {
1259 stfl_p(mem_buf, env->fregs[n - 9]);
1260 } else {
1261 stfl_p(mem_buf, env->fregs[n - 25]);
1262 }
1263 return 4;
1264 case 41:
1265 GET_REGL(env->ssr);
1266 case 42:
1267 GET_REGL(env->spc);
1268 case 43 ... 50:
1269 GET_REGL(env->gregs[n - 43]);
1270 case 51 ... 58:
1271 GET_REGL(env->gregs[n - (51 - 16)]);
pbrook56aebc82008-10-11 17:55:29 +00001272 }
bellardfdf9b3e2006-04-27 21:07:38 +00001273
pbrook56aebc82008-10-11 17:55:29 +00001274 return 0;
bellardfdf9b3e2006-04-27 21:07:38 +00001275}
1276
Andreas Färberf3840912012-02-20 06:44:56 +01001277static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
bellardfdf9b3e2006-04-27 21:07:38 +00001278{
pbrook56aebc82008-10-11 17:55:29 +00001279 switch (n) {
Aurelien Jarnoeca5c302012-09-16 13:12:21 +02001280 case 0 ... 7:
1281 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1282 env->gregs[n + 16] = ldl_p(mem_buf);
1283 } else {
1284 env->gregs[n] = ldl_p(mem_buf);
1285 }
1286 break;
1287 case 8 ... 15:
1288 env->gregs[n] = ldl_p(mem_buf);
1289 break;
1290 case 16:
1291 env->pc = ldl_p(mem_buf);
1292 break;
1293 case 17:
1294 env->pr = ldl_p(mem_buf);
1295 break;
1296 case 18:
1297 env->gbr = ldl_p(mem_buf);
1298 break;
1299 case 19:
1300 env->vbr = ldl_p(mem_buf);
1301 break;
1302 case 20:
1303 env->mach = ldl_p(mem_buf);
1304 break;
1305 case 21:
1306 env->macl = ldl_p(mem_buf);
1307 break;
1308 case 22:
1309 env->sr = ldl_p(mem_buf);
1310 break;
1311 case 23:
1312 env->fpul = ldl_p(mem_buf);
1313 break;
1314 case 24:
1315 env->fpscr = ldl_p(mem_buf);
1316 break;
1317 case 25 ... 40:
1318 if (env->fpscr & FPSCR_FR) {
1319 env->fregs[n - 9] = ldfl_p(mem_buf);
1320 } else {
1321 env->fregs[n - 25] = ldfl_p(mem_buf);
1322 }
1323 break;
1324 case 41:
1325 env->ssr = ldl_p(mem_buf);
1326 break;
1327 case 42:
1328 env->spc = ldl_p(mem_buf);
1329 break;
1330 case 43 ... 50:
1331 env->gregs[n - 43] = ldl_p(mem_buf);
1332 break;
1333 case 51 ... 58:
1334 env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
1335 break;
pbrook56aebc82008-10-11 17:55:29 +00001336 default: return 0;
1337 }
1338
1339 return 4;
bellardfdf9b3e2006-04-27 21:07:38 +00001340}
Edgar E. Iglesiasd74d6a92009-05-20 20:16:31 +02001341#elif defined (TARGET_MICROBLAZE)
1342
1343#define NUM_CORE_REGS (32 + 5)
1344
Andreas Färberf3840912012-02-20 06:44:56 +01001345static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
Edgar E. Iglesiasd74d6a92009-05-20 20:16:31 +02001346{
1347 if (n < 32) {
1348 GET_REG32(env->regs[n]);
1349 } else {
1350 GET_REG32(env->sregs[n - 32]);
1351 }
1352 return 0;
1353}
1354
Andreas Färberf3840912012-02-20 06:44:56 +01001355static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
Edgar E. Iglesiasd74d6a92009-05-20 20:16:31 +02001356{
1357 uint32_t tmp;
1358
1359 if (n > NUM_CORE_REGS)
1360 return 0;
1361
1362 tmp = ldl_p(mem_buf);
1363
1364 if (n < 32) {
1365 env->regs[n] = tmp;
1366 } else {
1367 env->sregs[n - 32] = tmp;
1368 }
1369 return 4;
1370}
thsf1ccf902007-10-08 13:16:14 +00001371#elif defined (TARGET_CRIS)
1372
pbrook56aebc82008-10-11 17:55:29 +00001373#define NUM_CORE_REGS 49
1374
Edgar E. Iglesias4a0b59f2010-02-20 19:51:56 +01001375static int
Andreas Färberf3840912012-02-20 06:44:56 +01001376read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
Edgar E. Iglesias4a0b59f2010-02-20 19:51:56 +01001377{
1378 if (n < 15) {
1379 GET_REG32(env->regs[n]);
1380 }
1381
1382 if (n == 15) {
1383 GET_REG32(env->pc);
1384 }
1385
1386 if (n < 32) {
1387 switch (n) {
1388 case 16:
1389 GET_REG8(env->pregs[n - 16]);
1390 break;
1391 case 17:
1392 GET_REG8(env->pregs[n - 16]);
1393 break;
1394 case 20:
1395 case 21:
1396 GET_REG16(env->pregs[n - 16]);
1397 break;
1398 default:
1399 if (n >= 23) {
1400 GET_REG32(env->pregs[n - 16]);
1401 }
1402 break;
1403 }
1404 }
1405 return 0;
1406}
1407
Andreas Färberf3840912012-02-20 06:44:56 +01001408static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
thsf1ccf902007-10-08 13:16:14 +00001409{
pbrook56aebc82008-10-11 17:55:29 +00001410 uint8_t srs;
1411
Edgar E. Iglesias4a0b59f2010-02-20 19:51:56 +01001412 if (env->pregs[PR_VR] < 32)
1413 return read_register_crisv10(env, mem_buf, n);
1414
pbrook56aebc82008-10-11 17:55:29 +00001415 srs = env->pregs[PR_SRS];
1416 if (n < 16) {
1417 GET_REG32(env->regs[n]);
1418 }
1419
1420 if (n >= 21 && n < 32) {
1421 GET_REG32(env->pregs[n - 16]);
1422 }
1423 if (n >= 33 && n < 49) {
1424 GET_REG32(env->sregs[srs][n - 33]);
1425 }
1426 switch (n) {
1427 case 16: GET_REG8(env->pregs[0]);
1428 case 17: GET_REG8(env->pregs[1]);
1429 case 18: GET_REG32(env->pregs[2]);
1430 case 19: GET_REG8(srs);
1431 case 20: GET_REG16(env->pregs[4]);
1432 case 32: GET_REG32(env->pc);
1433 }
1434
1435 return 0;
thsf1ccf902007-10-08 13:16:14 +00001436}
1437
Andreas Färberf3840912012-02-20 06:44:56 +01001438static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
thsf1ccf902007-10-08 13:16:14 +00001439{
pbrook56aebc82008-10-11 17:55:29 +00001440 uint32_t tmp;
thsf1ccf902007-10-08 13:16:14 +00001441
pbrook56aebc82008-10-11 17:55:29 +00001442 if (n > 49)
1443 return 0;
thsf1ccf902007-10-08 13:16:14 +00001444
pbrook56aebc82008-10-11 17:55:29 +00001445 tmp = ldl_p(mem_buf);
thsf1ccf902007-10-08 13:16:14 +00001446
pbrook56aebc82008-10-11 17:55:29 +00001447 if (n < 16) {
1448 env->regs[n] = tmp;
1449 }
thsf1ccf902007-10-08 13:16:14 +00001450
edgar_igld7b69672008-10-11 19:32:21 +00001451 if (n >= 21 && n < 32) {
1452 env->pregs[n - 16] = tmp;
1453 }
1454
1455 /* FIXME: Should support function regs be writable? */
pbrook56aebc82008-10-11 17:55:29 +00001456 switch (n) {
1457 case 16: return 1;
1458 case 17: return 1;
edgar_igld7b69672008-10-11 19:32:21 +00001459 case 18: env->pregs[PR_PID] = tmp; break;
pbrook56aebc82008-10-11 17:55:29 +00001460 case 19: return 1;
1461 case 20: return 2;
1462 case 32: env->pc = tmp; break;
1463 }
thsf1ccf902007-10-08 13:16:14 +00001464
pbrook56aebc82008-10-11 17:55:29 +00001465 return 4;
thsf1ccf902007-10-08 13:16:14 +00001466}
aurel3219bf5172008-12-07 23:26:32 +00001467#elif defined (TARGET_ALPHA)
1468
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001469#define NUM_CORE_REGS 67
aurel3219bf5172008-12-07 23:26:32 +00001470
Andreas Färberf3840912012-02-20 06:44:56 +01001471static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
aurel3219bf5172008-12-07 23:26:32 +00001472{
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001473 uint64_t val;
1474 CPU_DoubleU d;
aurel3219bf5172008-12-07 23:26:32 +00001475
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001476 switch (n) {
1477 case 0 ... 30:
1478 val = env->ir[n];
1479 break;
1480 case 32 ... 62:
1481 d.d = env->fir[n - 32];
1482 val = d.ll;
1483 break;
1484 case 63:
1485 val = cpu_alpha_load_fpcr(env);
1486 break;
1487 case 64:
1488 val = env->pc;
1489 break;
1490 case 66:
1491 val = env->unique;
1492 break;
1493 case 31:
1494 case 65:
1495 /* 31 really is the zero register; 65 is unassigned in the
1496 gdb protocol, but is still required to occupy 8 bytes. */
1497 val = 0;
1498 break;
1499 default:
1500 return 0;
aurel3219bf5172008-12-07 23:26:32 +00001501 }
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001502 GET_REGL(val);
aurel3219bf5172008-12-07 23:26:32 +00001503}
1504
Andreas Färberf3840912012-02-20 06:44:56 +01001505static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
aurel3219bf5172008-12-07 23:26:32 +00001506{
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001507 target_ulong tmp = ldtul_p(mem_buf);
1508 CPU_DoubleU d;
aurel3219bf5172008-12-07 23:26:32 +00001509
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001510 switch (n) {
1511 case 0 ... 30:
aurel3219bf5172008-12-07 23:26:32 +00001512 env->ir[n] = tmp;
Richard Henderson7c5a90d2009-12-31 11:54:01 -08001513 break;
1514 case 32 ... 62:
1515 d.ll = tmp;
1516 env->fir[n - 32] = d.d;
1517 break;
1518 case 63:
1519 cpu_alpha_store_fpcr(env, tmp);
1520 break;
1521 case 64:
1522 env->pc = tmp;
1523 break;
1524 case 66:
1525 env->unique = tmp;
1526 break;
1527 case 31:
1528 case 65:
1529 /* 31 really is the zero register; 65 is unassigned in the
1530 gdb protocol, but is still required to occupy 8 bytes. */
1531 break;
1532 default:
1533 return 0;
aurel3219bf5172008-12-07 23:26:32 +00001534 }
aurel3219bf5172008-12-07 23:26:32 +00001535 return 8;
1536}
Alexander Grafafcb0e42009-12-05 12:44:29 +01001537#elif defined (TARGET_S390X)
1538
Richard Henderson6ee77b12012-08-23 10:44:45 -07001539#define NUM_CORE_REGS S390_NUM_REGS
Alexander Grafafcb0e42009-12-05 12:44:29 +01001540
Andreas Färberf3840912012-02-20 06:44:56 +01001541static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
Alexander Grafafcb0e42009-12-05 12:44:29 +01001542{
Richard Henderson6ee77b12012-08-23 10:44:45 -07001543 uint64_t val;
1544 int cc_op;
1545
Alexander Grafafcb0e42009-12-05 12:44:29 +01001546 switch (n) {
Richard Henderson6ee77b12012-08-23 10:44:45 -07001547 case S390_PSWM_REGNUM:
1548 cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
1549 val = deposit64(env->psw.mask, 44, 2, cc_op);
1550 GET_REGL(val);
1551 break;
1552 case S390_PSWA_REGNUM:
1553 GET_REGL(env->psw.addr);
1554 break;
1555 case S390_R0_REGNUM ... S390_R15_REGNUM:
1556 GET_REGL(env->regs[n-S390_R0_REGNUM]);
1557 break;
1558 case S390_A0_REGNUM ... S390_A15_REGNUM:
1559 GET_REG32(env->aregs[n-S390_A0_REGNUM]);
1560 break;
1561 case S390_FPC_REGNUM:
1562 GET_REG32(env->fpc);
1563 break;
1564 case S390_F0_REGNUM ... S390_F15_REGNUM:
1565 GET_REG64(env->fregs[n-S390_F0_REGNUM].ll);
1566 break;
Alexander Grafafcb0e42009-12-05 12:44:29 +01001567 }
1568
1569 return 0;
1570}
1571
Andreas Färberf3840912012-02-20 06:44:56 +01001572static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
Alexander Grafafcb0e42009-12-05 12:44:29 +01001573{
1574 target_ulong tmpl;
1575 uint32_t tmp32;
1576 int r = 8;
1577 tmpl = ldtul_p(mem_buf);
1578 tmp32 = ldl_p(mem_buf);
1579
1580 switch (n) {
Richard Henderson6ee77b12012-08-23 10:44:45 -07001581 case S390_PSWM_REGNUM:
1582 env->psw.mask = tmpl;
1583 env->cc_op = extract64(tmpl, 44, 2);
1584 break;
1585 case S390_PSWA_REGNUM:
1586 env->psw.addr = tmpl;
1587 break;
1588 case S390_R0_REGNUM ... S390_R15_REGNUM:
1589 env->regs[n-S390_R0_REGNUM] = tmpl;
1590 break;
1591 case S390_A0_REGNUM ... S390_A15_REGNUM:
1592 env->aregs[n-S390_A0_REGNUM] = tmp32;
1593 r = 4;
1594 break;
1595 case S390_FPC_REGNUM:
1596 env->fpc = tmp32;
1597 r = 4;
1598 break;
1599 case S390_F0_REGNUM ... S390_F15_REGNUM:
1600 env->fregs[n-S390_F0_REGNUM].ll = tmpl;
1601 break;
1602 default:
1603 return 0;
Alexander Grafafcb0e42009-12-05 12:44:29 +01001604 }
Alexander Grafafcb0e42009-12-05 12:44:29 +01001605 return r;
1606}
Michael Walle0c45d3d2011-02-17 23:45:06 +01001607#elif defined (TARGET_LM32)
1608
1609#include "hw/lm32_pic.h"
1610#define NUM_CORE_REGS (32 + 7)
1611
Andreas Färberf3840912012-02-20 06:44:56 +01001612static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
Michael Walle0c45d3d2011-02-17 23:45:06 +01001613{
1614 if (n < 32) {
1615 GET_REG32(env->regs[n]);
1616 } else {
1617 switch (n) {
1618 case 32:
1619 GET_REG32(env->pc);
1620 break;
1621 /* FIXME: put in right exception ID */
1622 case 33:
1623 GET_REG32(0);
1624 break;
1625 case 34:
1626 GET_REG32(env->eba);
1627 break;
1628 case 35:
1629 GET_REG32(env->deba);
1630 break;
1631 case 36:
1632 GET_REG32(env->ie);
1633 break;
1634 case 37:
1635 GET_REG32(lm32_pic_get_im(env->pic_state));
1636 break;
1637 case 38:
1638 GET_REG32(lm32_pic_get_ip(env->pic_state));
1639 break;
1640 }
1641 }
1642 return 0;
1643}
1644
Andreas Färberf3840912012-02-20 06:44:56 +01001645static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
Michael Walle0c45d3d2011-02-17 23:45:06 +01001646{
1647 uint32_t tmp;
1648
1649 if (n > NUM_CORE_REGS) {
1650 return 0;
1651 }
1652
1653 tmp = ldl_p(mem_buf);
1654
1655 if (n < 32) {
1656 env->regs[n] = tmp;
1657 } else {
1658 switch (n) {
1659 case 32:
1660 env->pc = tmp;
1661 break;
1662 case 34:
1663 env->eba = tmp;
1664 break;
1665 case 35:
1666 env->deba = tmp;
1667 break;
1668 case 36:
1669 env->ie = tmp;
1670 break;
1671 case 37:
1672 lm32_pic_set_im(env->pic_state, tmp);
1673 break;
1674 case 38:
1675 lm32_pic_set_ip(env->pic_state, tmp);
1676 break;
1677 }
1678 }
1679 return 4;
1680}
Max Filippovccfcaba2011-09-06 03:55:52 +04001681#elif defined(TARGET_XTENSA)
1682
1683/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
1684 * Use num_regs to see all registers. gdb modification is required for that:
1685 * reset bit 0 in the 'flags' field of the registers definitions in the
1686 * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
1687 */
1688#define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
1689#define num_g_regs NUM_CORE_REGS
1690
Andreas Färberf3840912012-02-20 06:44:56 +01001691static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
Max Filippovccfcaba2011-09-06 03:55:52 +04001692{
1693 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1694
1695 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1696 return 0;
1697 }
1698
1699 switch (reg->type) {
1700 case 9: /*pc*/
1701 GET_REG32(env->pc);
1702 break;
1703
1704 case 1: /*ar*/
1705 xtensa_sync_phys_from_window(env);
1706 GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
1707 break;
1708
1709 case 2: /*SR*/
1710 GET_REG32(env->sregs[reg->targno & 0xff]);
1711 break;
1712
1713 case 3: /*UR*/
1714 GET_REG32(env->uregs[reg->targno & 0xff]);
1715 break;
1716
Max Filippovdd519cb2012-09-19 04:23:54 +04001717 case 4: /*f*/
1718 GET_REG32(float32_val(env->fregs[reg->targno & 0x0f]));
1719 break;
1720
Max Filippovccfcaba2011-09-06 03:55:52 +04001721 case 8: /*a*/
1722 GET_REG32(env->regs[reg->targno & 0x0f]);
1723 break;
1724
1725 default:
1726 qemu_log("%s from reg %d of unsupported type %d\n",
1727 __func__, n, reg->type);
1728 return 0;
1729 }
1730}
1731
Andreas Färberf3840912012-02-20 06:44:56 +01001732static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
Max Filippovccfcaba2011-09-06 03:55:52 +04001733{
1734 uint32_t tmp;
1735 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1736
1737 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1738 return 0;
1739 }
1740
1741 tmp = ldl_p(mem_buf);
1742
1743 switch (reg->type) {
1744 case 9: /*pc*/
1745 env->pc = tmp;
1746 break;
1747
1748 case 1: /*ar*/
1749 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
1750 xtensa_sync_window_from_phys(env);
1751 break;
1752
1753 case 2: /*SR*/
1754 env->sregs[reg->targno & 0xff] = tmp;
1755 break;
1756
1757 case 3: /*UR*/
1758 env->uregs[reg->targno & 0xff] = tmp;
1759 break;
1760
Max Filippovdd519cb2012-09-19 04:23:54 +04001761 case 4: /*f*/
1762 env->fregs[reg->targno & 0x0f] = make_float32(tmp);
1763 break;
1764
Max Filippovccfcaba2011-09-06 03:55:52 +04001765 case 8: /*a*/
1766 env->regs[reg->targno & 0x0f] = tmp;
1767 break;
1768
1769 default:
1770 qemu_log("%s to reg %d of unsupported type %d\n",
1771 __func__, n, reg->type);
1772 return 0;
1773 }
1774
1775 return 4;
1776}
bellard1fddef42005-04-17 19:16:13 +00001777#else
pbrook56aebc82008-10-11 17:55:29 +00001778
1779#define NUM_CORE_REGS 0
1780
Andreas Färber9349b4f2012-03-14 01:38:32 +01001781static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
bellard6da41ea2004-01-04 15:48:38 +00001782{
1783 return 0;
1784}
1785
Andreas Färber9349b4f2012-03-14 01:38:32 +01001786static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
bellard6da41ea2004-01-04 15:48:38 +00001787{
pbrook56aebc82008-10-11 17:55:29 +00001788 return 0;
bellard6da41ea2004-01-04 15:48:38 +00001789}
1790
1791#endif
bellardb4608c02003-06-27 17:34:32 +00001792
Max Filippovccfcaba2011-09-06 03:55:52 +04001793#if !defined(TARGET_XTENSA)
pbrook56aebc82008-10-11 17:55:29 +00001794static int num_g_regs = NUM_CORE_REGS;
Max Filippovccfcaba2011-09-06 03:55:52 +04001795#endif
pbrook56aebc82008-10-11 17:55:29 +00001796
1797#ifdef GDB_CORE_XML
1798/* Encode data using the encoding for 'x' packets. */
1799static int memtox(char *buf, const char *mem, int len)
1800{
1801 char *p = buf;
1802 char c;
1803
1804 while (len--) {
1805 c = *(mem++);
1806 switch (c) {
1807 case '#': case '$': case '*': case '}':
1808 *(p++) = '}';
1809 *(p++) = c ^ 0x20;
1810 break;
1811 default:
1812 *(p++) = c;
1813 break;
1814 }
1815 }
1816 return p - buf;
1817}
1818
aurel323faf7782008-12-07 23:26:17 +00001819static const char *get_feature_xml(const char *p, const char **newp)
pbrook56aebc82008-10-11 17:55:29 +00001820{
pbrook56aebc82008-10-11 17:55:29 +00001821 size_t len;
1822 int i;
1823 const char *name;
1824 static char target_xml[1024];
1825
1826 len = 0;
1827 while (p[len] && p[len] != ':')
1828 len++;
1829 *newp = p + len;
1830
1831 name = NULL;
1832 if (strncmp(p, "target.xml", len) == 0) {
1833 /* Generate the XML description for this CPU. */
1834 if (!target_xml[0]) {
1835 GDBRegisterState *r;
1836
blueswir15b3715b2008-10-25 11:18:12 +00001837 snprintf(target_xml, sizeof(target_xml),
1838 "<?xml version=\"1.0\"?>"
1839 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1840 "<target>"
1841 "<xi:include href=\"%s\"/>",
1842 GDB_CORE_XML);
pbrook56aebc82008-10-11 17:55:29 +00001843
aliguori880a7572008-11-18 20:30:24 +00001844 for (r = first_cpu->gdb_regs; r; r = r->next) {
blueswir12dc766d2009-04-13 16:06:19 +00001845 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1846 pstrcat(target_xml, sizeof(target_xml), r->xml);
1847 pstrcat(target_xml, sizeof(target_xml), "\"/>");
pbrook56aebc82008-10-11 17:55:29 +00001848 }
blueswir12dc766d2009-04-13 16:06:19 +00001849 pstrcat(target_xml, sizeof(target_xml), "</target>");
pbrook56aebc82008-10-11 17:55:29 +00001850 }
1851 return target_xml;
1852 }
1853 for (i = 0; ; i++) {
1854 name = xml_builtin[i][0];
1855 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1856 break;
1857 }
1858 return name ? xml_builtin[i][1] : NULL;
1859}
1860#endif
1861
Andreas Färber9349b4f2012-03-14 01:38:32 +01001862static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
pbrook56aebc82008-10-11 17:55:29 +00001863{
1864 GDBRegisterState *r;
1865
1866 if (reg < NUM_CORE_REGS)
1867 return cpu_gdb_read_register(env, mem_buf, reg);
1868
1869 for (r = env->gdb_regs; r; r = r->next) {
1870 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1871 return r->get_reg(env, mem_buf, reg - r->base_reg);
1872 }
1873 }
1874 return 0;
1875}
1876
Andreas Färber9349b4f2012-03-14 01:38:32 +01001877static int gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int reg)
pbrook56aebc82008-10-11 17:55:29 +00001878{
1879 GDBRegisterState *r;
1880
1881 if (reg < NUM_CORE_REGS)
1882 return cpu_gdb_write_register(env, mem_buf, reg);
1883
1884 for (r = env->gdb_regs; r; r = r->next) {
1885 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1886 return r->set_reg(env, mem_buf, reg - r->base_reg);
1887 }
1888 }
1889 return 0;
1890}
1891
Max Filippovccfcaba2011-09-06 03:55:52 +04001892#if !defined(TARGET_XTENSA)
pbrook56aebc82008-10-11 17:55:29 +00001893/* Register a supplemental set of CPU registers. If g_pos is nonzero it
1894 specifies the first register number and these registers are included in
1895 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1896 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1897 */
1898
Andreas Färber9349b4f2012-03-14 01:38:32 +01001899void gdb_register_coprocessor(CPUArchState * env,
pbrook56aebc82008-10-11 17:55:29 +00001900 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1901 int num_regs, const char *xml, int g_pos)
1902{
1903 GDBRegisterState *s;
1904 GDBRegisterState **p;
1905 static int last_reg = NUM_CORE_REGS;
1906
pbrook56aebc82008-10-11 17:55:29 +00001907 p = &env->gdb_regs;
1908 while (*p) {
1909 /* Check for duplicates. */
1910 if (strcmp((*p)->xml, xml) == 0)
1911 return;
1912 p = &(*p)->next;
1913 }
Stefan Weil9643c252011-10-18 22:25:38 +02001914
1915 s = g_new0(GDBRegisterState, 1);
1916 s->base_reg = last_reg;
1917 s->num_regs = num_regs;
1918 s->get_reg = get_reg;
1919 s->set_reg = set_reg;
1920 s->xml = xml;
1921
pbrook56aebc82008-10-11 17:55:29 +00001922 /* Add to end of list. */
1923 last_reg += num_regs;
1924 *p = s;
1925 if (g_pos) {
1926 if (g_pos != s->base_reg) {
1927 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1928 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1929 } else {
1930 num_g_regs = last_reg;
1931 }
1932 }
1933}
Max Filippovccfcaba2011-09-06 03:55:52 +04001934#endif
pbrook56aebc82008-10-11 17:55:29 +00001935
aliguoria1d1bb32008-11-18 20:07:32 +00001936#ifndef CONFIG_USER_ONLY
1937static const int xlat_gdb_type[] = {
1938 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1939 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1940 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1941};
1942#endif
1943
aliguori880a7572008-11-18 20:30:24 +00001944static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
aliguoria1d1bb32008-11-18 20:07:32 +00001945{
Andreas Färber9349b4f2012-03-14 01:38:32 +01001946 CPUArchState *env;
aliguori880a7572008-11-18 20:30:24 +00001947 int err = 0;
1948
aliguorie22a25c2009-03-12 20:12:48 +00001949 if (kvm_enabled())
1950 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1951
aliguoria1d1bb32008-11-18 20:07:32 +00001952 switch (type) {
1953 case GDB_BREAKPOINT_SW:
1954 case GDB_BREAKPOINT_HW:
aliguori880a7572008-11-18 20:30:24 +00001955 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1956 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1957 if (err)
1958 break;
1959 }
1960 return err;
aliguoria1d1bb32008-11-18 20:07:32 +00001961#ifndef CONFIG_USER_ONLY
1962 case GDB_WATCHPOINT_WRITE:
1963 case GDB_WATCHPOINT_READ:
1964 case GDB_WATCHPOINT_ACCESS:
aliguori880a7572008-11-18 20:30:24 +00001965 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1966 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1967 NULL);
1968 if (err)
1969 break;
1970 }
1971 return err;
aliguoria1d1bb32008-11-18 20:07:32 +00001972#endif
1973 default:
1974 return -ENOSYS;
1975 }
1976}
1977
aliguori880a7572008-11-18 20:30:24 +00001978static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
aliguoria1d1bb32008-11-18 20:07:32 +00001979{
Andreas Färber9349b4f2012-03-14 01:38:32 +01001980 CPUArchState *env;
aliguori880a7572008-11-18 20:30:24 +00001981 int err = 0;
1982
aliguorie22a25c2009-03-12 20:12:48 +00001983 if (kvm_enabled())
1984 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1985
aliguoria1d1bb32008-11-18 20:07:32 +00001986 switch (type) {
1987 case GDB_BREAKPOINT_SW:
1988 case GDB_BREAKPOINT_HW:
aliguori880a7572008-11-18 20:30:24 +00001989 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1990 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1991 if (err)
1992 break;
1993 }
1994 return err;
aliguoria1d1bb32008-11-18 20:07:32 +00001995#ifndef CONFIG_USER_ONLY
1996 case GDB_WATCHPOINT_WRITE:
1997 case GDB_WATCHPOINT_READ:
1998 case GDB_WATCHPOINT_ACCESS:
aliguori880a7572008-11-18 20:30:24 +00001999 for (env = first_cpu; env != NULL; env = env->next_cpu) {
2000 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
2001 if (err)
2002 break;
2003 }
2004 return err;
aliguoria1d1bb32008-11-18 20:07:32 +00002005#endif
2006 default:
2007 return -ENOSYS;
2008 }
2009}
2010
aliguori880a7572008-11-18 20:30:24 +00002011static void gdb_breakpoint_remove_all(void)
aliguoria1d1bb32008-11-18 20:07:32 +00002012{
Andreas Färber9349b4f2012-03-14 01:38:32 +01002013 CPUArchState *env;
aliguori880a7572008-11-18 20:30:24 +00002014
aliguorie22a25c2009-03-12 20:12:48 +00002015 if (kvm_enabled()) {
2016 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
2017 return;
2018 }
2019
aliguori880a7572008-11-18 20:30:24 +00002020 for (env = first_cpu; env != NULL; env = env->next_cpu) {
2021 cpu_breakpoint_remove_all(env, BP_GDB);
aliguoria1d1bb32008-11-18 20:07:32 +00002022#ifndef CONFIG_USER_ONLY
aliguori880a7572008-11-18 20:30:24 +00002023 cpu_watchpoint_remove_all(env, BP_GDB);
aliguoria1d1bb32008-11-18 20:07:32 +00002024#endif
aliguori880a7572008-11-18 20:30:24 +00002025 }
aliguoria1d1bb32008-11-18 20:07:32 +00002026}
2027
aurel32fab9d282009-04-08 21:29:37 +00002028static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
2029{
Avi Kivity4c0960c2009-08-17 23:19:53 +03002030 cpu_synchronize_state(s->c_cpu);
Peter Maydella896d032012-03-12 06:24:45 +00002031#if defined(TARGET_I386)
aurel32fab9d282009-04-08 21:29:37 +00002032 s->c_cpu->eip = pc;
aurel32fab9d282009-04-08 21:29:37 +00002033#elif defined (TARGET_PPC)
2034 s->c_cpu->nip = pc;
2035#elif defined (TARGET_SPARC)
2036 s->c_cpu->pc = pc;
2037 s->c_cpu->npc = pc + 4;
2038#elif defined (TARGET_ARM)
2039 s->c_cpu->regs[15] = pc;
2040#elif defined (TARGET_SH4)
2041 s->c_cpu->pc = pc;
2042#elif defined (TARGET_MIPS)
Nathan Froydff1d1972009-12-08 08:06:30 -08002043 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
2044 if (pc & 1) {
2045 s->c_cpu->hflags |= MIPS_HFLAG_M16;
2046 } else {
2047 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
2048 }
Edgar E. Iglesiasd74d6a92009-05-20 20:16:31 +02002049#elif defined (TARGET_MICROBLAZE)
2050 s->c_cpu->sregs[SR_PC] = pc;
Jia Liufc043552012-07-20 15:50:50 +08002051#elif defined(TARGET_OPENRISC)
2052 s->c_cpu->pc = pc;
aurel32fab9d282009-04-08 21:29:37 +00002053#elif defined (TARGET_CRIS)
2054 s->c_cpu->pc = pc;
2055#elif defined (TARGET_ALPHA)
2056 s->c_cpu->pc = pc;
Alexander Grafafcb0e42009-12-05 12:44:29 +01002057#elif defined (TARGET_S390X)
Alexander Grafafcb0e42009-12-05 12:44:29 +01002058 s->c_cpu->psw.addr = pc;
Michael Walle0c45d3d2011-02-17 23:45:06 +01002059#elif defined (TARGET_LM32)
2060 s->c_cpu->pc = pc;
Max Filippovccfcaba2011-09-06 03:55:52 +04002061#elif defined(TARGET_XTENSA)
2062 s->c_cpu->pc = pc;
aurel32fab9d282009-04-08 21:29:37 +00002063#endif
2064}
2065
Andreas Färber9349b4f2012-03-14 01:38:32 +01002066static CPUArchState *find_cpu(uint32_t thread_id)
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002067{
Andreas Färber9349b4f2012-03-14 01:38:32 +01002068 CPUArchState *env;
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002069
2070 for (env = first_cpu; env != NULL; env = env->next_cpu) {
Wen Congyang68f47302012-05-07 12:10:05 +08002071 if (cpu_index(env) == thread_id) {
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002072 return env;
2073 }
2074 }
2075
2076 return NULL;
2077}
2078
aliguori880a7572008-11-18 20:30:24 +00002079static int gdb_handle_packet(GDBState *s, const char *line_buf)
bellardb4608c02003-06-27 17:34:32 +00002080{
Andreas Färber9349b4f2012-03-14 01:38:32 +01002081 CPUArchState *env;
bellardb4608c02003-06-27 17:34:32 +00002082 const char *p;
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002083 uint32_t thread;
2084 int ch, reg_size, type, res;
pbrook56aebc82008-10-11 17:55:29 +00002085 char buf[MAX_PACKET_LENGTH];
2086 uint8_t mem_buf[MAX_PACKET_LENGTH];
2087 uint8_t *registers;
bellard9d9754a2006-06-25 15:32:37 +00002088 target_ulong addr, len;
ths3b46e622007-09-17 08:09:54 +00002089
bellard858693c2004-03-31 18:52:07 +00002090#ifdef DEBUG_GDB
2091 printf("command='%s'\n", line_buf);
bellard4c3a88a2003-07-26 12:06:08 +00002092#endif
bellard858693c2004-03-31 18:52:07 +00002093 p = line_buf;
2094 ch = *p++;
2095 switch(ch) {
2096 case '?':
bellard1fddef42005-04-17 19:16:13 +00002097 /* TODO: Make this return the correct value for user-mode. */
aurel32ca587a82008-12-18 22:44:13 +00002098 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
Wen Congyang68f47302012-05-07 12:10:05 +08002099 cpu_index(s->c_cpu));
bellard858693c2004-03-31 18:52:07 +00002100 put_packet(s, buf);
edgar_igl7d03f822008-05-17 18:58:29 +00002101 /* Remove all the breakpoints when this query is issued,
2102 * because gdb is doing and initial connect and the state
2103 * should be cleaned up.
2104 */
aliguori880a7572008-11-18 20:30:24 +00002105 gdb_breakpoint_remove_all();
bellard858693c2004-03-31 18:52:07 +00002106 break;
2107 case 'c':
2108 if (*p != '\0') {
bellard9d9754a2006-06-25 15:32:37 +00002109 addr = strtoull(p, (char **)&p, 16);
aurel32fab9d282009-04-08 21:29:37 +00002110 gdb_set_cpu_pc(s, addr);
bellard858693c2004-03-31 18:52:07 +00002111 }
aurel32ca587a82008-12-18 22:44:13 +00002112 s->signal = 0;
edgar_iglba70a622008-03-14 06:10:42 +00002113 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +00002114 return RS_IDLE;
edgar_igl1f487ee2008-05-17 22:20:53 +00002115 case 'C':
aurel32ca587a82008-12-18 22:44:13 +00002116 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
2117 if (s->signal == -1)
2118 s->signal = 0;
edgar_igl1f487ee2008-05-17 22:20:53 +00002119 gdb_continue(s);
2120 return RS_IDLE;
Jan Kiszkadd32aa12009-06-27 09:53:51 +02002121 case 'v':
2122 if (strncmp(p, "Cont", 4) == 0) {
2123 int res_signal, res_thread;
2124
2125 p += 4;
2126 if (*p == '?') {
2127 put_packet(s, "vCont;c;C;s;S");
2128 break;
2129 }
2130 res = 0;
2131 res_signal = 0;
2132 res_thread = 0;
2133 while (*p) {
2134 int action, signal;
2135
2136 if (*p++ != ';') {
2137 res = 0;
2138 break;
2139 }
2140 action = *p++;
2141 signal = 0;
2142 if (action == 'C' || action == 'S') {
2143 signal = strtoul(p, (char **)&p, 16);
2144 } else if (action != 'c' && action != 's') {
2145 res = 0;
2146 break;
2147 }
2148 thread = 0;
2149 if (*p == ':') {
2150 thread = strtoull(p+1, (char **)&p, 16);
2151 }
2152 action = tolower(action);
2153 if (res == 0 || (res == 'c' && action == 's')) {
2154 res = action;
2155 res_signal = signal;
2156 res_thread = thread;
2157 }
2158 }
2159 if (res) {
2160 if (res_thread != -1 && res_thread != 0) {
2161 env = find_cpu(res_thread);
2162 if (env == NULL) {
2163 put_packet(s, "E22");
2164 break;
2165 }
2166 s->c_cpu = env;
2167 }
2168 if (res == 's') {
2169 cpu_single_step(s->c_cpu, sstep_flags);
2170 }
2171 s->signal = res_signal;
2172 gdb_continue(s);
2173 return RS_IDLE;
2174 }
2175 break;
2176 } else {
2177 goto unknown_command;
2178 }
edgar_igl7d03f822008-05-17 18:58:29 +00002179 case 'k':
Jan Kiszka00e94db2012-03-06 18:32:35 +01002180#ifdef CONFIG_USER_ONLY
edgar_igl7d03f822008-05-17 18:58:29 +00002181 /* Kill the target */
2182 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
2183 exit(0);
Jan Kiszka00e94db2012-03-06 18:32:35 +01002184#endif
edgar_igl7d03f822008-05-17 18:58:29 +00002185 case 'D':
2186 /* Detach packet */
aliguori880a7572008-11-18 20:30:24 +00002187 gdb_breakpoint_remove_all();
Daniel Gutson7ea06da2010-02-26 14:13:50 -03002188 gdb_syscall_mode = GDB_SYS_DISABLED;
edgar_igl7d03f822008-05-17 18:58:29 +00002189 gdb_continue(s);
2190 put_packet(s, "OK");
2191 break;
bellard858693c2004-03-31 18:52:07 +00002192 case 's':
2193 if (*p != '\0') {
ths8fac5802007-07-12 10:05:07 +00002194 addr = strtoull(p, (char **)&p, 16);
aurel32fab9d282009-04-08 21:29:37 +00002195 gdb_set_cpu_pc(s, addr);
bellard858693c2004-03-31 18:52:07 +00002196 }
aliguori880a7572008-11-18 20:30:24 +00002197 cpu_single_step(s->c_cpu, sstep_flags);
edgar_iglba70a622008-03-14 06:10:42 +00002198 gdb_continue(s);
bellard41625032005-04-24 10:07:11 +00002199 return RS_IDLE;
pbrooka2d1eba2007-01-28 03:10:55 +00002200 case 'F':
2201 {
2202 target_ulong ret;
2203 target_ulong err;
2204
2205 ret = strtoull(p, (char **)&p, 16);
2206 if (*p == ',') {
2207 p++;
2208 err = strtoull(p, (char **)&p, 16);
2209 } else {
2210 err = 0;
2211 }
2212 if (*p == ',')
2213 p++;
2214 type = *p;
Meador Ingecdb432b2012-03-15 17:49:45 +00002215 if (s->current_syscall_cb) {
2216 s->current_syscall_cb(s->c_cpu, ret, err);
2217 s->current_syscall_cb = NULL;
2218 }
pbrooka2d1eba2007-01-28 03:10:55 +00002219 if (type == 'C') {
2220 put_packet(s, "T02");
2221 } else {
edgar_iglba70a622008-03-14 06:10:42 +00002222 gdb_continue(s);
pbrooka2d1eba2007-01-28 03:10:55 +00002223 }
2224 }
2225 break;
bellard858693c2004-03-31 18:52:07 +00002226 case 'g':
Avi Kivity4c0960c2009-08-17 23:19:53 +03002227 cpu_synchronize_state(s->g_cpu);
Max Filippovccfcaba2011-09-06 03:55:52 +04002228 env = s->g_cpu;
pbrook56aebc82008-10-11 17:55:29 +00002229 len = 0;
2230 for (addr = 0; addr < num_g_regs; addr++) {
aliguori880a7572008-11-18 20:30:24 +00002231 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
pbrook56aebc82008-10-11 17:55:29 +00002232 len += reg_size;
2233 }
2234 memtohex(buf, mem_buf, len);
bellard858693c2004-03-31 18:52:07 +00002235 put_packet(s, buf);
2236 break;
2237 case 'G':
Avi Kivity4c0960c2009-08-17 23:19:53 +03002238 cpu_synchronize_state(s->g_cpu);
Max Filippovccfcaba2011-09-06 03:55:52 +04002239 env = s->g_cpu;
pbrook56aebc82008-10-11 17:55:29 +00002240 registers = mem_buf;
bellard858693c2004-03-31 18:52:07 +00002241 len = strlen(p) / 2;
2242 hextomem((uint8_t *)registers, p, len);
pbrook56aebc82008-10-11 17:55:29 +00002243 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
aliguori880a7572008-11-18 20:30:24 +00002244 reg_size = gdb_write_register(s->g_cpu, registers, addr);
pbrook56aebc82008-10-11 17:55:29 +00002245 len -= reg_size;
2246 registers += reg_size;
2247 }
bellard858693c2004-03-31 18:52:07 +00002248 put_packet(s, "OK");
2249 break;
2250 case 'm':
bellard9d9754a2006-06-25 15:32:37 +00002251 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00002252 if (*p == ',')
2253 p++;
bellard9d9754a2006-06-25 15:32:37 +00002254 len = strtoull(p, NULL, 16);
Fabien Chouteau44520db2011-09-08 12:48:16 +02002255 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
bellard6f970bd2005-12-05 19:55:19 +00002256 put_packet (s, "E14");
2257 } else {
2258 memtohex(buf, mem_buf, len);
2259 put_packet(s, buf);
2260 }
bellard858693c2004-03-31 18:52:07 +00002261 break;
2262 case 'M':
bellard9d9754a2006-06-25 15:32:37 +00002263 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00002264 if (*p == ',')
2265 p++;
bellard9d9754a2006-06-25 15:32:37 +00002266 len = strtoull(p, (char **)&p, 16);
bellardb328f872005-01-17 22:03:16 +00002267 if (*p == ':')
bellard858693c2004-03-31 18:52:07 +00002268 p++;
2269 hextomem(mem_buf, p, len);
Fabien Chouteau44520db2011-09-08 12:48:16 +02002270 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
bellard905f20b2005-04-26 21:09:55 +00002271 put_packet(s, "E14");
Fabien Chouteau44520db2011-09-08 12:48:16 +02002272 } else {
bellard858693c2004-03-31 18:52:07 +00002273 put_packet(s, "OK");
Fabien Chouteau44520db2011-09-08 12:48:16 +02002274 }
bellard858693c2004-03-31 18:52:07 +00002275 break;
pbrook56aebc82008-10-11 17:55:29 +00002276 case 'p':
2277 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2278 This works, but can be very slow. Anything new enough to
2279 understand XML also knows how to use this properly. */
2280 if (!gdb_has_xml)
2281 goto unknown_command;
2282 addr = strtoull(p, (char **)&p, 16);
aliguori880a7572008-11-18 20:30:24 +00002283 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
pbrook56aebc82008-10-11 17:55:29 +00002284 if (reg_size) {
2285 memtohex(buf, mem_buf, reg_size);
2286 put_packet(s, buf);
2287 } else {
2288 put_packet(s, "E14");
2289 }
2290 break;
2291 case 'P':
2292 if (!gdb_has_xml)
2293 goto unknown_command;
2294 addr = strtoull(p, (char **)&p, 16);
2295 if (*p == '=')
2296 p++;
2297 reg_size = strlen(p) / 2;
2298 hextomem(mem_buf, p, reg_size);
aliguori880a7572008-11-18 20:30:24 +00002299 gdb_write_register(s->g_cpu, mem_buf, addr);
pbrook56aebc82008-10-11 17:55:29 +00002300 put_packet(s, "OK");
2301 break;
bellard858693c2004-03-31 18:52:07 +00002302 case 'Z':
bellard858693c2004-03-31 18:52:07 +00002303 case 'z':
2304 type = strtoul(p, (char **)&p, 16);
2305 if (*p == ',')
2306 p++;
bellard9d9754a2006-06-25 15:32:37 +00002307 addr = strtoull(p, (char **)&p, 16);
bellard858693c2004-03-31 18:52:07 +00002308 if (*p == ',')
2309 p++;
bellard9d9754a2006-06-25 15:32:37 +00002310 len = strtoull(p, (char **)&p, 16);
aliguoria1d1bb32008-11-18 20:07:32 +00002311 if (ch == 'Z')
aliguori880a7572008-11-18 20:30:24 +00002312 res = gdb_breakpoint_insert(addr, len, type);
aliguoria1d1bb32008-11-18 20:07:32 +00002313 else
aliguori880a7572008-11-18 20:30:24 +00002314 res = gdb_breakpoint_remove(addr, len, type);
aliguoria1d1bb32008-11-18 20:07:32 +00002315 if (res >= 0)
2316 put_packet(s, "OK");
2317 else if (res == -ENOSYS)
pbrook0f459d12008-06-09 00:20:13 +00002318 put_packet(s, "");
aliguoria1d1bb32008-11-18 20:07:32 +00002319 else
2320 put_packet(s, "E22");
bellard858693c2004-03-31 18:52:07 +00002321 break;
aliguori880a7572008-11-18 20:30:24 +00002322 case 'H':
2323 type = *p++;
2324 thread = strtoull(p, (char **)&p, 16);
2325 if (thread == -1 || thread == 0) {
2326 put_packet(s, "OK");
2327 break;
2328 }
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002329 env = find_cpu(thread);
aliguori880a7572008-11-18 20:30:24 +00002330 if (env == NULL) {
2331 put_packet(s, "E22");
2332 break;
2333 }
2334 switch (type) {
2335 case 'c':
2336 s->c_cpu = env;
2337 put_packet(s, "OK");
2338 break;
2339 case 'g':
2340 s->g_cpu = env;
2341 put_packet(s, "OK");
2342 break;
2343 default:
2344 put_packet(s, "E22");
2345 break;
2346 }
2347 break;
2348 case 'T':
2349 thread = strtoull(p, (char **)&p, 16);
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002350 env = find_cpu(thread);
2351
2352 if (env != NULL) {
2353 put_packet(s, "OK");
2354 } else {
aliguori880a7572008-11-18 20:30:24 +00002355 put_packet(s, "E22");
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002356 }
aliguori880a7572008-11-18 20:30:24 +00002357 break;
pbrook978efd62006-06-17 18:30:42 +00002358 case 'q':
edgar_igl60897d32008-05-09 08:25:14 +00002359 case 'Q':
2360 /* parse any 'q' packets here */
2361 if (!strcmp(p,"qemu.sstepbits")) {
2362 /* Query Breakpoint bit definitions */
blueswir1363a37d2008-08-21 17:58:08 +00002363 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2364 SSTEP_ENABLE,
2365 SSTEP_NOIRQ,
2366 SSTEP_NOTIMER);
edgar_igl60897d32008-05-09 08:25:14 +00002367 put_packet(s, buf);
2368 break;
2369 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2370 /* Display or change the sstep_flags */
2371 p += 10;
2372 if (*p != '=') {
2373 /* Display current setting */
blueswir1363a37d2008-08-21 17:58:08 +00002374 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
edgar_igl60897d32008-05-09 08:25:14 +00002375 put_packet(s, buf);
2376 break;
2377 }
2378 p++;
2379 type = strtoul(p, (char **)&p, 16);
2380 sstep_flags = type;
2381 put_packet(s, "OK");
2382 break;
aliguori880a7572008-11-18 20:30:24 +00002383 } else if (strcmp(p,"C") == 0) {
2384 /* "Current thread" remains vague in the spec, so always return
2385 * the first CPU (gdb returns the first thread). */
2386 put_packet(s, "QC1");
2387 break;
2388 } else if (strcmp(p,"fThreadInfo") == 0) {
2389 s->query_cpu = first_cpu;
2390 goto report_cpuinfo;
2391 } else if (strcmp(p,"sThreadInfo") == 0) {
2392 report_cpuinfo:
2393 if (s->query_cpu) {
Wen Congyang68f47302012-05-07 12:10:05 +08002394 snprintf(buf, sizeof(buf), "m%x", cpu_index(s->query_cpu));
aliguori880a7572008-11-18 20:30:24 +00002395 put_packet(s, buf);
2396 s->query_cpu = s->query_cpu->next_cpu;
2397 } else
2398 put_packet(s, "l");
2399 break;
2400 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2401 thread = strtoull(p+16, (char **)&p, 16);
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002402 env = find_cpu(thread);
2403 if (env != NULL) {
Andreas Färber55e5c282012-12-17 06:18:02 +01002404 CPUState *cpu = ENV_GET_CPU(env);
Avi Kivity4c0960c2009-08-17 23:19:53 +03002405 cpu_synchronize_state(env);
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002406 len = snprintf((char *)mem_buf, sizeof(mem_buf),
Andreas Färber55e5c282012-12-17 06:18:02 +01002407 "CPU#%d [%s]", cpu->cpu_index,
Nathan Froyd1e9fa732009-06-03 11:33:08 -07002408 env->halted ? "halted " : "running");
2409 memtohex(buf, mem_buf, len);
2410 put_packet(s, buf);
2411 }
aliguori880a7572008-11-18 20:30:24 +00002412 break;
edgar_igl60897d32008-05-09 08:25:14 +00002413 }
blueswir10b8a9882009-03-07 10:51:36 +00002414#ifdef CONFIG_USER_ONLY
edgar_igl60897d32008-05-09 08:25:14 +00002415 else if (strncmp(p, "Offsets", 7) == 0) {
aliguori880a7572008-11-18 20:30:24 +00002416 TaskState *ts = s->c_cpu->opaque;
pbrook978efd62006-06-17 18:30:42 +00002417
blueswir1363a37d2008-08-21 17:58:08 +00002418 snprintf(buf, sizeof(buf),
2419 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2420 ";Bss=" TARGET_ABI_FMT_lx,
2421 ts->info->code_offset,
2422 ts->info->data_offset,
2423 ts->info->data_offset);
pbrook978efd62006-06-17 18:30:42 +00002424 put_packet(s, buf);
2425 break;
2426 }
blueswir10b8a9882009-03-07 10:51:36 +00002427#else /* !CONFIG_USER_ONLY */
aliguori8a34a0f2009-03-05 23:01:55 +00002428 else if (strncmp(p, "Rcmd,", 5) == 0) {
2429 int len = strlen(p + 5);
2430
2431 if ((len % 2) != 0) {
2432 put_packet(s, "E01");
2433 break;
2434 }
2435 hextomem(mem_buf, p + 5, len);
2436 len = len / 2;
2437 mem_buf[len++] = 0;
Anthony Liguorifa5efcc2011-08-15 11:17:30 -05002438 qemu_chr_be_write(s->mon_chr, mem_buf, len);
aliguori8a34a0f2009-03-05 23:01:55 +00002439 put_packet(s, "OK");
2440 break;
2441 }
blueswir10b8a9882009-03-07 10:51:36 +00002442#endif /* !CONFIG_USER_ONLY */
pbrook56aebc82008-10-11 17:55:29 +00002443 if (strncmp(p, "Supported", 9) == 0) {
blueswir15b3715b2008-10-25 11:18:12 +00002444 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
pbrook56aebc82008-10-11 17:55:29 +00002445#ifdef GDB_CORE_XML
blueswir12dc766d2009-04-13 16:06:19 +00002446 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
pbrook56aebc82008-10-11 17:55:29 +00002447#endif
2448 put_packet(s, buf);
2449 break;
2450 }
2451#ifdef GDB_CORE_XML
2452 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2453 const char *xml;
2454 target_ulong total_len;
2455
2456 gdb_has_xml = 1;
2457 p += 19;
aliguori880a7572008-11-18 20:30:24 +00002458 xml = get_feature_xml(p, &p);
pbrook56aebc82008-10-11 17:55:29 +00002459 if (!xml) {
blueswir15b3715b2008-10-25 11:18:12 +00002460 snprintf(buf, sizeof(buf), "E00");
pbrook56aebc82008-10-11 17:55:29 +00002461 put_packet(s, buf);
2462 break;
2463 }
2464
2465 if (*p == ':')
2466 p++;
2467 addr = strtoul(p, (char **)&p, 16);
2468 if (*p == ',')
2469 p++;
2470 len = strtoul(p, (char **)&p, 16);
2471
2472 total_len = strlen(xml);
2473 if (addr > total_len) {
blueswir15b3715b2008-10-25 11:18:12 +00002474 snprintf(buf, sizeof(buf), "E00");
pbrook56aebc82008-10-11 17:55:29 +00002475 put_packet(s, buf);
2476 break;
2477 }
2478 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2479 len = (MAX_PACKET_LENGTH - 5) / 2;
2480 if (len < total_len - addr) {
2481 buf[0] = 'm';
2482 len = memtox(buf + 1, xml + addr, len);
2483 } else {
2484 buf[0] = 'l';
2485 len = memtox(buf + 1, xml + addr, total_len - addr);
2486 }
2487 put_packet_binary(s, buf, len + 1);
2488 break;
2489 }
2490#endif
2491 /* Unrecognised 'q' command. */
2492 goto unknown_command;
2493
bellard858693c2004-03-31 18:52:07 +00002494 default:
pbrook56aebc82008-10-11 17:55:29 +00002495 unknown_command:
bellard858693c2004-03-31 18:52:07 +00002496 /* put empty packet */
2497 buf[0] = '\0';
2498 put_packet(s, buf);
2499 break;
2500 }
2501 return RS_IDLE;
2502}
2503
Andreas Färber9349b4f2012-03-14 01:38:32 +01002504void gdb_set_stop_cpu(CPUArchState *env)
aliguori880a7572008-11-18 20:30:24 +00002505{
2506 gdbserver_state->c_cpu = env;
2507 gdbserver_state->g_cpu = env;
2508}
2509
bellard1fddef42005-04-17 19:16:13 +00002510#ifndef CONFIG_USER_ONLY
Luiz Capitulino1dfb4dd2011-07-29 14:26:33 -03002511static void gdb_vm_state_change(void *opaque, int running, RunState state)
bellard858693c2004-03-31 18:52:07 +00002512{
aliguori880a7572008-11-18 20:30:24 +00002513 GDBState *s = gdbserver_state;
Andreas Färber9349b4f2012-03-14 01:38:32 +01002514 CPUArchState *env = s->c_cpu;
bellard858693c2004-03-31 18:52:07 +00002515 char buf[256];
aliguorid6fc1b32008-11-18 19:55:44 +00002516 const char *type;
bellard858693c2004-03-31 18:52:07 +00002517 int ret;
2518
Meador Ingecdb432b2012-03-15 17:49:45 +00002519 if (running || s->state == RS_INACTIVE) {
2520 return;
2521 }
2522 /* Is there a GDB syscall waiting to be sent? */
2523 if (s->current_syscall_cb) {
2524 put_packet(s, s->syscall_buf);
pbrooka2d1eba2007-01-28 03:10:55 +00002525 return;
Jan Kiszkae07bbac2011-02-09 16:29:40 +01002526 }
Luiz Capitulino1dfb4dd2011-07-29 14:26:33 -03002527 switch (state) {
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002528 case RUN_STATE_DEBUG:
aliguori880a7572008-11-18 20:30:24 +00002529 if (env->watchpoint_hit) {
2530 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
aliguoria1d1bb32008-11-18 20:07:32 +00002531 case BP_MEM_READ:
aliguorid6fc1b32008-11-18 19:55:44 +00002532 type = "r";
2533 break;
aliguoria1d1bb32008-11-18 20:07:32 +00002534 case BP_MEM_ACCESS:
aliguorid6fc1b32008-11-18 19:55:44 +00002535 type = "a";
2536 break;
2537 default:
2538 type = "";
2539 break;
2540 }
aliguori880a7572008-11-18 20:30:24 +00002541 snprintf(buf, sizeof(buf),
2542 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
Wen Congyang68f47302012-05-07 12:10:05 +08002543 GDB_SIGNAL_TRAP, cpu_index(env), type,
aliguori880a7572008-11-18 20:30:24 +00002544 env->watchpoint_hit->vaddr);
aliguori880a7572008-11-18 20:30:24 +00002545 env->watchpoint_hit = NULL;
Jan Kiszka425189a2011-03-22 11:02:09 +01002546 goto send_packet;
pbrook6658ffb2007-03-16 23:58:11 +00002547 }
Jan Kiszka425189a2011-03-22 11:02:09 +01002548 tb_flush(env);
aurel32ca587a82008-12-18 22:44:13 +00002549 ret = GDB_SIGNAL_TRAP;
Jan Kiszka425189a2011-03-22 11:02:09 +01002550 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002551 case RUN_STATE_PAUSED:
aliguori9781e042009-01-22 17:15:29 +00002552 ret = GDB_SIGNAL_INT;
Jan Kiszka425189a2011-03-22 11:02:09 +01002553 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002554 case RUN_STATE_SHUTDOWN:
Jan Kiszka425189a2011-03-22 11:02:09 +01002555 ret = GDB_SIGNAL_QUIT;
2556 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002557 case RUN_STATE_IO_ERROR:
Jan Kiszka425189a2011-03-22 11:02:09 +01002558 ret = GDB_SIGNAL_IO;
2559 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002560 case RUN_STATE_WATCHDOG:
Jan Kiszka425189a2011-03-22 11:02:09 +01002561 ret = GDB_SIGNAL_ALRM;
2562 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002563 case RUN_STATE_INTERNAL_ERROR:
Jan Kiszka425189a2011-03-22 11:02:09 +01002564 ret = GDB_SIGNAL_ABRT;
2565 break;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002566 case RUN_STATE_SAVE_VM:
2567 case RUN_STATE_RESTORE_VM:
Jan Kiszka425189a2011-03-22 11:02:09 +01002568 return;
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002569 case RUN_STATE_FINISH_MIGRATE:
Jan Kiszka425189a2011-03-22 11:02:09 +01002570 ret = GDB_SIGNAL_XCPU;
2571 break;
2572 default:
2573 ret = GDB_SIGNAL_UNKNOWN;
2574 break;
bellardbbeb7b52006-04-23 18:42:15 +00002575 }
Wen Congyang68f47302012-05-07 12:10:05 +08002576 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, cpu_index(env));
Jan Kiszka425189a2011-03-22 11:02:09 +01002577
2578send_packet:
bellard858693c2004-03-31 18:52:07 +00002579 put_packet(s, buf);
Jan Kiszka425189a2011-03-22 11:02:09 +01002580
2581 /* disable single step if it was enabled */
2582 cpu_single_step(env, 0);
bellard858693c2004-03-31 18:52:07 +00002583}
bellard1fddef42005-04-17 19:16:13 +00002584#endif
bellard858693c2004-03-31 18:52:07 +00002585
pbrooka2d1eba2007-01-28 03:10:55 +00002586/* Send a gdb syscall request.
2587 This accepts limited printf-style format specifiers, specifically:
pbrooka87295e2007-05-26 15:09:38 +00002588 %x - target_ulong argument printed in hex.
2589 %lx - 64-bit argument printed in hex.
2590 %s - string pointer (target_ulong) and length (int) pair. */
blueswir17ccfb2e2008-09-14 06:45:34 +00002591void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
pbrooka2d1eba2007-01-28 03:10:55 +00002592{
2593 va_list va;
pbrooka2d1eba2007-01-28 03:10:55 +00002594 char *p;
Meador Ingecdb432b2012-03-15 17:49:45 +00002595 char *p_end;
pbrooka2d1eba2007-01-28 03:10:55 +00002596 target_ulong addr;
pbrooka87295e2007-05-26 15:09:38 +00002597 uint64_t i64;
pbrooka2d1eba2007-01-28 03:10:55 +00002598 GDBState *s;
2599
aliguori880a7572008-11-18 20:30:24 +00002600 s = gdbserver_state;
pbrooka2d1eba2007-01-28 03:10:55 +00002601 if (!s)
2602 return;
Meador Ingecdb432b2012-03-15 17:49:45 +00002603 s->current_syscall_cb = cb;
pbrooka2d1eba2007-01-28 03:10:55 +00002604#ifndef CONFIG_USER_ONLY
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002605 vm_stop(RUN_STATE_DEBUG);
pbrooka2d1eba2007-01-28 03:10:55 +00002606#endif
pbrooka2d1eba2007-01-28 03:10:55 +00002607 va_start(va, fmt);
Meador Ingecdb432b2012-03-15 17:49:45 +00002608 p = s->syscall_buf;
2609 p_end = &s->syscall_buf[sizeof(s->syscall_buf)];
pbrooka2d1eba2007-01-28 03:10:55 +00002610 *(p++) = 'F';
2611 while (*fmt) {
2612 if (*fmt == '%') {
2613 fmt++;
2614 switch (*fmt++) {
2615 case 'x':
2616 addr = va_arg(va, target_ulong);
Meador Ingecdb432b2012-03-15 17:49:45 +00002617 p += snprintf(p, p_end - p, TARGET_FMT_lx, addr);
pbrooka2d1eba2007-01-28 03:10:55 +00002618 break;
pbrooka87295e2007-05-26 15:09:38 +00002619 case 'l':
2620 if (*(fmt++) != 'x')
2621 goto bad_format;
2622 i64 = va_arg(va, uint64_t);
Meador Ingecdb432b2012-03-15 17:49:45 +00002623 p += snprintf(p, p_end - p, "%" PRIx64, i64);
pbrooka87295e2007-05-26 15:09:38 +00002624 break;
pbrooka2d1eba2007-01-28 03:10:55 +00002625 case 's':
2626 addr = va_arg(va, target_ulong);
Meador Ingecdb432b2012-03-15 17:49:45 +00002627 p += snprintf(p, p_end - p, TARGET_FMT_lx "/%x",
blueswir1363a37d2008-08-21 17:58:08 +00002628 addr, va_arg(va, int));
pbrooka2d1eba2007-01-28 03:10:55 +00002629 break;
2630 default:
pbrooka87295e2007-05-26 15:09:38 +00002631 bad_format:
pbrooka2d1eba2007-01-28 03:10:55 +00002632 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2633 fmt - 1);
2634 break;
2635 }
2636 } else {
2637 *(p++) = *(fmt++);
2638 }
2639 }
pbrook8a93e022007-08-06 13:19:15 +00002640 *p = 0;
pbrooka2d1eba2007-01-28 03:10:55 +00002641 va_end(va);
pbrooka2d1eba2007-01-28 03:10:55 +00002642#ifdef CONFIG_USER_ONLY
Meador Ingecdb432b2012-03-15 17:49:45 +00002643 put_packet(s, s->syscall_buf);
aliguori880a7572008-11-18 20:30:24 +00002644 gdb_handlesig(s->c_cpu, 0);
pbrooka2d1eba2007-01-28 03:10:55 +00002645#else
Meador Ingecdb432b2012-03-15 17:49:45 +00002646 /* In this case wait to send the syscall packet until notification that
2647 the CPU has stopped. This must be done because if the packet is sent
2648 now the reply from the syscall request could be received while the CPU
2649 is still in the running state, which can cause packets to be dropped
2650 and state transition 'T' packets to be sent while the syscall is still
2651 being processed. */
aurel323098dba2009-03-07 21:28:24 +00002652 cpu_exit(s->c_cpu);
pbrooka2d1eba2007-01-28 03:10:55 +00002653#endif
2654}
2655
bellard6a00d602005-11-21 23:25:50 +00002656static void gdb_read_byte(GDBState *s, int ch)
bellard858693c2004-03-31 18:52:07 +00002657{
2658 int i, csum;
ths60fe76f2007-12-16 03:02:09 +00002659 uint8_t reply;
bellard858693c2004-03-31 18:52:07 +00002660
bellard1fddef42005-04-17 19:16:13 +00002661#ifndef CONFIG_USER_ONLY
pbrook4046d912007-01-28 01:53:16 +00002662 if (s->last_packet_len) {
2663 /* Waiting for a response to the last packet. If we see the start
2664 of a new command then abandon the previous response. */
2665 if (ch == '-') {
2666#ifdef DEBUG_GDB
2667 printf("Got NACK, retransmitting\n");
2668#endif
thsffe8ab82007-12-16 03:16:05 +00002669 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
pbrook4046d912007-01-28 01:53:16 +00002670 }
2671#ifdef DEBUG_GDB
2672 else if (ch == '+')
2673 printf("Got ACK\n");
2674 else
2675 printf("Got '%c' when expecting ACK/NACK\n", ch);
2676#endif
2677 if (ch == '+' || ch == '$')
2678 s->last_packet_len = 0;
2679 if (ch != '$')
2680 return;
2681 }
Luiz Capitulino13548692011-07-29 15:36:43 -03002682 if (runstate_is_running()) {
bellard858693c2004-03-31 18:52:07 +00002683 /* when the CPU is running, we cannot do anything except stop
2684 it when receiving a char */
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002685 vm_stop(RUN_STATE_PAUSED);
ths5fafdf22007-09-16 21:08:06 +00002686 } else
bellard1fddef42005-04-17 19:16:13 +00002687#endif
bellard41625032005-04-24 10:07:11 +00002688 {
bellard858693c2004-03-31 18:52:07 +00002689 switch(s->state) {
2690 case RS_IDLE:
2691 if (ch == '$') {
2692 s->line_buf_index = 0;
2693 s->state = RS_GETLINE;
bellard4c3a88a2003-07-26 12:06:08 +00002694 }
2695 break;
bellard858693c2004-03-31 18:52:07 +00002696 case RS_GETLINE:
2697 if (ch == '#') {
2698 s->state = RS_CHKSUM1;
2699 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2700 s->state = RS_IDLE;
2701 } else {
2702 s->line_buf[s->line_buf_index++] = ch;
2703 }
2704 break;
2705 case RS_CHKSUM1:
2706 s->line_buf[s->line_buf_index] = '\0';
2707 s->line_csum = fromhex(ch) << 4;
2708 s->state = RS_CHKSUM2;
2709 break;
2710 case RS_CHKSUM2:
2711 s->line_csum |= fromhex(ch);
2712 csum = 0;
2713 for(i = 0; i < s->line_buf_index; i++) {
2714 csum += s->line_buf[i];
2715 }
2716 if (s->line_csum != (csum & 0xff)) {
ths60fe76f2007-12-16 03:02:09 +00002717 reply = '-';
2718 put_buffer(s, &reply, 1);
bellard858693c2004-03-31 18:52:07 +00002719 s->state = RS_IDLE;
2720 } else {
ths60fe76f2007-12-16 03:02:09 +00002721 reply = '+';
2722 put_buffer(s, &reply, 1);
aliguori880a7572008-11-18 20:30:24 +00002723 s->state = gdb_handle_packet(s, s->line_buf);
bellard858693c2004-03-31 18:52:07 +00002724 }
bellardb4608c02003-06-27 17:34:32 +00002725 break;
pbrooka2d1eba2007-01-28 03:10:55 +00002726 default:
2727 abort();
bellardb4608c02003-06-27 17:34:32 +00002728 }
2729 }
bellard858693c2004-03-31 18:52:07 +00002730}
2731
Paul Brook0e1c9c52010-06-16 13:03:51 +01002732/* Tell the remote gdb that the process has exited. */
Andreas Färber9349b4f2012-03-14 01:38:32 +01002733void gdb_exit(CPUArchState *env, int code)
Paul Brook0e1c9c52010-06-16 13:03:51 +01002734{
2735 GDBState *s;
2736 char buf[4];
2737
2738 s = gdbserver_state;
2739 if (!s) {
2740 return;
2741 }
2742#ifdef CONFIG_USER_ONLY
2743 if (gdbserver_fd < 0 || s->fd < 0) {
2744 return;
2745 }
2746#endif
2747
2748 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2749 put_packet(s, buf);
Fabien Chouteaue2af15b2011-01-13 12:46:57 +01002750
2751#ifndef CONFIG_USER_ONLY
2752 if (s->chr) {
Anthony Liguori70f24fb2011-08-15 11:17:38 -05002753 qemu_chr_delete(s->chr);
Fabien Chouteaue2af15b2011-01-13 12:46:57 +01002754 }
2755#endif
Paul Brook0e1c9c52010-06-16 13:03:51 +01002756}
2757
bellard1fddef42005-04-17 19:16:13 +00002758#ifdef CONFIG_USER_ONLY
2759int
aurel32ca587a82008-12-18 22:44:13 +00002760gdb_queuesig (void)
2761{
2762 GDBState *s;
2763
2764 s = gdbserver_state;
2765
2766 if (gdbserver_fd < 0 || s->fd < 0)
2767 return 0;
2768 else
2769 return 1;
2770}
2771
2772int
Andreas Färber9349b4f2012-03-14 01:38:32 +01002773gdb_handlesig (CPUArchState *env, int sig)
bellard1fddef42005-04-17 19:16:13 +00002774{
2775 GDBState *s;
2776 char buf[256];
2777 int n;
2778
aliguori880a7572008-11-18 20:30:24 +00002779 s = gdbserver_state;
edgar_igl1f487ee2008-05-17 22:20:53 +00002780 if (gdbserver_fd < 0 || s->fd < 0)
2781 return sig;
bellard1fddef42005-04-17 19:16:13 +00002782
2783 /* disable single step if it was enabled */
2784 cpu_single_step(env, 0);
2785 tb_flush(env);
2786
2787 if (sig != 0)
2788 {
aurel32ca587a82008-12-18 22:44:13 +00002789 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
bellard1fddef42005-04-17 19:16:13 +00002790 put_packet(s, buf);
2791 }
edgar_igl1f487ee2008-05-17 22:20:53 +00002792 /* put_packet() might have detected that the peer terminated the
2793 connection. */
2794 if (s->fd < 0)
2795 return sig;
bellard1fddef42005-04-17 19:16:13 +00002796
bellard1fddef42005-04-17 19:16:13 +00002797 sig = 0;
2798 s->state = RS_IDLE;
bellard41625032005-04-24 10:07:11 +00002799 s->running_state = 0;
2800 while (s->running_state == 0) {
bellard1fddef42005-04-17 19:16:13 +00002801 n = read (s->fd, buf, 256);
2802 if (n > 0)
2803 {
2804 int i;
2805
2806 for (i = 0; i < n; i++)
bellard6a00d602005-11-21 23:25:50 +00002807 gdb_read_byte (s, buf[i]);
bellard1fddef42005-04-17 19:16:13 +00002808 }
2809 else if (n == 0 || errno != EAGAIN)
2810 {
Stefan Weile7d81002011-12-10 00:19:46 +01002811 /* XXX: Connection closed. Should probably wait for another
bellard1fddef42005-04-17 19:16:13 +00002812 connection before continuing. */
2813 return sig;
2814 }
bellard41625032005-04-24 10:07:11 +00002815 }
edgar_igl1f487ee2008-05-17 22:20:53 +00002816 sig = s->signal;
2817 s->signal = 0;
bellard1fddef42005-04-17 19:16:13 +00002818 return sig;
2819}
bellarde9009672005-04-26 20:42:36 +00002820
aurel32ca587a82008-12-18 22:44:13 +00002821/* Tell the remote gdb that the process has exited due to SIG. */
Andreas Färber9349b4f2012-03-14 01:38:32 +01002822void gdb_signalled(CPUArchState *env, int sig)
aurel32ca587a82008-12-18 22:44:13 +00002823{
2824 GDBState *s;
2825 char buf[4];
2826
2827 s = gdbserver_state;
2828 if (gdbserver_fd < 0 || s->fd < 0)
2829 return;
2830
2831 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2832 put_packet(s, buf);
2833}
bellard1fddef42005-04-17 19:16:13 +00002834
aliguori880a7572008-11-18 20:30:24 +00002835static void gdb_accept(void)
bellard858693c2004-03-31 18:52:07 +00002836{
2837 GDBState *s;
2838 struct sockaddr_in sockaddr;
2839 socklen_t len;
2840 int val, fd;
2841
2842 for(;;) {
2843 len = sizeof(sockaddr);
2844 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2845 if (fd < 0 && errno != EINTR) {
2846 perror("accept");
2847 return;
2848 } else if (fd >= 0) {
Kevin Wolf40ff6d72009-12-02 12:24:42 +01002849#ifndef _WIN32
2850 fcntl(fd, F_SETFD, FD_CLOEXEC);
2851#endif
bellard858693c2004-03-31 18:52:07 +00002852 break;
2853 }
2854 }
2855
2856 /* set short latency */
2857 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00002858 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
ths3b46e622007-09-17 08:09:54 +00002859
Anthony Liguori7267c092011-08-20 22:09:37 -05002860 s = g_malloc0(sizeof(GDBState));
aliguori880a7572008-11-18 20:30:24 +00002861 s->c_cpu = first_cpu;
2862 s->g_cpu = first_cpu;
bellard858693c2004-03-31 18:52:07 +00002863 s->fd = fd;
pbrook56aebc82008-10-11 17:55:29 +00002864 gdb_has_xml = 0;
bellard858693c2004-03-31 18:52:07 +00002865
aliguori880a7572008-11-18 20:30:24 +00002866 gdbserver_state = s;
pbrooka2d1eba2007-01-28 03:10:55 +00002867
bellard858693c2004-03-31 18:52:07 +00002868 fcntl(fd, F_SETFL, O_NONBLOCK);
bellard858693c2004-03-31 18:52:07 +00002869}
2870
2871static int gdbserver_open(int port)
2872{
2873 struct sockaddr_in sockaddr;
2874 int fd, val, ret;
2875
2876 fd = socket(PF_INET, SOCK_STREAM, 0);
2877 if (fd < 0) {
2878 perror("socket");
2879 return -1;
2880 }
Kevin Wolf40ff6d72009-12-02 12:24:42 +01002881#ifndef _WIN32
2882 fcntl(fd, F_SETFD, FD_CLOEXEC);
2883#endif
bellard858693c2004-03-31 18:52:07 +00002884
2885 /* allow fast reuse */
2886 val = 1;
bellard8f447cc2006-06-14 15:21:14 +00002887 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
bellard858693c2004-03-31 18:52:07 +00002888
2889 sockaddr.sin_family = AF_INET;
2890 sockaddr.sin_port = htons(port);
2891 sockaddr.sin_addr.s_addr = 0;
2892 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2893 if (ret < 0) {
2894 perror("bind");
Peter Maydellbb161722011-12-24 23:37:24 +00002895 close(fd);
bellard858693c2004-03-31 18:52:07 +00002896 return -1;
2897 }
2898 ret = listen(fd, 0);
2899 if (ret < 0) {
2900 perror("listen");
Peter Maydellbb161722011-12-24 23:37:24 +00002901 close(fd);
bellard858693c2004-03-31 18:52:07 +00002902 return -1;
2903 }
bellard858693c2004-03-31 18:52:07 +00002904 return fd;
2905}
2906
2907int gdbserver_start(int port)
2908{
2909 gdbserver_fd = gdbserver_open(port);
2910 if (gdbserver_fd < 0)
2911 return -1;
2912 /* accept connections */
aliguori880a7572008-11-18 20:30:24 +00002913 gdb_accept();
bellardb4608c02003-06-27 17:34:32 +00002914 return 0;
2915}
aurel322b1319c2008-12-18 22:44:04 +00002916
2917/* Disable gdb stub for child processes. */
Andreas Färber9349b4f2012-03-14 01:38:32 +01002918void gdbserver_fork(CPUArchState *env)
aurel322b1319c2008-12-18 22:44:04 +00002919{
2920 GDBState *s = gdbserver_state;
edgar_igl9f6164d2009-01-07 10:22:28 +00002921 if (gdbserver_fd < 0 || s->fd < 0)
aurel322b1319c2008-12-18 22:44:04 +00002922 return;
2923 close(s->fd);
2924 s->fd = -1;
2925 cpu_breakpoint_remove_all(env, BP_GDB);
2926 cpu_watchpoint_remove_all(env, BP_GDB);
2927}
pbrook4046d912007-01-28 01:53:16 +00002928#else
thsaa1f17c2007-07-11 22:48:58 +00002929static int gdb_chr_can_receive(void *opaque)
pbrook4046d912007-01-28 01:53:16 +00002930{
pbrook56aebc82008-10-11 17:55:29 +00002931 /* We can handle an arbitrarily large amount of data.
2932 Pick the maximum packet size, which is as good as anything. */
2933 return MAX_PACKET_LENGTH;
pbrook4046d912007-01-28 01:53:16 +00002934}
2935
thsaa1f17c2007-07-11 22:48:58 +00002936static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
pbrook4046d912007-01-28 01:53:16 +00002937{
pbrook4046d912007-01-28 01:53:16 +00002938 int i;
2939
2940 for (i = 0; i < size; i++) {
aliguori880a7572008-11-18 20:30:24 +00002941 gdb_read_byte(gdbserver_state, buf[i]);
pbrook4046d912007-01-28 01:53:16 +00002942 }
2943}
2944
2945static void gdb_chr_event(void *opaque, int event)
2946{
2947 switch (event) {
Amit Shahb6b8df52009-10-07 18:31:16 +05302948 case CHR_EVENT_OPENED:
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002949 vm_stop(RUN_STATE_PAUSED);
pbrook56aebc82008-10-11 17:55:29 +00002950 gdb_has_xml = 0;
pbrook4046d912007-01-28 01:53:16 +00002951 break;
2952 default:
2953 break;
2954 }
2955}
2956
aliguori8a34a0f2009-03-05 23:01:55 +00002957static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2958{
2959 char buf[MAX_PACKET_LENGTH];
2960
2961 buf[0] = 'O';
2962 if (len > (MAX_PACKET_LENGTH/2) - 1)
2963 len = (MAX_PACKET_LENGTH/2) - 1;
2964 memtohex(buf + 1, (uint8_t *)msg, len);
2965 put_packet(s, buf);
2966}
2967
2968static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2969{
2970 const char *p = (const char *)buf;
2971 int max_sz;
2972
2973 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2974 for (;;) {
2975 if (len <= max_sz) {
2976 gdb_monitor_output(gdbserver_state, p, len);
2977 break;
2978 }
2979 gdb_monitor_output(gdbserver_state, p, max_sz);
2980 p += max_sz;
2981 len -= max_sz;
2982 }
2983 return len;
2984}
2985
aliguori59030a82009-04-05 18:43:41 +00002986#ifndef _WIN32
2987static void gdb_sigterm_handler(int signal)
2988{
Luiz Capitulino13548692011-07-29 15:36:43 -03002989 if (runstate_is_running()) {
Luiz Capitulino0461d5a2011-09-30 14:45:27 -03002990 vm_stop(RUN_STATE_PAUSED);
Jan Kiszkae07bbac2011-02-09 16:29:40 +01002991 }
aliguori59030a82009-04-05 18:43:41 +00002992}
2993#endif
2994
2995int gdbserver_start(const char *device)
pbrook4046d912007-01-28 01:53:16 +00002996{
2997 GDBState *s;
aliguori59030a82009-04-05 18:43:41 +00002998 char gdbstub_device_name[128];
aliguori36556b22009-03-28 18:05:53 +00002999 CharDriverState *chr = NULL;
3000 CharDriverState *mon_chr;
pbrook4046d912007-01-28 01:53:16 +00003001
aliguori59030a82009-04-05 18:43:41 +00003002 if (!device)
3003 return -1;
3004 if (strcmp(device, "none") != 0) {
3005 if (strstart(device, "tcp:", NULL)) {
3006 /* enforce required TCP attributes */
3007 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
3008 "%s,nowait,nodelay,server", device);
3009 device = gdbstub_device_name;
aliguori36556b22009-03-28 18:05:53 +00003010 }
aliguori59030a82009-04-05 18:43:41 +00003011#ifndef _WIN32
3012 else if (strcmp(device, "stdio") == 0) {
3013 struct sigaction act;
pbrookcfc34752007-02-22 01:48:01 +00003014
aliguori59030a82009-04-05 18:43:41 +00003015 memset(&act, 0, sizeof(act));
3016 act.sa_handler = gdb_sigterm_handler;
3017 sigaction(SIGINT, &act, NULL);
3018 }
3019#endif
Anthony Liguori27143a42011-08-15 11:17:36 -05003020 chr = qemu_chr_new("gdb", device, NULL);
aliguori36556b22009-03-28 18:05:53 +00003021 if (!chr)
3022 return -1;
3023
3024 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
3025 gdb_chr_event, NULL);
pbrookcfc34752007-02-22 01:48:01 +00003026 }
3027
aliguori36556b22009-03-28 18:05:53 +00003028 s = gdbserver_state;
3029 if (!s) {
Anthony Liguori7267c092011-08-20 22:09:37 -05003030 s = g_malloc0(sizeof(GDBState));
aliguori36556b22009-03-28 18:05:53 +00003031 gdbserver_state = s;
pbrook4046d912007-01-28 01:53:16 +00003032
aliguori36556b22009-03-28 18:05:53 +00003033 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
3034
3035 /* Initialize a monitor terminal for gdb */
Anthony Liguori7267c092011-08-20 22:09:37 -05003036 mon_chr = g_malloc0(sizeof(*mon_chr));
aliguori36556b22009-03-28 18:05:53 +00003037 mon_chr->chr_write = gdb_monitor_write;
3038 monitor_init(mon_chr, 0);
3039 } else {
3040 if (s->chr)
Anthony Liguori70f24fb2011-08-15 11:17:38 -05003041 qemu_chr_delete(s->chr);
aliguori36556b22009-03-28 18:05:53 +00003042 mon_chr = s->mon_chr;
3043 memset(s, 0, sizeof(GDBState));
3044 }
aliguori880a7572008-11-18 20:30:24 +00003045 s->c_cpu = first_cpu;
3046 s->g_cpu = first_cpu;
pbrook4046d912007-01-28 01:53:16 +00003047 s->chr = chr;
aliguori36556b22009-03-28 18:05:53 +00003048 s->state = chr ? RS_IDLE : RS_INACTIVE;
3049 s->mon_chr = mon_chr;
Meador Ingecdb432b2012-03-15 17:49:45 +00003050 s->current_syscall_cb = NULL;
aliguori8a34a0f2009-03-05 23:01:55 +00003051
pbrook4046d912007-01-28 01:53:16 +00003052 return 0;
3053}
3054#endif