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bellardb92e5a22003-08-08 23:58:05 +00001/*
2 * Software MMU support
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define DATA_SIZE (1 << SHIFT)
21
22#if DATA_SIZE == 8
23#define SUFFIX q
bellard61382a52003-10-27 21:22:23 +000024#define USUFFIX q
bellardb92e5a22003-08-08 23:58:05 +000025#define DATA_TYPE uint64_t
26#elif DATA_SIZE == 4
27#define SUFFIX l
bellard61382a52003-10-27 21:22:23 +000028#define USUFFIX l
bellardb92e5a22003-08-08 23:58:05 +000029#define DATA_TYPE uint32_t
30#elif DATA_SIZE == 2
31#define SUFFIX w
bellard61382a52003-10-27 21:22:23 +000032#define USUFFIX uw
bellardb92e5a22003-08-08 23:58:05 +000033#define DATA_TYPE uint16_t
34#elif DATA_SIZE == 1
35#define SUFFIX b
bellard61382a52003-10-27 21:22:23 +000036#define USUFFIX ub
bellardb92e5a22003-08-08 23:58:05 +000037#define DATA_TYPE uint8_t
38#else
39#error unsupported data size
40#endif
41
bellardb769d8f2004-10-03 15:07:13 +000042#ifdef SOFTMMU_CODE_ACCESS
43#define READ_ACCESS_TYPE 2
44#else
45#define READ_ACCESS_TYPE 0
46#endif
47
bellardc27004e2005-01-03 23:35:10 +000048static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +000049 int is_user,
50 void *retaddr);
bellard108c49b2005-07-24 12:55:09 +000051static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
bellardc27004e2005-01-03 23:35:10 +000052 target_ulong tlb_addr)
bellardb92e5a22003-08-08 23:58:05 +000053{
54 DATA_TYPE res;
55 int index;
56
57 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
58#if SHIFT <= 2
bellarda4193c82004-06-03 14:01:43 +000059 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
bellardb92e5a22003-08-08 23:58:05 +000060#else
61#ifdef TARGET_WORDS_BIGENDIAN
bellarda4193c82004-06-03 14:01:43 +000062 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
63 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
bellardb92e5a22003-08-08 23:58:05 +000064#else
bellarda4193c82004-06-03 14:01:43 +000065 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
66 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
bellardb92e5a22003-08-08 23:58:05 +000067#endif
68#endif /* SHIFT > 2 */
69 return res;
70}
71
bellardb92e5a22003-08-08 23:58:05 +000072/* handle all cases except unaligned access which span two pages */
bellardc27004e2005-01-03 23:35:10 +000073DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +000074 int is_user)
bellardb92e5a22003-08-08 23:58:05 +000075{
76 DATA_TYPE res;
bellard61382a52003-10-27 21:22:23 +000077 int index;
bellardc27004e2005-01-03 23:35:10 +000078 target_ulong tlb_addr;
bellard108c49b2005-07-24 12:55:09 +000079 target_phys_addr_t physaddr;
bellardb92e5a22003-08-08 23:58:05 +000080 void *retaddr;
81
82 /* test if there is match for unaligned or IO access */
83 /* XXX: could done more in memory macro in a non portable way */
bellardb92e5a22003-08-08 23:58:05 +000084 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
85 redo:
86 tlb_addr = env->tlb_read[is_user][index].address;
87 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
88 physaddr = addr + env->tlb_read[is_user][index].addend;
89 if (tlb_addr & ~TARGET_PAGE_MASK) {
90 /* IO access */
91 if ((addr & (DATA_SIZE - 1)) != 0)
92 goto do_unaligned_access;
93 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
bellard98699962005-11-26 10:29:22 +000094 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +000095 /* slow unaligned access (it spans two pages or IO) */
96 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +000097 retaddr = GETPC();
98 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
99 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000100 } else {
101 /* unaligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000102 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
bellardb92e5a22003-08-08 23:58:05 +0000103 }
104 } else {
105 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000106 retaddr = GETPC();
bellardb769d8f2004-10-03 15:07:13 +0000107 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000108 goto redo;
109 }
110 return res;
111}
112
113/* handle all unaligned cases */
bellardc27004e2005-01-03 23:35:10 +0000114static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000115 int is_user,
116 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000117{
118 DATA_TYPE res, res1, res2;
bellard61382a52003-10-27 21:22:23 +0000119 int index, shift;
bellard108c49b2005-07-24 12:55:09 +0000120 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000121 target_ulong tlb_addr, addr1, addr2;
bellardb92e5a22003-08-08 23:58:05 +0000122
bellardb92e5a22003-08-08 23:58:05 +0000123 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
124 redo:
125 tlb_addr = env->tlb_read[is_user][index].address;
126 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
127 physaddr = addr + env->tlb_read[is_user][index].addend;
128 if (tlb_addr & ~TARGET_PAGE_MASK) {
129 /* IO access */
130 if ((addr & (DATA_SIZE - 1)) != 0)
131 goto do_unaligned_access;
132 res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
bellard98699962005-11-26 10:29:22 +0000133 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000134 do_unaligned_access:
135 /* slow unaligned access (it spans two pages) */
136 addr1 = addr & ~(DATA_SIZE - 1);
137 addr2 = addr1 + DATA_SIZE;
bellard61382a52003-10-27 21:22:23 +0000138 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
139 is_user, retaddr);
140 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
141 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000142 shift = (addr & (DATA_SIZE - 1)) * 8;
143#ifdef TARGET_WORDS_BIGENDIAN
144 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
145#else
146 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
147#endif
bellard6986f882004-01-18 21:53:18 +0000148 res = (DATA_TYPE)res;
bellardb92e5a22003-08-08 23:58:05 +0000149 } else {
150 /* unaligned/aligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000151 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
bellardb92e5a22003-08-08 23:58:05 +0000152 }
153 } else {
154 /* the page is not in the TLB : fill it */
bellardb769d8f2004-10-03 15:07:13 +0000155 tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000156 goto redo;
157 }
158 return res;
159}
160
bellardb769d8f2004-10-03 15:07:13 +0000161#ifndef SOFTMMU_CODE_ACCESS
162
bellardc27004e2005-01-03 23:35:10 +0000163static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellardb769d8f2004-10-03 15:07:13 +0000164 DATA_TYPE val,
165 int is_user,
166 void *retaddr);
167
bellard108c49b2005-07-24 12:55:09 +0000168static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
bellardb769d8f2004-10-03 15:07:13 +0000169 DATA_TYPE val,
bellardc27004e2005-01-03 23:35:10 +0000170 target_ulong tlb_addr,
bellardb769d8f2004-10-03 15:07:13 +0000171 void *retaddr)
172{
173 int index;
174
175 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
176 env->mem_write_vaddr = tlb_addr;
177 env->mem_write_pc = (unsigned long)retaddr;
178#if SHIFT <= 2
179 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
180#else
181#ifdef TARGET_WORDS_BIGENDIAN
182 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
183 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
184#else
185 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
186 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
187#endif
188#endif /* SHIFT > 2 */
189}
bellardb92e5a22003-08-08 23:58:05 +0000190
bellardc27004e2005-01-03 23:35:10 +0000191void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000192 DATA_TYPE val,
193 int is_user)
bellardb92e5a22003-08-08 23:58:05 +0000194{
bellard108c49b2005-07-24 12:55:09 +0000195 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000196 target_ulong tlb_addr;
bellardb92e5a22003-08-08 23:58:05 +0000197 void *retaddr;
bellard61382a52003-10-27 21:22:23 +0000198 int index;
bellardb92e5a22003-08-08 23:58:05 +0000199
bellardb92e5a22003-08-08 23:58:05 +0000200 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
201 redo:
202 tlb_addr = env->tlb_write[is_user][index].address;
203 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard4ad06a22003-11-09 16:58:12 +0000204 physaddr = addr + env->tlb_write[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000205 if (tlb_addr & ~TARGET_PAGE_MASK) {
206 /* IO access */
207 if ((addr & (DATA_SIZE - 1)) != 0)
208 goto do_unaligned_access;
bellardd720b932004-04-25 17:57:43 +0000209 retaddr = GETPC();
210 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000211 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000212 do_unaligned_access:
bellard61382a52003-10-27 21:22:23 +0000213 retaddr = GETPC();
214 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
215 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000216 } else {
217 /* aligned/unaligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000218 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
bellardb92e5a22003-08-08 23:58:05 +0000219 }
220 } else {
221 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000222 retaddr = GETPC();
223 tlb_fill(addr, 1, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000224 goto redo;
225 }
226}
227
228/* handles all unaligned cases */
bellardc27004e2005-01-03 23:35:10 +0000229static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
bellard61382a52003-10-27 21:22:23 +0000230 DATA_TYPE val,
231 int is_user,
232 void *retaddr)
bellardb92e5a22003-08-08 23:58:05 +0000233{
bellard108c49b2005-07-24 12:55:09 +0000234 target_phys_addr_t physaddr;
bellardc27004e2005-01-03 23:35:10 +0000235 target_ulong tlb_addr;
bellard61382a52003-10-27 21:22:23 +0000236 int index, i;
bellardb92e5a22003-08-08 23:58:05 +0000237
bellardb92e5a22003-08-08 23:58:05 +0000238 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
239 redo:
240 tlb_addr = env->tlb_write[is_user][index].address;
241 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
bellard4ad06a22003-11-09 16:58:12 +0000242 physaddr = addr + env->tlb_write[is_user][index].addend;
bellardb92e5a22003-08-08 23:58:05 +0000243 if (tlb_addr & ~TARGET_PAGE_MASK) {
244 /* IO access */
245 if ((addr & (DATA_SIZE - 1)) != 0)
246 goto do_unaligned_access;
bellardd720b932004-04-25 17:57:43 +0000247 glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
bellard98699962005-11-26 10:29:22 +0000248 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
bellardb92e5a22003-08-08 23:58:05 +0000249 do_unaligned_access:
250 /* XXX: not efficient, but simple */
251 for(i = 0;i < DATA_SIZE; i++) {
252#ifdef TARGET_WORDS_BIGENDIAN
bellard61382a52003-10-27 21:22:23 +0000253 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
254 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000255#else
bellard61382a52003-10-27 21:22:23 +0000256 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
257 is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000258#endif
259 }
260 } else {
261 /* aligned/unaligned access in the same page */
bellard108c49b2005-07-24 12:55:09 +0000262 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
bellardb92e5a22003-08-08 23:58:05 +0000263 }
264 } else {
265 /* the page is not in the TLB : fill it */
bellard61382a52003-10-27 21:22:23 +0000266 tlb_fill(addr, 1, is_user, retaddr);
bellardb92e5a22003-08-08 23:58:05 +0000267 goto redo;
268 }
269}
270
bellardb769d8f2004-10-03 15:07:13 +0000271#endif /* !defined(SOFTMMU_CODE_ACCESS) */
272
273#undef READ_ACCESS_TYPE
bellardb92e5a22003-08-08 23:58:05 +0000274#undef SHIFT
275#undef DATA_TYPE
276#undef SUFFIX
bellard61382a52003-10-27 21:22:23 +0000277#undef USUFFIX
bellardb92e5a22003-08-08 23:58:05 +0000278#undef DATA_SIZE