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bellard27503322003-11-13 01:46:15 +00001/*
2 * QEMU Soundblaster 16 emulation
3 *
bellard85571bc2004-11-07 18:04:02 +00004 * Copyright (c) 2003-2004 Vassili Karpov (malc)
bellard27503322003-11-13 01:46:15 +00005 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
bellard27503322003-11-13 01:46:15 +000024#include "vl.h"
25
bellard27503322003-11-13 01:46:15 +000026#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
27
bellardfb065182004-11-09 23:09:44 +000028#define dolog(...) AUD_log ("sb16", __VA_ARGS__)
bellard15b61472004-11-14 16:02:09 +000029
30/* #define DEBUG */
31/* #define DEBUG_SB16_MOST */
32
bellardfb065182004-11-09 23:09:44 +000033#ifdef DEBUG
34#define ldebug(...) dolog (__VA_ARGS__)
35#else
36#define ldebug(...)
37#endif
38
bellard85571bc2004-11-07 18:04:02 +000039#define IO_READ_PROTO(name) \
bellard7d977de2004-03-14 21:41:34 +000040 uint32_t name (void *opaque, uint32_t nport)
bellard85571bc2004-11-07 18:04:02 +000041#define IO_WRITE_PROTO(name) \
bellard7d977de2004-03-14 21:41:34 +000042 void name (void *opaque, uint32_t nport, uint32_t val)
bellard27503322003-11-13 01:46:15 +000043
bellard85571bc2004-11-07 18:04:02 +000044static const char e3[] = "COPYRIGHT (C) CREATIVE TECHNOLOGY LTD, 1992.";
bellardd329a6f2004-06-07 20:58:31 +000045
bellard27503322003-11-13 01:46:15 +000046static struct {
47 int ver_lo;
48 int ver_hi;
49 int irq;
50 int dma;
51 int hdma;
52 int port;
bellard85571bc2004-11-07 18:04:02 +000053} conf = {5, 4, 5, 1, 5, 0x220};
bellard27503322003-11-13 01:46:15 +000054
bellard5e2a6442004-03-23 22:42:11 +000055typedef struct SB16State {
bellard85571bc2004-11-07 18:04:02 +000056 int irq;
57 int dma;
58 int hdma;
59 int port;
60 int ver;
61
bellard27503322003-11-13 01:46:15 +000062 int in_index;
63 int out_data_len;
64 int fmt_stereo;
65 int fmt_signed;
66 int fmt_bits;
bellard85571bc2004-11-07 18:04:02 +000067 audfmt_e fmt;
bellard27503322003-11-13 01:46:15 +000068 int dma_auto;
bellard85571bc2004-11-07 18:04:02 +000069 int block_size;
bellard27503322003-11-13 01:46:15 +000070 int fifo;
71 int freq;
72 int time_const;
73 int speaker;
74 int needed_bytes;
75 int cmd;
bellard27503322003-11-13 01:46:15 +000076 int use_hdma;
bellard85571bc2004-11-07 18:04:02 +000077 int highspeed;
78 int can_write;
bellard27503322003-11-13 01:46:15 +000079
80 int v2x6;
81
bellard85571bc2004-11-07 18:04:02 +000082 uint8_t csp_param;
83 uint8_t csp_value;
84 uint8_t csp_mode;
85 uint8_t csp_regs[256];
86 uint8_t csp_index;
87 uint8_t csp_reg83[4];
88 int csp_reg83r;
89 int csp_reg83w;
90
bellardd75d9f62004-10-09 17:20:54 +000091 uint8_t in2_data[10];
bellard85571bc2004-11-07 18:04:02 +000092 uint8_t out_data[50];
93 uint8_t test_reg;
94 uint8_t last_read_byte;
95 int nzero;
bellard27503322003-11-13 01:46:15 +000096
97 int left_till_irq;
bellard27503322003-11-13 01:46:15 +000098
bellard85571bc2004-11-07 18:04:02 +000099 int dma_running;
100 int bytes_per_second;
101 int align;
102 SWVoice *voice;
103
104 QEMUTimer *ts, *aux_ts;
bellard5e2a6442004-03-23 22:42:11 +0000105 /* mixer state */
106 int mixer_nreg;
bellard202a4562004-04-16 22:09:02 +0000107 uint8_t mixer_regs[256];
bellard5e2a6442004-03-23 22:42:11 +0000108} SB16State;
bellard27503322003-11-13 01:46:15 +0000109
bellard5e2a6442004-03-23 22:42:11 +0000110/* XXX: suppress that and use a context */
111static struct SB16State dsp;
112
bellard85571bc2004-11-07 18:04:02 +0000113static int magic_of_irq (int irq)
114{
115 switch (irq) {
116 case 5:
117 return 2;
118 case 7:
119 return 4;
120 case 9:
121 return 1;
122 case 10:
123 return 8;
124 default:
125 dolog ("bad irq %d\n", irq);
126 return 2;
127 }
128}
129
130static int irq_of_magic (int magic)
131{
132 switch (magic) {
133 case 1:
134 return 9;
135 case 2:
136 return 5;
137 case 4:
138 return 7;
139 case 8:
140 return 10;
141 default:
142 dolog ("bad irq magic %d\n", magic);
143 return -1;
144 }
145}
146
147#if 0
bellard5e2a6442004-03-23 22:42:11 +0000148static void log_dsp (SB16State *dsp)
bellard27503322003-11-13 01:46:15 +0000149{
bellard85571bc2004-11-07 18:04:02 +0000150 ldebug ("%s:%s:%d:%s:dmasize=%d:freq=%d:const=%d:speaker=%d\n",
151 dsp->fmt_stereo ? "Stereo" : "Mono",
152 dsp->fmt_signed ? "Signed" : "Unsigned",
153 dsp->fmt_bits,
154 dsp->dma_auto ? "Auto" : "Single",
155 dsp->block_size,
156 dsp->freq,
157 dsp->time_const,
158 dsp->speaker);
159}
160#endif
161
162static void speaker (SB16State *s, int on)
163{
164 s->speaker = on;
165 /* AUD_enable (s->voice, on); */
bellard27503322003-11-13 01:46:15 +0000166}
167
bellard85571bc2004-11-07 18:04:02 +0000168static void control (SB16State *s, int hold)
bellard27503322003-11-13 01:46:15 +0000169{
bellard85571bc2004-11-07 18:04:02 +0000170 int dma = s->use_hdma ? s->hdma : s->dma;
171 s->dma_running = hold;
172
173 ldebug ("hold %d high %d dma %d\n", hold, s->use_hdma, dma);
174
bellard27503322003-11-13 01:46:15 +0000175 if (hold) {
bellard85571bc2004-11-07 18:04:02 +0000176 DMA_hold_DREQ (dma);
177 AUD_enable (s->voice, 1);
bellard27503322003-11-13 01:46:15 +0000178 }
179 else {
bellard85571bc2004-11-07 18:04:02 +0000180 DMA_release_DREQ (dma);
181 AUD_enable (s->voice, 0);
bellard27503322003-11-13 01:46:15 +0000182 }
183}
184
bellard85571bc2004-11-07 18:04:02 +0000185static void aux_timer (void *opaque)
bellard27503322003-11-13 01:46:15 +0000186{
bellard85571bc2004-11-07 18:04:02 +0000187 SB16State *s = opaque;
188 s->can_write = 1;
189 pic_set_irq (s->irq, 1);
190}
bellard27503322003-11-13 01:46:15 +0000191
bellard85571bc2004-11-07 18:04:02 +0000192#define DMA8_AUTO 1
193#define DMA8_HIGH 2
194
195static void dma_cmd8 (SB16State *s, int mask, int dma_len)
196{
197 s->fmt = AUD_FMT_U8;
198 s->use_hdma = 0;
199 s->fmt_bits = 8;
200 s->fmt_signed = 0;
201 s->fmt_stereo = (s->mixer_regs[0x0e] & 2) != 0;
202 if (-1 == s->time_const) {
203 s->freq = 11025;
204 }
205 else {
206 int tmp = (256 - s->time_const);
207 s->freq = (1000000 + (tmp / 2)) / tmp;
208 }
209
bellard15b61472004-11-14 16:02:09 +0000210 if (dma_len != -1)
211 s->block_size = dma_len << s->fmt_stereo;
212 else {
213 /* This is apparently the only way to make both Act1/PL
214 and SecondReality/FC work
215
216 Act1 sets block size via command 0x48 and it's an odd number
217 SR does the same with even number
218 Both use stereo, and Creatives own documentation states that
219 0x48 sets block size in bytes less one.. go figure */
220 s->block_size &= ~s->fmt_stereo;
221 }
bellard85571bc2004-11-07 18:04:02 +0000222
223 s->freq >>= s->fmt_stereo;
224 s->left_till_irq = s->block_size;
225 s->bytes_per_second = (s->freq << s->fmt_stereo);
226 /* s->highspeed = (mask & DMA8_HIGH) != 0; */
227 s->dma_auto = (mask & DMA8_AUTO) != 0;
228 s->align = (1 << s->fmt_stereo) - 1;
229
bellard15b61472004-11-14 16:02:09 +0000230 if (s->block_size & s->align)
231 dolog ("warning: unaligned buffer\n");
232
bellard85571bc2004-11-07 18:04:02 +0000233 ldebug ("freq %d, stereo %d, sign %d, bits %d, "
234 "dma %d, auto %d, fifo %d, high %d\n",
235 s->freq, s->fmt_stereo, s->fmt_signed, s->fmt_bits,
236 s->block_size, s->dma_auto, s->fifo, s->highspeed);
237
238 if (s->freq)
239 s->voice = AUD_open (s->voice, "sb16", s->freq,
240 1 << s->fmt_stereo, s->fmt);
241
242 control (s, 1);
243 speaker (s, 1);
244}
245
246static void dma_cmd (SB16State *s, uint8_t cmd, uint8_t d0, int dma_len)
247{
248 s->use_hdma = cmd < 0xc0;
249 s->fifo = (cmd >> 1) & 1;
250 s->dma_auto = (cmd >> 2) & 1;
251 s->fmt_signed = (d0 >> 4) & 1;
252 s->fmt_stereo = (d0 >> 5) & 1;
bellard27503322003-11-13 01:46:15 +0000253
254 switch (cmd >> 4) {
255 case 11:
bellard85571bc2004-11-07 18:04:02 +0000256 s->fmt_bits = 16;
bellard27503322003-11-13 01:46:15 +0000257 break;
258
259 case 12:
bellard85571bc2004-11-07 18:04:02 +0000260 s->fmt_bits = 8;
bellard27503322003-11-13 01:46:15 +0000261 break;
262 }
263
bellard85571bc2004-11-07 18:04:02 +0000264 if (-1 != s->time_const) {
265#if 1
266 int tmp = 256 - s->time_const;
267 s->freq = (1000000 + (tmp / 2)) / tmp;
268#else
269 /* s->freq = 1000000 / ((255 - s->time_const) << s->fmt_stereo); */
270 s->freq = 1000000 / ((255 - s->time_const));
271#endif
272 s->time_const = -1;
bellard27503322003-11-13 01:46:15 +0000273 }
bellard27503322003-11-13 01:46:15 +0000274
bellard85571bc2004-11-07 18:04:02 +0000275 s->block_size = dma_len + 1;
276 s->block_size <<= (s->fmt_bits == 16);
bellard15b61472004-11-14 16:02:09 +0000277 if (!s->dma_auto) {
278 /* It is clear that for DOOM and auto-init this value
279 shouldn't take stereo into account, while Miles Sound Systems
280 setsound.exe with single transfer mode wouldn't work without it
281 wonders of SB16 yet again */
bellard85571bc2004-11-07 18:04:02 +0000282 s->block_size <<= s->fmt_stereo;
bellard15b61472004-11-14 16:02:09 +0000283 }
bellard27503322003-11-13 01:46:15 +0000284
bellard85571bc2004-11-07 18:04:02 +0000285 ldebug ("freq %d, stereo %d, sign %d, bits %d, "
286 "dma %d, auto %d, fifo %d, high %d\n",
287 s->freq, s->fmt_stereo, s->fmt_signed, s->fmt_bits,
288 s->block_size, s->dma_auto, s->fifo, s->highspeed);
bellard27503322003-11-13 01:46:15 +0000289
bellard85571bc2004-11-07 18:04:02 +0000290 if (16 == s->fmt_bits) {
291 if (s->fmt_signed) {
292 s->fmt = AUD_FMT_S16;
bellard27503322003-11-13 01:46:15 +0000293 }
294 else {
bellard85571bc2004-11-07 18:04:02 +0000295 s->fmt = AUD_FMT_U16;
bellard27503322003-11-13 01:46:15 +0000296 }
297 }
298 else {
bellard85571bc2004-11-07 18:04:02 +0000299 if (s->fmt_signed) {
300 s->fmt = AUD_FMT_S8;
bellard27503322003-11-13 01:46:15 +0000301 }
302 else {
bellard85571bc2004-11-07 18:04:02 +0000303 s->fmt = AUD_FMT_U8;
bellard27503322003-11-13 01:46:15 +0000304 }
305 }
306
bellard85571bc2004-11-07 18:04:02 +0000307 s->left_till_irq = s->block_size;
bellard27503322003-11-13 01:46:15 +0000308
bellard85571bc2004-11-07 18:04:02 +0000309 s->bytes_per_second = (s->freq << s->fmt_stereo) << (s->fmt_bits == 16);
310 s->highspeed = 0;
311 s->align = (1 << (s->fmt_stereo + (s->fmt_bits == 16))) - 1;
bellard15b61472004-11-14 16:02:09 +0000312 if (s->block_size & s->align)
313 dolog ("warning: unaligned buffer\n");
bellard85571bc2004-11-07 18:04:02 +0000314
315 if (s->freq)
316 s->voice = AUD_open (s->voice, "sb16", s->freq,
317 1 << s->fmt_stereo, s->fmt);
318
319 control (s, 1);
320 speaker (s, 1);
321}
322
323static inline void dsp_out_data (SB16State *s, uint8_t val)
324{
325 ldebug ("outdata %#x\n", val);
326 if (s->out_data_len < sizeof (s->out_data))
327 s->out_data[s->out_data_len++] = val;
328}
329
330static inline uint8_t dsp_get_data (SB16State *s)
331{
332 if (s->in_index)
333 return s->in2_data[--s->in_index];
bellard27503322003-11-13 01:46:15 +0000334 else {
bellard85571bc2004-11-07 18:04:02 +0000335 dolog ("buffer underflow\n");
bellardd75d9f62004-10-09 17:20:54 +0000336 return 0;
bellard85571bc2004-11-07 18:04:02 +0000337 }
bellardd75d9f62004-10-09 17:20:54 +0000338}
339
bellard85571bc2004-11-07 18:04:02 +0000340static void command (SB16State *s, uint8_t cmd)
bellard27503322003-11-13 01:46:15 +0000341{
bellard85571bc2004-11-07 18:04:02 +0000342 ldebug ("command %#x\n", cmd);
bellard27503322003-11-13 01:46:15 +0000343
344 if (cmd > 0xaf && cmd < 0xd0) {
bellard85571bc2004-11-07 18:04:02 +0000345 if (cmd & 8) {
346 dolog ("ADC not yet supported (command %#x)\n", cmd);
347 }
bellard27503322003-11-13 01:46:15 +0000348
349 switch (cmd >> 4) {
350 case 11:
351 case 12:
352 break;
353 default:
bellard85571bc2004-11-07 18:04:02 +0000354 dolog ("%#x wrong bits\n", cmd);
bellard27503322003-11-13 01:46:15 +0000355 }
bellard85571bc2004-11-07 18:04:02 +0000356 s->needed_bytes = 3;
bellard27503322003-11-13 01:46:15 +0000357 }
358 else {
359 switch (cmd) {
bellardd75d9f62004-10-09 17:20:54 +0000360 case 0x03:
bellard85571bc2004-11-07 18:04:02 +0000361 dsp_out_data (s, 0x10); /* s->csp_param); */
362 goto warn;
363
bellardd329a6f2004-06-07 20:58:31 +0000364 case 0x04:
bellard85571bc2004-11-07 18:04:02 +0000365 s->needed_bytes = 1;
366 goto warn;
bellardd329a6f2004-06-07 20:58:31 +0000367
368 case 0x05:
bellard85571bc2004-11-07 18:04:02 +0000369 s->needed_bytes = 2;
370 goto warn;
371
372 case 0x08:
373 /* __asm__ ("int3"); */
374 goto warn;
bellardd75d9f62004-10-09 17:20:54 +0000375
bellardd329a6f2004-06-07 20:58:31 +0000376 case 0x0e:
bellard85571bc2004-11-07 18:04:02 +0000377 s->needed_bytes = 2;
378 goto warn;
379
380 case 0x09:
381 dsp_out_data (s, 0xf8);
382 goto warn;
bellardd329a6f2004-06-07 20:58:31 +0000383
384 case 0x0f:
bellard85571bc2004-11-07 18:04:02 +0000385 s->needed_bytes = 1;
386 goto warn;
bellardd329a6f2004-06-07 20:58:31 +0000387
bellard27503322003-11-13 01:46:15 +0000388 case 0x10:
bellard85571bc2004-11-07 18:04:02 +0000389 s->needed_bytes = 1;
390 goto warn;
bellard27503322003-11-13 01:46:15 +0000391
392 case 0x14:
bellard85571bc2004-11-07 18:04:02 +0000393 s->needed_bytes = 2;
394 s->block_size = 0;
bellard27503322003-11-13 01:46:15 +0000395 break;
396
bellard15b61472004-11-14 16:02:09 +0000397 case 0x1c: /* Auto-Initialize DMA DAC, 8-bit */
398 control (s, 1);
399 break;
400
bellard85571bc2004-11-07 18:04:02 +0000401 case 0x20: /* Direct ADC, Juice/PL */
402 dsp_out_data (s, 0xff);
403 goto warn;
bellard27503322003-11-13 01:46:15 +0000404
405 case 0x35:
bellard85571bc2004-11-07 18:04:02 +0000406 dolog ("MIDI command(0x35) not implemented\n");
bellard27503322003-11-13 01:46:15 +0000407 break;
408
409 case 0x40:
bellard85571bc2004-11-07 18:04:02 +0000410 s->freq = -1;
411 s->time_const = -1;
412 s->needed_bytes = 1;
bellard27503322003-11-13 01:46:15 +0000413 break;
414
415 case 0x41:
bellard85571bc2004-11-07 18:04:02 +0000416 s->freq = -1;
417 s->time_const = -1;
418 s->needed_bytes = 2;
bellard27503322003-11-13 01:46:15 +0000419 break;
420
bellard85571bc2004-11-07 18:04:02 +0000421 case 0x42:
422 s->freq = -1;
423 s->time_const = -1;
424 s->needed_bytes = 2;
425 goto warn;
426
bellardd75d9f62004-10-09 17:20:54 +0000427 case 0x45:
bellard85571bc2004-11-07 18:04:02 +0000428 dsp_out_data (s, 0xaa);
429 goto warn;
430
bellard27503322003-11-13 01:46:15 +0000431 case 0x47: /* Continue Auto-Initialize DMA 16bit */
432 break;
433
434 case 0x48:
bellard85571bc2004-11-07 18:04:02 +0000435 s->needed_bytes = 2;
bellard27503322003-11-13 01:46:15 +0000436 break;
437
bellard27503322003-11-13 01:46:15 +0000438 case 0x80:
bellard85571bc2004-11-07 18:04:02 +0000439 s->needed_bytes = 2;
bellard27503322003-11-13 01:46:15 +0000440 break;
441
442 case 0x90:
443 case 0x91:
bellard85571bc2004-11-07 18:04:02 +0000444 dma_cmd8 (s, ((cmd & 1) == 0) | DMA8_HIGH, -1);
bellard27503322003-11-13 01:46:15 +0000445 break;
446
bellard85571bc2004-11-07 18:04:02 +0000447 case 0xd0: /* halt DMA operation. 8bit */
448 control (s, 0);
bellard27503322003-11-13 01:46:15 +0000449 break;
450
bellard85571bc2004-11-07 18:04:02 +0000451 case 0xd1: /* speaker on */
452 speaker (s, 1);
bellard27503322003-11-13 01:46:15 +0000453 break;
454
bellard85571bc2004-11-07 18:04:02 +0000455 case 0xd3: /* speaker off */
456 speaker (s, 0);
bellard27503322003-11-13 01:46:15 +0000457 break;
458
bellard85571bc2004-11-07 18:04:02 +0000459 case 0xd4: /* continue DMA operation. 8bit */
460 control (s, 1);
461 break;
bellard27503322003-11-13 01:46:15 +0000462
bellard85571bc2004-11-07 18:04:02 +0000463 case 0xd5: /* halt DMA operation. 16bit */
464 control (s, 0);
465 break;
466
467 case 0xd6: /* continue DMA operation. 16bit */
468 control (s, 1);
469 break;
470
471 case 0xd9: /* exit auto-init DMA after this block. 16bit */
472 s->dma_auto = 0;
473 break;
474
475 case 0xda: /* exit auto-init DMA after this block. 8bit */
476 s->dma_auto = 0;
bellard27503322003-11-13 01:46:15 +0000477 break;
478
479 case 0xe0:
bellard85571bc2004-11-07 18:04:02 +0000480 s->needed_bytes = 1;
481 goto warn;
bellard27503322003-11-13 01:46:15 +0000482
483 case 0xe1:
bellard85571bc2004-11-07 18:04:02 +0000484 dsp_out_data (s, s->ver & 0xff);
485 dsp_out_data (s, s->ver >> 8);
486 break;
487
488 case 0xe2:
489 s->needed_bytes = 1;
490 goto warn;
bellard27503322003-11-13 01:46:15 +0000491
bellardd329a6f2004-06-07 20:58:31 +0000492 case 0xe3:
493 {
494 int i;
bellard85571bc2004-11-07 18:04:02 +0000495 for (i = sizeof (e3) - 1; i >= 0; --i)
496 dsp_out_data (s, e3[i]);
bellardd329a6f2004-06-07 20:58:31 +0000497 }
bellardd75d9f62004-10-09 17:20:54 +0000498 break;
499
bellard85571bc2004-11-07 18:04:02 +0000500 case 0xe4: /* write test reg */
501 s->needed_bytes = 1;
502 break;
503
504 case 0xe7:
505 dolog ("Attempt to probe for ESS (0xe7)?\n");
506 return;
507
bellardd75d9f62004-10-09 17:20:54 +0000508 case 0xe8: /* read test reg */
bellard85571bc2004-11-07 18:04:02 +0000509 dsp_out_data (s, s->test_reg);
bellardd75d9f62004-10-09 17:20:54 +0000510 break;
511
bellard27503322003-11-13 01:46:15 +0000512 case 0xf2:
bellard85571bc2004-11-07 18:04:02 +0000513 case 0xf3:
514 dsp_out_data (s, 0xaa);
515 s->mixer_regs[0x82] |= (cmd == 0xf2) ? 1 : 2;
516 pic_set_irq (s->irq, 1);
517 break;
bellard27503322003-11-13 01:46:15 +0000518
bellardd75d9f62004-10-09 17:20:54 +0000519 case 0xf9:
bellard85571bc2004-11-07 18:04:02 +0000520 s->needed_bytes = 1;
521 goto warn;
bellardd75d9f62004-10-09 17:20:54 +0000522
523 case 0xfa:
bellard85571bc2004-11-07 18:04:02 +0000524 dsp_out_data (s, 0);
525 goto warn;
bellardd75d9f62004-10-09 17:20:54 +0000526
527 case 0xfc: /* FIXME */
bellard85571bc2004-11-07 18:04:02 +0000528 dsp_out_data (s, 0);
529 goto warn;
bellardd75d9f62004-10-09 17:20:54 +0000530
bellard27503322003-11-13 01:46:15 +0000531 default:
bellardd75d9f62004-10-09 17:20:54 +0000532 dolog ("unrecognized command %#x\n", cmd);
bellard5e2a6442004-03-23 22:42:11 +0000533 return;
bellard27503322003-11-13 01:46:15 +0000534 }
535 }
536
bellard85571bc2004-11-07 18:04:02 +0000537 s->cmd = cmd;
538 if (!s->needed_bytes)
539 ldebug ("\n");
bellard27503322003-11-13 01:46:15 +0000540 return;
bellard85571bc2004-11-07 18:04:02 +0000541
542 warn:
bellardfb065182004-11-09 23:09:44 +0000543 dolog ("warning: command %#x,%d is not trully understood yet\n",
bellard85571bc2004-11-07 18:04:02 +0000544 cmd, s->needed_bytes);
545 s->cmd = cmd;
546 return;
547}
548
549static uint16_t dsp_get_lohi (SB16State *s)
550{
551 uint8_t hi = dsp_get_data (s);
552 uint8_t lo = dsp_get_data (s);
553 return (hi << 8) | lo;
554}
555
556static uint16_t dsp_get_hilo (SB16State *s)
557{
558 uint8_t lo = dsp_get_data (s);
559 uint8_t hi = dsp_get_data (s);
560 return (hi << 8) | lo;
561}
562
563static void complete (SB16State *s)
564{
565 int d0, d1, d2;
566 ldebug ("complete command %#x, in_index %d, needed_bytes %d\n",
567 s->cmd, s->in_index, s->needed_bytes);
568
569 if (s->cmd > 0xaf && s->cmd < 0xd0) {
570 d2 = dsp_get_data (s);
571 d1 = dsp_get_data (s);
572 d0 = dsp_get_data (s);
573
574 if (s->cmd & 8) {
575 dolog ("ADC params cmd = %#x d0 = %d, d1 = %d, d2 = %d\n",
576 s->cmd, d0, d1, d2);
577 }
578 else {
579 ldebug ("cmd = %#x d0 = %d, d1 = %d, d2 = %d\n",
580 s->cmd, d0, d1, d2);
581 dma_cmd (s, s->cmd, d0, d1 + (d2 << 8));
582 }
583 }
584 else {
585 switch (s->cmd) {
586 case 0x04:
587 s->csp_mode = dsp_get_data (s);
588 s->csp_reg83r = 0;
589 s->csp_reg83w = 0;
590 ldebug ("CSP command 0x04: mode=%#x\n", s->csp_mode);
591 break;
592
593 case 0x05:
594 s->csp_param = dsp_get_data (s);
595 s->csp_value = dsp_get_data (s);
596 ldebug ("CSP command 0x05: param=%#x value=%#x\n",
597 s->csp_param,
598 s->csp_value);
599 break;
600
601 case 0x0e:
602 d0 = dsp_get_data (s);
603 d1 = dsp_get_data (s);
604 ldebug ("write CSP register %d <- %#x\n", d1, d0);
605 if (d1 == 0x83) {
606 ldebug ("0x83[%d] <- %#x\n", s->csp_reg83r, d0);
607 s->csp_reg83[s->csp_reg83r % 4] = d0;
608 s->csp_reg83r += 1;
609 }
610 else
611 s->csp_regs[d1] = d0;
612 break;
613
614 case 0x0f:
615 d0 = dsp_get_data (s);
616 ldebug ("read CSP register %#x -> %#x, mode=%#x\n",
617 d0, s->csp_regs[d0], s->csp_mode);
618 if (d0 == 0x83) {
619 ldebug ("0x83[%d] -> %#x\n",
620 s->csp_reg83w,
621 s->csp_reg83[s->csp_reg83w % 4]);
622 dsp_out_data (s, s->csp_reg83[s->csp_reg83w % 4]);
623 s->csp_reg83w += 1;
624 }
625 else
626 dsp_out_data (s, s->csp_regs[d0]);
627 break;
628
629 case 0x10:
630 d0 = dsp_get_data (s);
631 dolog ("cmd 0x10 d0=%#x\n", d0);
632 break;
633
634 case 0x14:
bellard15b61472004-11-14 16:02:09 +0000635 dma_cmd8 (s, 0, dsp_get_lohi (s) + 1);
bellard85571bc2004-11-07 18:04:02 +0000636 break;
637
638 case 0x40:
639 s->time_const = dsp_get_data (s);
640 ldebug ("set time const %d\n", s->time_const);
641 break;
642
643 case 0x42: /* FT2 sets output freq with this, go figure */
644 dolog ("cmd 0x42 might not do what it think it should\n");
645
646 case 0x41:
647 s->freq = dsp_get_hilo (s);
648 ldebug ("set freq %d\n", s->freq);
649 break;
650
651 case 0x48:
bellard15b61472004-11-14 16:02:09 +0000652 s->block_size = dsp_get_lohi (s) + 1;
bellard85571bc2004-11-07 18:04:02 +0000653 ldebug ("set dma block len %d\n", s->block_size);
654 break;
655
656 case 0x80:
657 {
bellard15b61472004-11-14 16:02:09 +0000658 int freq, samples, bytes;
bellard85571bc2004-11-07 18:04:02 +0000659 int64_t ticks;
660
bellard15b61472004-11-14 16:02:09 +0000661 freq = s->freq > 0 ? s->freq : 11025;
662 samples = dsp_get_lohi (s) + 1;
bellard85571bc2004-11-07 18:04:02 +0000663 bytes = samples << s->fmt_stereo << (s->fmt_bits == 16);
bellard15b61472004-11-14 16:02:09 +0000664 ticks = (bytes * ticks_per_sec) / freq;
665 if (ticks < ticks_per_sec / 1024)
bellard85571bc2004-11-07 18:04:02 +0000666 pic_set_irq (s->irq, 1);
667 else
668 qemu_mod_timer (s->aux_ts, qemu_get_clock (vm_clock) + ticks);
669 ldebug ("mix silence %d %d %lld\n", samples, bytes, ticks);
670 }
671 break;
672
673 case 0xe0:
674 d0 = dsp_get_data (s);
675 s->out_data_len = 0;
676 ldebug ("E0 data = %#x\n", d0);
677 dsp_out_data(s, ~d0);
678 break;
679
680 case 0xe2:
681 d0 = dsp_get_data (s);
bellard15b61472004-11-14 16:02:09 +0000682 ldebug ("E2 = %#x\n", d0);
bellard85571bc2004-11-07 18:04:02 +0000683 break;
684
685 case 0xe4:
686 s->test_reg = dsp_get_data (s);
687 break;
688
689 case 0xf9:
690 d0 = dsp_get_data (s);
691 ldebug ("command 0xf9 with %#x\n", d0);
692 switch (d0) {
693 case 0x0e:
694 dsp_out_data (s, 0xff);
695 break;
696
697 case 0x0f:
698 dsp_out_data (s, 0x07);
699 break;
700
701 case 0x37:
702 dsp_out_data (s, 0x38);
703 break;
704
705 default:
706 dsp_out_data (s, 0x00);
707 break;
708 }
709 break;
710
711 default:
712 dolog ("complete: unrecognized command %#x\n", s->cmd);
713 return;
714 }
715 }
716
717 ldebug ("\n");
718 s->cmd = -1;
719 return;
720}
721
722static void reset (SB16State *s)
723{
724 pic_set_irq (s->irq, 0);
725 if (s->dma_auto) {
726 pic_set_irq (s->irq, 1);
727 pic_set_irq (s->irq, 0);
728 }
729
730 s->mixer_regs[0x82] = 0;
731 s->dma_auto = 0;
732 s->in_index = 0;
733 s->out_data_len = 0;
734 s->left_till_irq = 0;
735 s->needed_bytes = 0;
736 s->block_size = -1;
737 s->nzero = 0;
738 s->highspeed = 0;
739 s->v2x6 = 0;
740
741 dsp_out_data(s, 0xaa);
742 speaker (s, 0);
743 control (s, 0);
bellard27503322003-11-13 01:46:15 +0000744}
745
746static IO_WRITE_PROTO (dsp_write)
747{
bellard85571bc2004-11-07 18:04:02 +0000748 SB16State *s = opaque;
bellard27503322003-11-13 01:46:15 +0000749 int iport;
750
bellard85571bc2004-11-07 18:04:02 +0000751 iport = nport - s->port;
bellard27503322003-11-13 01:46:15 +0000752
bellard85571bc2004-11-07 18:04:02 +0000753 ldebug ("write %#x <- %#x\n", nport, val);
bellard27503322003-11-13 01:46:15 +0000754 switch (iport) {
bellard85571bc2004-11-07 18:04:02 +0000755 case 0x06:
756 switch (val) {
757 case 0x00:
758 if (s->v2x6 == 1) {
759 if (0 && s->highspeed) {
760 s->highspeed = 0;
761 pic_set_irq (s->irq, 0);
762 control (s, 0);
763 }
764 else
765 reset (s);
766 }
767 s->v2x6 = 0;
768 break;
769
770 case 0x01:
771 case 0x03: /* FreeBSD kludge */
772 s->v2x6 = 1;
773 break;
774
775 case 0xc6:
776 s->v2x6 = 0; /* Prince of Persia, csp.sys, diagnose.exe */
777 break;
778
779 case 0xb8: /* Panic */
780 reset (s);
781 break;
782
783 case 0x39:
784 dsp_out_data (s, 0x38);
785 reset (s);
786 s->v2x6 = 0x39;
787 break;
788
789 default:
790 s->v2x6 = val;
791 break;
bellard27503322003-11-13 01:46:15 +0000792 }
bellard27503322003-11-13 01:46:15 +0000793 break;
794
bellard85571bc2004-11-07 18:04:02 +0000795 case 0x0c: /* write data or command | write status */
796/* if (s->highspeed) */
797/* break; */
798
799 if (0 == s->needed_bytes) {
800 command (s, val);
801#if 0
802 if (0 == s->needed_bytes) {
803 log_dsp (s);
bellard27503322003-11-13 01:46:15 +0000804 }
bellard85571bc2004-11-07 18:04:02 +0000805#endif
bellard27503322003-11-13 01:46:15 +0000806 }
807 else {
bellard85571bc2004-11-07 18:04:02 +0000808 if (s->in_index == sizeof (s->in2_data)) {
bellardd75d9f62004-10-09 17:20:54 +0000809 dolog ("in data overrun\n");
810 }
811 else {
bellard85571bc2004-11-07 18:04:02 +0000812 s->in2_data[s->in_index++] = val;
813 if (s->in_index == s->needed_bytes) {
814 s->needed_bytes = 0;
815 complete (s);
816#if 0
817 log_dsp (s);
818#endif
819 }
bellard27503322003-11-13 01:46:15 +0000820 }
821 }
822 break;
823
824 default:
bellard85571bc2004-11-07 18:04:02 +0000825 ldebug ("(nport=%#x, val=%#x)\n", nport, val);
bellard5e2a6442004-03-23 22:42:11 +0000826 break;
bellard27503322003-11-13 01:46:15 +0000827 }
828}
829
830static IO_READ_PROTO (dsp_read)
831{
bellard85571bc2004-11-07 18:04:02 +0000832 SB16State *s = opaque;
833 int iport, retval, ack = 0;
bellard27503322003-11-13 01:46:15 +0000834
bellard85571bc2004-11-07 18:04:02 +0000835 iport = nport - s->port;
bellard27503322003-11-13 01:46:15 +0000836
837 switch (iport) {
bellard85571bc2004-11-07 18:04:02 +0000838 case 0x06: /* reset */
839 retval = 0xff;
bellardd75d9f62004-10-09 17:20:54 +0000840 break;
bellard27503322003-11-13 01:46:15 +0000841
bellard85571bc2004-11-07 18:04:02 +0000842 case 0x0a: /* read data */
843 if (s->out_data_len) {
844 retval = s->out_data[--s->out_data_len];
845 s->last_read_byte = retval;
846 }
847 else {
bellardd75d9f62004-10-09 17:20:54 +0000848 dolog ("empty output buffer\n");
bellard85571bc2004-11-07 18:04:02 +0000849 retval = s->last_read_byte;
bellardd75d9f62004-10-09 17:20:54 +0000850 /* goto error; */
bellard27503322003-11-13 01:46:15 +0000851 }
852 break;
853
bellard85571bc2004-11-07 18:04:02 +0000854 case 0x0c: /* 0 can write */
855 retval = s->can_write ? 0 : 0x80;
856 break;
857
858 case 0x0d: /* timer interrupt clear */
859 /* dolog ("timer interrupt clear\n"); */
bellard27503322003-11-13 01:46:15 +0000860 retval = 0;
861 break;
862
bellard85571bc2004-11-07 18:04:02 +0000863 case 0x0e: /* data available status | irq 8 ack */
864 retval = (!s->out_data_len || s->highspeed) ? 0 : 0x80;
865 if (s->mixer_regs[0x82] & 1) {
866 ack = 1;
867 s->mixer_regs[0x82] &= 1;
868 pic_set_irq (s->irq, 0);
869 }
bellard27503322003-11-13 01:46:15 +0000870 break;
871
bellard85571bc2004-11-07 18:04:02 +0000872 case 0x0f: /* irq 16 ack */
bellardbc0b1dc2004-01-18 22:19:31 +0000873 retval = 0xff;
bellard85571bc2004-11-07 18:04:02 +0000874 if (s->mixer_regs[0x82] & 2) {
875 ack = 1;
876 s->mixer_regs[0x82] &= 2;
877 pic_set_irq (s->irq, 0);
878 }
bellard27503322003-11-13 01:46:15 +0000879 break;
880
881 default:
882 goto error;
883 }
884
bellard85571bc2004-11-07 18:04:02 +0000885 if (!ack)
886 ldebug ("read %#x -> %#x\n", nport, retval);
bellard27503322003-11-13 01:46:15 +0000887
888 return retval;
889
890 error:
bellard85571bc2004-11-07 18:04:02 +0000891 dolog ("WARNING dsp_read %#x error\n", nport);
bellardd75d9f62004-10-09 17:20:54 +0000892 return 0xff;
bellard27503322003-11-13 01:46:15 +0000893}
894
bellard85571bc2004-11-07 18:04:02 +0000895static void reset_mixer (SB16State *s)
896{
897 int i;
898
899 memset (s->mixer_regs, 0xff, 0x7f);
900 memset (s->mixer_regs + 0x83, 0xff, sizeof (s->mixer_regs) - 0x83);
901
902 s->mixer_regs[0x02] = 4; /* master volume 3bits */
903 s->mixer_regs[0x06] = 4; /* MIDI volume 3bits */
904 s->mixer_regs[0x08] = 0; /* CD volume 3bits */
905 s->mixer_regs[0x0a] = 0; /* voice volume 2bits */
906
907 /* d5=input filt, d3=lowpass filt, d1,d2=input source */
908 s->mixer_regs[0x0c] = 0;
909
910 /* d5=output filt, d1=stereo switch */
911 s->mixer_regs[0x0e] = 0;
912
913 /* voice volume L d5,d7, R d1,d3 */
914 s->mixer_regs[0x04] = (4 << 5) | (4 << 1);
915 /* master ... */
916 s->mixer_regs[0x22] = (4 << 5) | (4 << 1);
917 /* MIDI ... */
918 s->mixer_regs[0x26] = (4 << 5) | (4 << 1);
919
920 for (i = 0x30; i < 0x48; i++) {
921 s->mixer_regs[i] = 0x20;
922 }
923}
924
bellard27503322003-11-13 01:46:15 +0000925static IO_WRITE_PROTO(mixer_write_indexb)
926{
bellard85571bc2004-11-07 18:04:02 +0000927 SB16State *s = opaque;
928 s->mixer_nreg = val;
bellard27503322003-11-13 01:46:15 +0000929}
930
931static IO_WRITE_PROTO(mixer_write_datab)
932{
bellard85571bc2004-11-07 18:04:02 +0000933 SB16State *s = opaque;
bellard202a4562004-04-16 22:09:02 +0000934
bellard85571bc2004-11-07 18:04:02 +0000935 ldebug ("mixer_write [%#x] <- %#x\n", s->mixer_nreg, val);
936 if (s->mixer_nreg > sizeof (s->mixer_regs))
937 return;
938
939 switch (s->mixer_nreg) {
bellardd75d9f62004-10-09 17:20:54 +0000940 case 0x00:
bellard85571bc2004-11-07 18:04:02 +0000941 reset_mixer (s);
942 break;
bellardd75d9f62004-10-09 17:20:54 +0000943
bellard85571bc2004-11-07 18:04:02 +0000944 case 0x80:
945 {
946 int irq = irq_of_magic (val);
947 ldebug ("setting irq to %d (val=%#x)\n", irq, val);
948 if (irq > 0)
949 s->irq = irq;
bellardd75d9f62004-10-09 17:20:54 +0000950 }
951 break;
952
bellardd75d9f62004-10-09 17:20:54 +0000953 case 0x81:
bellard85571bc2004-11-07 18:04:02 +0000954 {
955 int dma, hdma;
956
957 dma = lsbindex (val & 0xf);
958 hdma = lsbindex (val & 0xf0);
959 dolog ("attempt to set DMA register 8bit %d, 16bit %d (val=%#x)\n",
960 dma, hdma, val);
961#if 0
962 s->dma = dma;
963 s->hdma = hdma;
964#endif
965 }
bellardd75d9f62004-10-09 17:20:54 +0000966 break;
bellard85571bc2004-11-07 18:04:02 +0000967
968 case 0x82:
969 dolog ("attempt to write into IRQ status register (val=%#x)\n",
970 val);
bellard202a4562004-04-16 22:09:02 +0000971 return;
bellard85571bc2004-11-07 18:04:02 +0000972
973 default:
974 if (s->mixer_nreg >= 0x80)
975 dolog ("attempt to write mixer[%#x] <- %#x\n", s->mixer_nreg, val);
976 break;
bellardd75d9f62004-10-09 17:20:54 +0000977 }
bellard27503322003-11-13 01:46:15 +0000978
bellard85571bc2004-11-07 18:04:02 +0000979 s->mixer_regs[s->mixer_nreg] = val;
bellardd75d9f62004-10-09 17:20:54 +0000980}
981
bellard27503322003-11-13 01:46:15 +0000982static IO_WRITE_PROTO(mixer_write_indexw)
983{
bellard7d977de2004-03-14 21:41:34 +0000984 mixer_write_indexb (opaque, nport, val & 0xff);
985 mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
bellard27503322003-11-13 01:46:15 +0000986}
987
988static IO_READ_PROTO(mixer_read)
989{
bellard85571bc2004-11-07 18:04:02 +0000990 SB16State *s = opaque;
bellard15b61472004-11-14 16:02:09 +0000991#ifndef DEBUG_SB16_MOST
992 if (s->mixer_nreg != 0x82)
993#endif
bellard85571bc2004-11-07 18:04:02 +0000994 ldebug ("mixer_read[%#x] -> %#x\n",
995 s->mixer_nreg, s->mixer_regs[s->mixer_nreg]);
996 return s->mixer_regs[s->mixer_nreg];
bellard27503322003-11-13 01:46:15 +0000997}
998
bellard85571bc2004-11-07 18:04:02 +0000999static int write_audio (SB16State *s, int nchan, int dma_pos,
1000 int dma_len, int len)
bellard27503322003-11-13 01:46:15 +00001001{
1002 int temp, net;
bellardf9e92e92004-02-25 23:32:01 +00001003 uint8_t tmpbuf[4096];
bellard27503322003-11-13 01:46:15 +00001004
bellard85571bc2004-11-07 18:04:02 +00001005 temp = len;
bellard27503322003-11-13 01:46:15 +00001006 net = 0;
1007
1008 while (temp) {
bellard85571bc2004-11-07 18:04:02 +00001009 int left = dma_len - dma_pos;
1010 int to_copy, copied;
bellard27503322003-11-13 01:46:15 +00001011
bellard85571bc2004-11-07 18:04:02 +00001012 to_copy = audio_MIN (temp, left);
bellardf9e92e92004-02-25 23:32:01 +00001013 if (to_copy > sizeof(tmpbuf))
1014 to_copy = sizeof(tmpbuf);
bellard85571bc2004-11-07 18:04:02 +00001015
1016 copied = DMA_read_memory (nchan, tmpbuf, dma_pos, to_copy);
1017 copied = AUD_write (s->voice, tmpbuf, copied);
bellard27503322003-11-13 01:46:15 +00001018
1019 temp -= copied;
bellard85571bc2004-11-07 18:04:02 +00001020 dma_pos = (dma_pos + copied) % dma_len;
bellard27503322003-11-13 01:46:15 +00001021 net += copied;
1022
bellard85571bc2004-11-07 18:04:02 +00001023 if (!copied)
1024 break;
bellard27503322003-11-13 01:46:15 +00001025 }
1026
1027 return net;
1028}
1029
bellard85571bc2004-11-07 18:04:02 +00001030static int SB_read_DMA (void *opaque, int nchan, int dma_pos, int dma_len)
bellard27503322003-11-13 01:46:15 +00001031{
bellard85571bc2004-11-07 18:04:02 +00001032 SB16State *s = opaque;
1033 int free, rfree, till, copy, written, elapsed;
bellard27503322003-11-13 01:46:15 +00001034
bellard85571bc2004-11-07 18:04:02 +00001035 if (s->left_till_irq < 0) {
1036 s->left_till_irq = s->block_size;
bellard27503322003-11-13 01:46:15 +00001037 }
1038
bellard85571bc2004-11-07 18:04:02 +00001039 elapsed = AUD_calc_elapsed (s->voice);
1040 free = elapsed;/* AUD_get_free (s->voice); */
1041 rfree = free;
1042 free = audio_MIN (free, elapsed) & ~s->align;
bellard27503322003-11-13 01:46:15 +00001043
bellard85571bc2004-11-07 18:04:02 +00001044 if ((free <= 0) || !dma_len) {
1045 return dma_pos;
bellard27503322003-11-13 01:46:15 +00001046 }
1047
bellard85571bc2004-11-07 18:04:02 +00001048 copy = free;
1049 till = s->left_till_irq;
bellard27503322003-11-13 01:46:15 +00001050
bellardd75d9f62004-10-09 17:20:54 +00001051#ifdef DEBUG_SB16_MOST
bellard85571bc2004-11-07 18:04:02 +00001052 dolog ("pos:%06d free:%d,%d till:%d len:%d\n",
1053 dma_pos, free, AUD_get_free (s->voice), till, dma_len);
bellardd75d9f62004-10-09 17:20:54 +00001054#endif
1055
bellard27503322003-11-13 01:46:15 +00001056 if (till <= copy) {
bellard85571bc2004-11-07 18:04:02 +00001057 if (0 == s->dma_auto) {
bellard27503322003-11-13 01:46:15 +00001058 copy = till;
1059 }
1060 }
1061
bellard85571bc2004-11-07 18:04:02 +00001062 written = write_audio (s, nchan, dma_pos, dma_len, copy);
1063 dma_pos = (dma_pos + written) % dma_len;
1064 s->left_till_irq -= written;
bellard27503322003-11-13 01:46:15 +00001065
bellard85571bc2004-11-07 18:04:02 +00001066 if (s->left_till_irq <= 0) {
1067 s->mixer_regs[0x82] |= (nchan & 4) ? 2 : 1;
1068 pic_set_irq (s->irq, 1);
1069 if (0 == s->dma_auto) {
1070 control (s, 0);
1071 speaker (s, 0);
bellard27503322003-11-13 01:46:15 +00001072 }
1073 }
1074
bellardd75d9f62004-10-09 17:20:54 +00001075#ifdef DEBUG_SB16_MOST
bellard15b61472004-11-14 16:02:09 +00001076 ldebug ("pos %5d free %5d size %5d till % 5d copy %5d written %5d size %5d\n",
1077 dma_pos, free, dma_len, s->left_till_irq, copy, written,
1078 s->block_size);
bellardd75d9f62004-10-09 17:20:54 +00001079#endif
bellard27503322003-11-13 01:46:15 +00001080
bellard85571bc2004-11-07 18:04:02 +00001081 while (s->left_till_irq <= 0) {
1082 s->left_till_irq = s->block_size + s->left_till_irq;
bellard27503322003-11-13 01:46:15 +00001083 }
1084
bellard85571bc2004-11-07 18:04:02 +00001085 AUD_adjust (s->voice, written);
1086 return dma_pos;
bellard27503322003-11-13 01:46:15 +00001087}
1088
bellard85571bc2004-11-07 18:04:02 +00001089void SB_timer (void *opaque)
bellard27503322003-11-13 01:46:15 +00001090{
bellard85571bc2004-11-07 18:04:02 +00001091 SB16State *s = opaque;
1092 AUD_run ();
1093 qemu_mod_timer (s->ts, qemu_get_clock (vm_clock) + 1);
bellard27503322003-11-13 01:46:15 +00001094}
1095
bellard85571bc2004-11-07 18:04:02 +00001096static void SB_save (QEMUFile *f, void *opaque)
bellard27503322003-11-13 01:46:15 +00001097{
bellard85571bc2004-11-07 18:04:02 +00001098 SB16State *s = opaque;
bellard27503322003-11-13 01:46:15 +00001099
bellard85571bc2004-11-07 18:04:02 +00001100 qemu_put_be32s (f, &s->irq);
1101 qemu_put_be32s (f, &s->dma);
1102 qemu_put_be32s (f, &s->hdma);
1103 qemu_put_be32s (f, &s->port);
1104 qemu_put_be32s (f, &s->ver);
1105 qemu_put_be32s (f, &s->in_index);
1106 qemu_put_be32s (f, &s->out_data_len);
1107 qemu_put_be32s (f, &s->fmt_stereo);
1108 qemu_put_be32s (f, &s->fmt_signed);
1109 qemu_put_be32s (f, &s->fmt_bits);
1110 qemu_put_be32s (f, &s->fmt);
1111 qemu_put_be32s (f, &s->dma_auto);
1112 qemu_put_be32s (f, &s->block_size);
1113 qemu_put_be32s (f, &s->fifo);
1114 qemu_put_be32s (f, &s->freq);
1115 qemu_put_be32s (f, &s->time_const);
1116 qemu_put_be32s (f, &s->speaker);
1117 qemu_put_be32s (f, &s->needed_bytes);
1118 qemu_put_be32s (f, &s->cmd);
1119 qemu_put_be32s (f, &s->use_hdma);
1120 qemu_put_be32s (f, &s->highspeed);
1121 qemu_put_be32s (f, &s->can_write);
1122 qemu_put_be32s (f, &s->v2x6);
1123
1124 qemu_put_8s (f, &s->csp_param);
1125 qemu_put_8s (f, &s->csp_value);
1126 qemu_put_8s (f, &s->csp_mode);
1127 qemu_put_8s (f, &s->csp_param);
1128 qemu_put_buffer (f, s->csp_regs, 256);
1129 qemu_put_8s (f, &s->csp_index);
1130 qemu_put_buffer (f, s->csp_reg83, 4);
1131 qemu_put_be32s (f, &s->csp_reg83r);
1132 qemu_put_be32s (f, &s->csp_reg83w);
1133
1134 qemu_put_buffer (f, s->in2_data, sizeof (s->in2_data));
1135 qemu_put_buffer (f, s->out_data, sizeof (s->out_data));
1136 qemu_put_8s (f, &s->test_reg);
1137 qemu_put_8s (f, &s->last_read_byte);
1138
1139 qemu_put_be32s (f, &s->nzero);
1140 qemu_put_be32s (f, &s->left_till_irq);
1141 qemu_put_be32s (f, &s->dma_running);
1142 qemu_put_be32s (f, &s->bytes_per_second);
1143 qemu_put_be32s (f, &s->align);
1144
1145 qemu_put_be32s (f, &s->mixer_nreg);
1146 qemu_put_buffer (f, s->mixer_regs, 256);
bellardd75d9f62004-10-09 17:20:54 +00001147}
1148
bellard85571bc2004-11-07 18:04:02 +00001149static int SB_load (QEMUFile *f, void *opaque, int version_id)
bellardd75d9f62004-10-09 17:20:54 +00001150{
bellard85571bc2004-11-07 18:04:02 +00001151 SB16State *s = opaque;
1152
1153 if (version_id != 1)
1154 return -EINVAL;
1155
1156 qemu_get_be32s (f, &s->irq);
1157 qemu_get_be32s (f, &s->dma);
1158 qemu_get_be32s (f, &s->hdma);
1159 qemu_get_be32s (f, &s->port);
1160 qemu_get_be32s (f, &s->ver);
1161 qemu_get_be32s (f, &s->in_index);
1162 qemu_get_be32s (f, &s->out_data_len);
1163 qemu_get_be32s (f, &s->fmt_stereo);
1164 qemu_get_be32s (f, &s->fmt_signed);
1165 qemu_get_be32s (f, &s->fmt_bits);
1166 qemu_get_be32s (f, &s->fmt);
1167 qemu_get_be32s (f, &s->dma_auto);
1168 qemu_get_be32s (f, &s->block_size);
1169 qemu_get_be32s (f, &s->fifo);
1170 qemu_get_be32s (f, &s->freq);
1171 qemu_get_be32s (f, &s->time_const);
1172 qemu_get_be32s (f, &s->speaker);
1173 qemu_get_be32s (f, &s->needed_bytes);
1174 qemu_get_be32s (f, &s->cmd);
1175 qemu_get_be32s (f, &s->use_hdma);
1176 qemu_get_be32s (f, &s->highspeed);
1177 qemu_get_be32s (f, &s->can_write);
1178 qemu_get_be32s (f, &s->v2x6);
1179
1180 qemu_get_8s (f, &s->csp_param);
1181 qemu_get_8s (f, &s->csp_value);
1182 qemu_get_8s (f, &s->csp_mode);
1183 qemu_get_8s (f, &s->csp_param);
1184 qemu_get_buffer (f, s->csp_regs, 256);
1185 qemu_get_8s (f, &s->csp_index);
1186 qemu_get_buffer (f, s->csp_reg83, 4);
1187 qemu_get_be32s (f, &s->csp_reg83r);
1188 qemu_get_be32s (f, &s->csp_reg83w);
1189
1190 qemu_get_buffer (f, s->in2_data, sizeof (s->in2_data));
1191 qemu_get_buffer (f, s->out_data, sizeof (s->out_data));
1192 qemu_get_8s (f, &s->test_reg);
1193 qemu_get_8s (f, &s->last_read_byte);
1194
1195 qemu_get_be32s (f, &s->nzero);
1196 qemu_get_be32s (f, &s->left_till_irq);
1197 qemu_get_be32s (f, &s->dma_running);
1198 qemu_get_be32s (f, &s->bytes_per_second);
1199 qemu_get_be32s (f, &s->align);
1200
1201 qemu_get_be32s (f, &s->mixer_nreg);
1202 qemu_get_buffer (f, s->mixer_regs, 256);
1203
bellardfb065182004-11-09 23:09:44 +00001204 if (s->voice) {
1205 AUD_close (s->voice);
1206 s->voice = NULL;
1207 }
bellard85571bc2004-11-07 18:04:02 +00001208
1209 if (s->dma_running) {
1210 if (s->freq)
1211 s->voice = AUD_open (s->voice, "sb16", s->freq,
1212 1 << s->fmt_stereo, s->fmt);
1213
1214 control (s, 1);
1215 speaker (s, s->speaker);
bellardd75d9f62004-10-09 17:20:54 +00001216 }
bellard85571bc2004-11-07 18:04:02 +00001217 return 0;
bellardd75d9f62004-10-09 17:20:54 +00001218}
bellardd75d9f62004-10-09 17:20:54 +00001219
bellard27503322003-11-13 01:46:15 +00001220void SB16_init (void)
1221{
bellard5e2a6442004-03-23 22:42:11 +00001222 SB16State *s = &dsp;
bellard27503322003-11-13 01:46:15 +00001223 int i;
1224 static const uint8_t dsp_write_ports[] = {0x6, 0xc};
1225 static const uint8_t dsp_read_ports[] = {0x6, 0xa, 0xc, 0xd, 0xe, 0xf};
1226
bellard85571bc2004-11-07 18:04:02 +00001227 s->ts = qemu_new_timer (vm_clock, SB_timer, s);
1228 if (!s->ts)
1229 return;
bellard202a4562004-04-16 22:09:02 +00001230
bellard85571bc2004-11-07 18:04:02 +00001231 s->irq = conf.irq;
1232 s->dma = conf.dma;
1233 s->hdma = conf.hdma;
1234 s->port = conf.port;
1235 s->ver = conf.ver_lo | (conf.ver_hi << 8);
bellard27503322003-11-13 01:46:15 +00001236
bellard85571bc2004-11-07 18:04:02 +00001237 s->mixer_regs[0x80] = magic_of_irq (s->irq);
1238 s->mixer_regs[0x81] = (1 << s->dma) | (1 << s->hdma);
1239 s->mixer_regs[0x82] = 2 << 5;
1240
1241 s->csp_regs[5] = 1;
1242 s->csp_regs[9] = 0xf8;
1243
1244 reset_mixer (s);
1245 s->aux_ts = qemu_new_timer (vm_clock, aux_timer, s);
1246 if (!s->aux_ts)
1247 return;
bellard27503322003-11-13 01:46:15 +00001248
1249 for (i = 0; i < LENOFA (dsp_write_ports); i++) {
bellard85571bc2004-11-07 18:04:02 +00001250 register_ioport_write (s->port + dsp_write_ports[i], 1, 1, dsp_write, s);
bellard27503322003-11-13 01:46:15 +00001251 }
1252
1253 for (i = 0; i < LENOFA (dsp_read_ports); i++) {
bellard85571bc2004-11-07 18:04:02 +00001254 register_ioport_read (s->port + dsp_read_ports[i], 1, 1, dsp_read, s);
bellardd75d9f62004-10-09 17:20:54 +00001255 }
1256
bellard85571bc2004-11-07 18:04:02 +00001257 register_ioport_write (s->port + 0x4, 1, 1, mixer_write_indexb, s);
1258 register_ioport_write (s->port + 0x4, 1, 2, mixer_write_indexw, s);
1259 register_ioport_read (s->port + 0x5, 1, 1, mixer_read, s);
1260 register_ioport_write (s->port + 0x5, 1, 1, mixer_write_datab, s);
1261
1262 DMA_register_channel (s->hdma, SB_read_DMA, s);
1263 DMA_register_channel (s->dma, SB_read_DMA, s);
1264 s->can_write = 1;
1265
1266 qemu_mod_timer (s->ts, qemu_get_clock (vm_clock) + 1);
1267 register_savevm ("sb16", 0, 1, SB_save, SB_load, s);
bellard27503322003-11-13 01:46:15 +00001268}