bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Paolo Bonzini | cb9c377 | 2012-12-06 12:15:58 +0100 | [diff] [blame] | 24 | #ifndef TCG_TARGET_I386 |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 25 | #define TCG_TARGET_I386 1 |
| 26 | |
Richard Henderson | f6bff89 | 2014-04-01 08:34:03 -0700 | [diff] [blame] | 27 | #define TCG_TARGET_INSN_UNIT_SIZE 1 |
| 28 | |
Richard Henderson | 78cd7b8 | 2013-08-20 14:41:29 -0700 | [diff] [blame] | 29 | #ifdef __x86_64__ |
| 30 | # define TCG_TARGET_REG_BITS 64 |
| 31 | # define TCG_TARGET_NB_REGS 16 |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 32 | #else |
Richard Henderson | 78cd7b8 | 2013-08-20 14:41:29 -0700 | [diff] [blame] | 33 | # define TCG_TARGET_REG_BITS 32 |
| 34 | # define TCG_TARGET_NB_REGS 8 |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 35 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 36 | |
Richard Henderson | 771142c | 2011-11-09 08:03:33 +0000 | [diff] [blame] | 37 | typedef enum { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 38 | TCG_REG_EAX = 0, |
| 39 | TCG_REG_ECX, |
| 40 | TCG_REG_EDX, |
| 41 | TCG_REG_EBX, |
| 42 | TCG_REG_ESP, |
| 43 | TCG_REG_EBP, |
| 44 | TCG_REG_ESI, |
| 45 | TCG_REG_EDI, |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 46 | |
| 47 | /* 64-bit registers; always define the symbols to avoid |
| 48 | too much if-deffing. */ |
| 49 | TCG_REG_R8, |
| 50 | TCG_REG_R9, |
| 51 | TCG_REG_R10, |
| 52 | TCG_REG_R11, |
| 53 | TCG_REG_R12, |
| 54 | TCG_REG_R13, |
| 55 | TCG_REG_R14, |
| 56 | TCG_REG_R15, |
| 57 | TCG_REG_RAX = TCG_REG_EAX, |
| 58 | TCG_REG_RCX = TCG_REG_ECX, |
| 59 | TCG_REG_RDX = TCG_REG_EDX, |
| 60 | TCG_REG_RBX = TCG_REG_EBX, |
| 61 | TCG_REG_RSP = TCG_REG_ESP, |
| 62 | TCG_REG_RBP = TCG_REG_EBP, |
| 63 | TCG_REG_RSI = TCG_REG_ESI, |
| 64 | TCG_REG_RDI = TCG_REG_EDI, |
Richard Henderson | 771142c | 2011-11-09 08:03:33 +0000 | [diff] [blame] | 65 | } TCGReg; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 66 | |
| 67 | /* used for function call generation */ |
| 68 | #define TCG_REG_CALL_STACK TCG_REG_ESP |
| 69 | #define TCG_TARGET_STACK_ALIGN 16 |
Stefan Weil | 1b7621a | 2012-09-13 19:37:43 +0200 | [diff] [blame] | 70 | #if defined(_WIN64) |
| 71 | #define TCG_TARGET_CALL_STACK_OFFSET 32 |
| 72 | #else |
bellard | 39cf05d | 2008-05-22 14:59:57 +0000 | [diff] [blame] | 73 | #define TCG_TARGET_CALL_STACK_OFFSET 0 |
Stefan Weil | 1b7621a | 2012-09-13 19:37:43 +0200 | [diff] [blame] | 74 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 75 | |
Richard Henderson | 9d2eec2 | 2014-01-27 21:49:17 -0800 | [diff] [blame] | 76 | extern bool have_bmi1; |
| 77 | |
aurel32 | 9619376 | 2009-03-10 19:37:46 +0000 | [diff] [blame] | 78 | /* optional instructions */ |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 79 | #define TCG_TARGET_HAS_div2_i32 1 |
| 80 | #define TCG_TARGET_HAS_rot_i32 1 |
| 81 | #define TCG_TARGET_HAS_ext8s_i32 1 |
| 82 | #define TCG_TARGET_HAS_ext16s_i32 1 |
| 83 | #define TCG_TARGET_HAS_ext8u_i32 1 |
| 84 | #define TCG_TARGET_HAS_ext16u_i32 1 |
| 85 | #define TCG_TARGET_HAS_bswap16_i32 1 |
| 86 | #define TCG_TARGET_HAS_bswap32_i32 1 |
| 87 | #define TCG_TARGET_HAS_neg_i32 1 |
| 88 | #define TCG_TARGET_HAS_not_i32 1 |
Richard Henderson | 9d2eec2 | 2014-01-27 21:49:17 -0800 | [diff] [blame] | 89 | #define TCG_TARGET_HAS_andc_i32 have_bmi1 |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 90 | #define TCG_TARGET_HAS_orc_i32 0 |
| 91 | #define TCG_TARGET_HAS_eqv_i32 0 |
| 92 | #define TCG_TARGET_HAS_nand_i32 0 |
| 93 | #define TCG_TARGET_HAS_nor_i32 0 |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 94 | #define TCG_TARGET_HAS_deposit_i32 1 |
Richard Henderson | d0a1629 | 2012-09-21 10:13:36 -0700 | [diff] [blame] | 95 | #define TCG_TARGET_HAS_movcond_i32 1 |
Richard Henderson | bbc863b | 2013-02-19 23:51:50 -0800 | [diff] [blame] | 96 | #define TCG_TARGET_HAS_add2_i32 1 |
| 97 | #define TCG_TARGET_HAS_sub2_i32 1 |
| 98 | #define TCG_TARGET_HAS_mulu2_i32 1 |
Richard Henderson | 624988a | 2013-02-19 23:51:57 -0800 | [diff] [blame] | 99 | #define TCG_TARGET_HAS_muls2_i32 1 |
Richard Henderson | 0327152 | 2013-08-14 14:35:56 -0700 | [diff] [blame] | 100 | #define TCG_TARGET_HAS_muluh_i32 0 |
| 101 | #define TCG_TARGET_HAS_mulsh_i32 0 |
aurel32 | 9619376 | 2009-03-10 19:37:46 +0000 | [diff] [blame] | 102 | |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 103 | #if TCG_TARGET_REG_BITS == 64 |
Richard Henderson | 4bb7a41 | 2013-09-09 17:03:24 -0700 | [diff] [blame] | 104 | #define TCG_TARGET_HAS_trunc_shr_i32 0 |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 105 | #define TCG_TARGET_HAS_div2_i64 1 |
| 106 | #define TCG_TARGET_HAS_rot_i64 1 |
| 107 | #define TCG_TARGET_HAS_ext8s_i64 1 |
| 108 | #define TCG_TARGET_HAS_ext16s_i64 1 |
| 109 | #define TCG_TARGET_HAS_ext32s_i64 1 |
| 110 | #define TCG_TARGET_HAS_ext8u_i64 1 |
| 111 | #define TCG_TARGET_HAS_ext16u_i64 1 |
| 112 | #define TCG_TARGET_HAS_ext32u_i64 1 |
| 113 | #define TCG_TARGET_HAS_bswap16_i64 1 |
| 114 | #define TCG_TARGET_HAS_bswap32_i64 1 |
| 115 | #define TCG_TARGET_HAS_bswap64_i64 1 |
| 116 | #define TCG_TARGET_HAS_neg_i64 1 |
| 117 | #define TCG_TARGET_HAS_not_i64 1 |
Richard Henderson | 9d2eec2 | 2014-01-27 21:49:17 -0800 | [diff] [blame] | 118 | #define TCG_TARGET_HAS_andc_i64 have_bmi1 |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 119 | #define TCG_TARGET_HAS_orc_i64 0 |
| 120 | #define TCG_TARGET_HAS_eqv_i64 0 |
| 121 | #define TCG_TARGET_HAS_nand_i64 0 |
| 122 | #define TCG_TARGET_HAS_nor_i64 0 |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 123 | #define TCG_TARGET_HAS_deposit_i64 1 |
Richard Henderson | d0a1629 | 2012-09-21 10:13:36 -0700 | [diff] [blame] | 124 | #define TCG_TARGET_HAS_movcond_i64 1 |
Richard Henderson | 624988a | 2013-02-19 23:51:57 -0800 | [diff] [blame] | 125 | #define TCG_TARGET_HAS_add2_i64 1 |
| 126 | #define TCG_TARGET_HAS_sub2_i64 1 |
| 127 | #define TCG_TARGET_HAS_mulu2_i64 1 |
| 128 | #define TCG_TARGET_HAS_muls2_i64 1 |
Richard Henderson | 0327152 | 2013-08-14 14:35:56 -0700 | [diff] [blame] | 129 | #define TCG_TARGET_HAS_muluh_i64 0 |
| 130 | #define TCG_TARGET_HAS_mulsh_i64 0 |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 131 | #endif |
| 132 | |
Richard Henderson | 8221a26 | 2013-09-04 09:35:37 -0700 | [diff] [blame] | 133 | #define TCG_TARGET_HAS_new_ldst 1 |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 134 | |
Jan Kiszka | a477332 | 2011-09-29 18:52:11 +0200 | [diff] [blame] | 135 | #define TCG_TARGET_deposit_i32_valid(ofs, len) \ |
| 136 | (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ |
| 137 | ((ofs) == 0 && (len) == 16)) |
| 138 | #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid |
| 139 | |
Richard Henderson | 5d8a4f8 | 2010-06-03 17:35:17 -0700 | [diff] [blame] | 140 | #if TCG_TARGET_REG_BITS == 64 |
| 141 | # define TCG_AREG0 TCG_REG_R14 |
| 142 | #else |
| 143 | # define TCG_AREG0 TCG_REG_EBP |
| 144 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 145 | |
Richard Henderson | b93949e | 2013-08-20 14:22:50 -0700 | [diff] [blame] | 146 | static inline void flush_icache_range(uintptr_t start, uintptr_t stop) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 147 | { |
| 148 | } |
Paolo Bonzini | cb9c377 | 2012-12-06 12:15:58 +0100 | [diff] [blame] | 149 | |
| 150 | #endif |