bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 2 | * virtual page mapping and translated block handling |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 20 | #include "config.h" |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 21 | #ifdef _WIN32 |
ths | 4fddf62 | 2007-12-17 04:42:29 +0000 | [diff] [blame] | 22 | #define WIN32_LEAN_AND_MEAN |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 23 | #include <windows.h> |
| 24 | #else |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 25 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 26 | #include <sys/mman.h> |
| 27 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 28 | #include <stdlib.h> |
| 29 | #include <stdio.h> |
| 30 | #include <stdarg.h> |
| 31 | #include <string.h> |
| 32 | #include <errno.h> |
| 33 | #include <unistd.h> |
| 34 | #include <inttypes.h> |
| 35 | |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 36 | #include "cpu.h" |
| 37 | #include "exec-all.h" |
aurel32 | ca10f86 | 2008-04-11 21:35:42 +0000 | [diff] [blame] | 38 | #include "qemu-common.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 39 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 40 | #include "hw/hw.h" |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 41 | #include "osdep.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 42 | #include "kvm.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 43 | #if defined(CONFIG_USER_ONLY) |
| 44 | #include <qemu.h> |
| 45 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 46 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 47 | //#define DEBUG_TB_INVALIDATE |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 48 | //#define DEBUG_FLUSH |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 49 | //#define DEBUG_TLB |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 50 | //#define DEBUG_UNASSIGNED |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 51 | |
| 52 | /* make various TB consistency checks */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 53 | //#define DEBUG_TB_CHECK |
| 54 | //#define DEBUG_TLB_CHECK |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 55 | |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 56 | //#define DEBUG_IOPORT |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 57 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 58 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 59 | #if !defined(CONFIG_USER_ONLY) |
| 60 | /* TB consistency checks only implemented for usermode emulation. */ |
| 61 | #undef DEBUG_TB_CHECK |
| 62 | #endif |
| 63 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 64 | #define SMC_BITMAP_USE_THRESHOLD 10 |
| 65 | |
| 66 | #define MMAP_AREA_START 0x00000000 |
| 67 | #define MMAP_AREA_END 0xa8000000 |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 68 | |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 69 | #if defined(TARGET_SPARC64) |
| 70 | #define TARGET_PHYS_ADDR_SPACE_BITS 41 |
blueswir1 | 5dcb6b9 | 2007-05-19 12:58:30 +0000 | [diff] [blame] | 71 | #elif defined(TARGET_SPARC) |
| 72 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 73 | #elif defined(TARGET_ALPHA) |
| 74 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
| 75 | #define TARGET_VIRT_ADDR_SPACE_BITS 42 |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 76 | #elif defined(TARGET_PPC64) |
| 77 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 78 | #elif defined(TARGET_X86_64) && !defined(USE_KQEMU) |
| 79 | #define TARGET_PHYS_ADDR_SPACE_BITS 42 |
| 80 | #elif defined(TARGET_I386) && !defined(USE_KQEMU) |
| 81 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 82 | #else |
| 83 | /* Note: for compatibility with kqemu, we use 32 bits for x86_64 */ |
| 84 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
| 85 | #endif |
| 86 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 87 | static TranslationBlock *tbs; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 88 | int code_gen_max_blocks; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 89 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 90 | static int nb_tbs; |
bellard | eb51d10 | 2003-05-14 21:51:13 +0000 | [diff] [blame] | 91 | /* any access to the tbs or the page table must use this lock */ |
| 92 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 93 | |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 94 | #if defined(__arm__) || defined(__sparc_v9__) |
| 95 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 |
| 96 | have limited branch ranges (possibly also PPC) so place it in a |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 97 | section close to code segment. */ |
| 98 | #define code_gen_section \ |
| 99 | __attribute__((__section__(".gen_code"))) \ |
| 100 | __attribute__((aligned (32))) |
| 101 | #else |
| 102 | #define code_gen_section \ |
| 103 | __attribute__((aligned (32))) |
| 104 | #endif |
| 105 | |
| 106 | uint8_t code_gen_prologue[1024] code_gen_section; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 107 | static uint8_t *code_gen_buffer; |
| 108 | static unsigned long code_gen_buffer_size; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 109 | /* threshold to flush the translated code buffer */ |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 110 | static unsigned long code_gen_buffer_max_size; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 111 | uint8_t *code_gen_ptr; |
| 112 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 113 | #if !defined(CONFIG_USER_ONLY) |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 114 | ram_addr_t phys_ram_size; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 115 | int phys_ram_fd; |
| 116 | uint8_t *phys_ram_base; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 117 | uint8_t *phys_ram_dirty; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 118 | static int in_migration; |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 119 | static ram_addr_t phys_ram_alloc_offset = 0; |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 120 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 121 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 122 | CPUState *first_cpu; |
| 123 | /* current CPU in the current thread. It is only valid inside |
| 124 | cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 125 | CPUState *cpu_single_env; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 126 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 127 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 128 | 2 = Adaptive rate instruction counting. */ |
| 129 | int use_icount = 0; |
| 130 | /* Current instruction counter. While executing translated code this may |
| 131 | include some instructions that have not yet been executed. */ |
| 132 | int64_t qemu_icount; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 133 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 134 | typedef struct PageDesc { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 135 | /* list of TBs intersecting this ram page */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 136 | TranslationBlock *first_tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 137 | /* in order to optimize self modifying code, we count the number |
| 138 | of lookups we do to a given page to use a bitmap */ |
| 139 | unsigned int code_write_count; |
| 140 | uint8_t *code_bitmap; |
| 141 | #if defined(CONFIG_USER_ONLY) |
| 142 | unsigned long flags; |
| 143 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 144 | } PageDesc; |
| 145 | |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 146 | typedef struct PhysPageDesc { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 147 | /* offset in host memory of the page + io_index in the low bits */ |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 148 | ram_addr_t phys_offset; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 149 | } PhysPageDesc; |
| 150 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 151 | #define L2_BITS 10 |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 152 | #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS) |
| 153 | /* XXX: this is a temporary hack for alpha target. |
| 154 | * In the future, this is to be replaced by a multi-level table |
| 155 | * to actually be able to handle the complete 64 bits address space. |
| 156 | */ |
| 157 | #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS) |
| 158 | #else |
aurel32 | 0387544 | 2008-04-22 20:45:18 +0000 | [diff] [blame] | 159 | #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS) |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 160 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 161 | |
| 162 | #define L1_SIZE (1 << L1_BITS) |
| 163 | #define L2_SIZE (1 << L2_BITS) |
| 164 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 165 | unsigned long qemu_real_host_page_size; |
| 166 | unsigned long qemu_host_page_bits; |
| 167 | unsigned long qemu_host_page_size; |
| 168 | unsigned long qemu_host_page_mask; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 169 | |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 170 | /* XXX: for system emulation, it could just be an array */ |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 171 | static PageDesc *l1_map[L1_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 172 | static PhysPageDesc **l1_phys_map; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 173 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 174 | #if !defined(CONFIG_USER_ONLY) |
| 175 | static void io_mem_init(void); |
| 176 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 177 | /* io memory support */ |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 178 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 179 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 180 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 181 | static int io_mem_nb; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 182 | static int io_mem_watch; |
| 183 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 184 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 185 | /* log support */ |
blueswir1 | d9b630f | 2008-10-05 09:57:08 +0000 | [diff] [blame] | 186 | static const char *logfilename = "/tmp/qemu.log"; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 187 | FILE *logfile; |
| 188 | int loglevel; |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 189 | static int log_append = 0; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 190 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 191 | /* statistics */ |
| 192 | static int tlb_flush_count; |
| 193 | static int tb_flush_count; |
| 194 | static int tb_phys_invalidate_count; |
| 195 | |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 196 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 197 | typedef struct subpage_t { |
| 198 | target_phys_addr_t base; |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 199 | CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4]; |
| 200 | CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4]; |
| 201 | void *opaque[TARGET_PAGE_SIZE][2][4]; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 202 | } subpage_t; |
| 203 | |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 204 | #ifdef _WIN32 |
| 205 | static void map_exec(void *addr, long size) |
| 206 | { |
| 207 | DWORD old_protect; |
| 208 | VirtualProtect(addr, size, |
| 209 | PAGE_EXECUTE_READWRITE, &old_protect); |
| 210 | |
| 211 | } |
| 212 | #else |
| 213 | static void map_exec(void *addr, long size) |
| 214 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 215 | unsigned long start, end, page_size; |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 216 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 217 | page_size = getpagesize(); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 218 | start = (unsigned long)addr; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 219 | start &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 220 | |
| 221 | end = (unsigned long)addr + size; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 222 | end += page_size - 1; |
| 223 | end &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 224 | |
| 225 | mprotect((void *)start, end - start, |
| 226 | PROT_READ | PROT_WRITE | PROT_EXEC); |
| 227 | } |
| 228 | #endif |
| 229 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 230 | static void page_init(void) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 231 | { |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 232 | /* NOTE: we can always suppose that qemu_host_page_size >= |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 233 | TARGET_PAGE_SIZE */ |
aliguori | c2b48b6 | 2008-11-11 22:06:42 +0000 | [diff] [blame] | 234 | #ifdef _WIN32 |
| 235 | { |
| 236 | SYSTEM_INFO system_info; |
| 237 | |
| 238 | GetSystemInfo(&system_info); |
| 239 | qemu_real_host_page_size = system_info.dwPageSize; |
| 240 | } |
| 241 | #else |
| 242 | qemu_real_host_page_size = getpagesize(); |
| 243 | #endif |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 244 | if (qemu_host_page_size == 0) |
| 245 | qemu_host_page_size = qemu_real_host_page_size; |
| 246 | if (qemu_host_page_size < TARGET_PAGE_SIZE) |
| 247 | qemu_host_page_size = TARGET_PAGE_SIZE; |
| 248 | qemu_host_page_bits = 0; |
| 249 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) |
| 250 | qemu_host_page_bits++; |
| 251 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 252 | l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *)); |
| 253 | memset(l1_phys_map, 0, L1_SIZE * sizeof(void *)); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 254 | |
| 255 | #if !defined(_WIN32) && defined(CONFIG_USER_ONLY) |
| 256 | { |
| 257 | long long startaddr, endaddr; |
| 258 | FILE *f; |
| 259 | int n; |
| 260 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 261 | mmap_lock(); |
pbrook | 0776590 | 2008-05-31 16:33:53 +0000 | [diff] [blame] | 262 | last_brk = (unsigned long)sbrk(0); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 263 | f = fopen("/proc/self/maps", "r"); |
| 264 | if (f) { |
| 265 | do { |
| 266 | n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr); |
| 267 | if (n == 2) { |
blueswir1 | e0b8d65 | 2008-05-03 17:51:24 +0000 | [diff] [blame] | 268 | startaddr = MIN(startaddr, |
| 269 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); |
| 270 | endaddr = MIN(endaddr, |
| 271 | (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1); |
pbrook | b5fc909 | 2008-05-29 13:56:10 +0000 | [diff] [blame] | 272 | page_set_flags(startaddr & TARGET_PAGE_MASK, |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 273 | TARGET_PAGE_ALIGN(endaddr), |
| 274 | PAGE_RESERVED); |
| 275 | } |
| 276 | } while (!feof(f)); |
| 277 | fclose(f); |
| 278 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 279 | mmap_unlock(); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 280 | } |
| 281 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 282 | } |
| 283 | |
aliguori | 434929b | 2008-09-15 15:56:30 +0000 | [diff] [blame] | 284 | static inline PageDesc **page_l1_map(target_ulong index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 285 | { |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 286 | #if TARGET_LONG_BITS > 32 |
| 287 | /* Host memory outside guest VM. For 32-bit targets we have already |
| 288 | excluded high addresses. */ |
ths | d8173e0 | 2008-08-29 13:10:00 +0000 | [diff] [blame] | 289 | if (index > ((target_ulong)L2_SIZE * L1_SIZE)) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 290 | return NULL; |
| 291 | #endif |
aliguori | 434929b | 2008-09-15 15:56:30 +0000 | [diff] [blame] | 292 | return &l1_map[index >> L2_BITS]; |
| 293 | } |
| 294 | |
| 295 | static inline PageDesc *page_find_alloc(target_ulong index) |
| 296 | { |
| 297 | PageDesc **lp, *p; |
| 298 | lp = page_l1_map(index); |
| 299 | if (!lp) |
| 300 | return NULL; |
| 301 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 302 | p = *lp; |
| 303 | if (!p) { |
| 304 | /* allocate if not found */ |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 305 | #if defined(CONFIG_USER_ONLY) |
| 306 | unsigned long addr; |
| 307 | size_t len = sizeof(PageDesc) * L2_SIZE; |
| 308 | /* Don't use qemu_malloc because it may recurse. */ |
| 309 | p = mmap(0, len, PROT_READ | PROT_WRITE, |
| 310 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 311 | *lp = p; |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 312 | addr = h2g(p); |
| 313 | if (addr == (target_ulong)addr) { |
| 314 | page_set_flags(addr & TARGET_PAGE_MASK, |
| 315 | TARGET_PAGE_ALIGN(addr + len), |
| 316 | PAGE_RESERVED); |
| 317 | } |
| 318 | #else |
| 319 | p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE); |
| 320 | *lp = p; |
| 321 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 322 | } |
| 323 | return p + (index & (L2_SIZE - 1)); |
| 324 | } |
| 325 | |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 326 | static inline PageDesc *page_find(target_ulong index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 327 | { |
aliguori | 434929b | 2008-09-15 15:56:30 +0000 | [diff] [blame] | 328 | PageDesc **lp, *p; |
| 329 | lp = page_l1_map(index); |
| 330 | if (!lp) |
| 331 | return NULL; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 332 | |
aliguori | 434929b | 2008-09-15 15:56:30 +0000 | [diff] [blame] | 333 | p = *lp; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 334 | if (!p) |
| 335 | return 0; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 336 | return p + (index & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 337 | } |
| 338 | |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 339 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 340 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 341 | void **lp, **p; |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 342 | PhysPageDesc *pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 343 | |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 344 | p = (void **)l1_phys_map; |
| 345 | #if TARGET_PHYS_ADDR_SPACE_BITS > 32 |
| 346 | |
| 347 | #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS) |
| 348 | #error unsupported TARGET_PHYS_ADDR_SPACE_BITS |
| 349 | #endif |
| 350 | lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1)); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 351 | p = *lp; |
| 352 | if (!p) { |
| 353 | /* allocate if not found */ |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 354 | if (!alloc) |
| 355 | return NULL; |
| 356 | p = qemu_vmalloc(sizeof(void *) * L1_SIZE); |
| 357 | memset(p, 0, sizeof(void *) * L1_SIZE); |
| 358 | *lp = p; |
| 359 | } |
| 360 | #endif |
| 361 | lp = p + ((index >> L2_BITS) & (L1_SIZE - 1)); |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 362 | pd = *lp; |
| 363 | if (!pd) { |
| 364 | int i; |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 365 | /* allocate if not found */ |
| 366 | if (!alloc) |
| 367 | return NULL; |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 368 | pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE); |
| 369 | *lp = pd; |
| 370 | for (i = 0; i < L2_SIZE; i++) |
| 371 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 372 | } |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 373 | return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1)); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 374 | } |
| 375 | |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 376 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 377 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 378 | return phys_page_find_alloc(index, 0); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 379 | } |
| 380 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 381 | #if !defined(CONFIG_USER_ONLY) |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 382 | static void tlb_protect_code(ram_addr_t ram_addr); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 383 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 384 | target_ulong vaddr); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 385 | #define mmap_lock() do { } while(0) |
| 386 | #define mmap_unlock() do { } while(0) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 387 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 388 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 389 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
| 390 | |
| 391 | #if defined(CONFIG_USER_ONLY) |
| 392 | /* Currently it is not recommanded to allocate big chunks of data in |
| 393 | user mode. It will change when a dedicated libc will be used */ |
| 394 | #define USE_STATIC_CODE_GEN_BUFFER |
| 395 | #endif |
| 396 | |
| 397 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 398 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]; |
| 399 | #endif |
| 400 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 401 | static void code_gen_alloc(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 402 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 403 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 404 | code_gen_buffer = static_code_gen_buffer; |
| 405 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 406 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 407 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 408 | code_gen_buffer_size = tb_size; |
| 409 | if (code_gen_buffer_size == 0) { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 410 | #if defined(CONFIG_USER_ONLY) |
| 411 | /* in user mode, phys_ram_size is not meaningful */ |
| 412 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 413 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 414 | /* XXX: needs ajustments */ |
aliguori | 174a9a1 | 2008-09-24 14:10:36 +0000 | [diff] [blame] | 415 | code_gen_buffer_size = (unsigned long)(phys_ram_size / 4); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 416 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 417 | } |
| 418 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) |
| 419 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; |
| 420 | /* The code gen buffer location may have constraints depending on |
| 421 | the host cpu and OS */ |
| 422 | #if defined(__linux__) |
| 423 | { |
| 424 | int flags; |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 425 | void *start = NULL; |
| 426 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 427 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 428 | #if defined(__x86_64__) |
| 429 | flags |= MAP_32BIT; |
| 430 | /* Cannot map more than that */ |
| 431 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 432 | code_gen_buffer_size = (800 * 1024 * 1024); |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 433 | #elif defined(__sparc_v9__) |
| 434 | // Map the buffer below 2G, so we can use direct calls and branches |
| 435 | flags |= MAP_FIXED; |
| 436 | start = (void *) 0x60000000UL; |
| 437 | if (code_gen_buffer_size > (512 * 1024 * 1024)) |
| 438 | code_gen_buffer_size = (512 * 1024 * 1024); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 439 | #endif |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 440 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
| 441 | PROT_WRITE | PROT_READ | PROT_EXEC, |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 442 | flags, -1, 0); |
| 443 | if (code_gen_buffer == MAP_FAILED) { |
| 444 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 445 | exit(1); |
| 446 | } |
| 447 | } |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 448 | #elif defined(__FreeBSD__) |
| 449 | { |
| 450 | int flags; |
| 451 | void *addr = NULL; |
| 452 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 453 | #if defined(__x86_64__) |
| 454 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume |
| 455 | * 0x40000000 is free */ |
| 456 | flags |= MAP_FIXED; |
| 457 | addr = (void *)0x40000000; |
| 458 | /* Cannot map more than that */ |
| 459 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 460 | code_gen_buffer_size = (800 * 1024 * 1024); |
| 461 | #endif |
| 462 | code_gen_buffer = mmap(addr, code_gen_buffer_size, |
| 463 | PROT_WRITE | PROT_READ | PROT_EXEC, |
| 464 | flags, -1, 0); |
| 465 | if (code_gen_buffer == MAP_FAILED) { |
| 466 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 467 | exit(1); |
| 468 | } |
| 469 | } |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 470 | #else |
| 471 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); |
| 472 | if (!code_gen_buffer) { |
| 473 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 474 | exit(1); |
| 475 | } |
| 476 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 477 | #endif |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 478 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 479 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
| 480 | code_gen_buffer_max_size = code_gen_buffer_size - |
| 481 | code_gen_max_block_size(); |
| 482 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
| 483 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
| 484 | } |
| 485 | |
| 486 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
| 487 | (in bytes) allocated to the translation buffer. Zero means default |
| 488 | size. */ |
| 489 | void cpu_exec_init_all(unsigned long tb_size) |
| 490 | { |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 491 | cpu_gen_init(); |
| 492 | code_gen_alloc(tb_size); |
| 493 | code_gen_ptr = code_gen_buffer; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 494 | page_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 495 | #if !defined(CONFIG_USER_ONLY) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 496 | io_mem_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 497 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 498 | } |
| 499 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 500 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
| 501 | |
| 502 | #define CPU_COMMON_SAVE_VERSION 1 |
| 503 | |
| 504 | static void cpu_common_save(QEMUFile *f, void *opaque) |
| 505 | { |
| 506 | CPUState *env = opaque; |
| 507 | |
| 508 | qemu_put_be32s(f, &env->halted); |
| 509 | qemu_put_be32s(f, &env->interrupt_request); |
| 510 | } |
| 511 | |
| 512 | static int cpu_common_load(QEMUFile *f, void *opaque, int version_id) |
| 513 | { |
| 514 | CPUState *env = opaque; |
| 515 | |
| 516 | if (version_id != CPU_COMMON_SAVE_VERSION) |
| 517 | return -EINVAL; |
| 518 | |
| 519 | qemu_get_be32s(f, &env->halted); |
pbrook | 75f482a | 2008-07-01 21:53:33 +0000 | [diff] [blame] | 520 | qemu_get_be32s(f, &env->interrupt_request); |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 521 | tlb_flush(env, 1); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | #endif |
| 526 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 527 | void cpu_exec_init(CPUState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 528 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 529 | CPUState **penv; |
| 530 | int cpu_index; |
| 531 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 532 | env->next_cpu = NULL; |
| 533 | penv = &first_cpu; |
| 534 | cpu_index = 0; |
| 535 | while (*penv != NULL) { |
| 536 | penv = (CPUState **)&(*penv)->next_cpu; |
| 537 | cpu_index++; |
| 538 | } |
| 539 | env->cpu_index = cpu_index; |
| 540 | *penv = env; |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 541 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 542 | register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION, |
| 543 | cpu_common_save, cpu_common_load, env); |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 544 | register_savevm("cpu", cpu_index, CPU_SAVE_VERSION, |
| 545 | cpu_save, cpu_load, env); |
| 546 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 547 | } |
| 548 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 549 | static inline void invalidate_page_bitmap(PageDesc *p) |
| 550 | { |
| 551 | if (p->code_bitmap) { |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 552 | qemu_free(p->code_bitmap); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 553 | p->code_bitmap = NULL; |
| 554 | } |
| 555 | p->code_write_count = 0; |
| 556 | } |
| 557 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 558 | /* set to NULL all the 'first_tb' fields in all PageDescs */ |
| 559 | static void page_flush_tb(void) |
| 560 | { |
| 561 | int i, j; |
| 562 | PageDesc *p; |
| 563 | |
| 564 | for(i = 0; i < L1_SIZE; i++) { |
| 565 | p = l1_map[i]; |
| 566 | if (p) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 567 | for(j = 0; j < L2_SIZE; j++) { |
| 568 | p->first_tb = NULL; |
| 569 | invalidate_page_bitmap(p); |
| 570 | p++; |
| 571 | } |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 572 | } |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | /* flush all the translation blocks */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 577 | /* XXX: tb_flush is currently not thread safe */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 578 | void tb_flush(CPUState *env1) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 579 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 580 | CPUState *env; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 581 | #if defined(DEBUG_FLUSH) |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 582 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
| 583 | (unsigned long)(code_gen_ptr - code_gen_buffer), |
| 584 | nb_tbs, nb_tbs > 0 ? |
| 585 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 586 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 587 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 588 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
| 589 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 590 | nb_tbs = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 591 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 592 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 593 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
| 594 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 595 | |
bellard | 8a8a608 | 2004-10-03 13:36:49 +0000 | [diff] [blame] | 596 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 597 | page_flush_tb(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 598 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 599 | code_gen_ptr = code_gen_buffer; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 600 | /* XXX: flush processor icache at this point if cache flush is |
| 601 | expensive */ |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 602 | tb_flush_count++; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 603 | } |
| 604 | |
| 605 | #ifdef DEBUG_TB_CHECK |
| 606 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 607 | static void tb_invalidate_check(target_ulong address) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 608 | { |
| 609 | TranslationBlock *tb; |
| 610 | int i; |
| 611 | address &= TARGET_PAGE_MASK; |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 612 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 613 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 614 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
| 615 | address >= tb->pc + tb->size)) { |
| 616 | printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 617 | address, (long)tb->pc, tb->size); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 618 | } |
| 619 | } |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | /* verify that all the pages have correct rights for code */ |
| 624 | static void tb_page_check(void) |
| 625 | { |
| 626 | TranslationBlock *tb; |
| 627 | int i, flags1, flags2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 628 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 629 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 630 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 631 | flags1 = page_get_flags(tb->pc); |
| 632 | flags2 = page_get_flags(tb->pc + tb->size - 1); |
| 633 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { |
| 634 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 635 | (long)tb->pc, tb->size, flags1, flags2); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 636 | } |
| 637 | } |
| 638 | } |
| 639 | } |
| 640 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 641 | static void tb_jmp_check(TranslationBlock *tb) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 642 | { |
| 643 | TranslationBlock *tb1; |
| 644 | unsigned int n1; |
| 645 | |
| 646 | /* suppress any remaining jumps to this TB */ |
| 647 | tb1 = tb->jmp_first; |
| 648 | for(;;) { |
| 649 | n1 = (long)tb1 & 3; |
| 650 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 651 | if (n1 == 2) |
| 652 | break; |
| 653 | tb1 = tb1->jmp_next[n1]; |
| 654 | } |
| 655 | /* check end of list */ |
| 656 | if (tb1 != tb) { |
| 657 | printf("ERROR: jmp_list from 0x%08lx\n", (long)tb); |
| 658 | } |
| 659 | } |
| 660 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 661 | #endif |
| 662 | |
| 663 | /* invalidate one TB */ |
| 664 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, |
| 665 | int next_offset) |
| 666 | { |
| 667 | TranslationBlock *tb1; |
| 668 | for(;;) { |
| 669 | tb1 = *ptb; |
| 670 | if (tb1 == tb) { |
| 671 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); |
| 672 | break; |
| 673 | } |
| 674 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); |
| 675 | } |
| 676 | } |
| 677 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 678 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
| 679 | { |
| 680 | TranslationBlock *tb1; |
| 681 | unsigned int n1; |
| 682 | |
| 683 | for(;;) { |
| 684 | tb1 = *ptb; |
| 685 | n1 = (long)tb1 & 3; |
| 686 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 687 | if (tb1 == tb) { |
| 688 | *ptb = tb1->page_next[n1]; |
| 689 | break; |
| 690 | } |
| 691 | ptb = &tb1->page_next[n1]; |
| 692 | } |
| 693 | } |
| 694 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 695 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
| 696 | { |
| 697 | TranslationBlock *tb1, **ptb; |
| 698 | unsigned int n1; |
| 699 | |
| 700 | ptb = &tb->jmp_next[n]; |
| 701 | tb1 = *ptb; |
| 702 | if (tb1) { |
| 703 | /* find tb(n) in circular list */ |
| 704 | for(;;) { |
| 705 | tb1 = *ptb; |
| 706 | n1 = (long)tb1 & 3; |
| 707 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 708 | if (n1 == n && tb1 == tb) |
| 709 | break; |
| 710 | if (n1 == 2) { |
| 711 | ptb = &tb1->jmp_first; |
| 712 | } else { |
| 713 | ptb = &tb1->jmp_next[n1]; |
| 714 | } |
| 715 | } |
| 716 | /* now we can suppress tb(n) from the list */ |
| 717 | *ptb = tb->jmp_next[n]; |
| 718 | |
| 719 | tb->jmp_next[n] = NULL; |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | /* reset the jump entry 'n' of a TB so that it is not chained to |
| 724 | another TB */ |
| 725 | static inline void tb_reset_jump(TranslationBlock *tb, int n) |
| 726 | { |
| 727 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); |
| 728 | } |
| 729 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 730 | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 731 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 732 | CPUState *env; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 733 | PageDesc *p; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 734 | unsigned int h, n1; |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 735 | target_phys_addr_t phys_pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 736 | TranslationBlock *tb1, *tb2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 737 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 738 | /* remove the TB from the hash list */ |
| 739 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 740 | h = tb_phys_hash_func(phys_pc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 741 | tb_remove(&tb_phys_hash[h], tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 742 | offsetof(TranslationBlock, phys_hash_next)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 743 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 744 | /* remove the TB from the page list */ |
| 745 | if (tb->page_addr[0] != page_addr) { |
| 746 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); |
| 747 | tb_page_remove(&p->first_tb, tb); |
| 748 | invalidate_page_bitmap(p); |
| 749 | } |
| 750 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { |
| 751 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); |
| 752 | tb_page_remove(&p->first_tb, tb); |
| 753 | invalidate_page_bitmap(p); |
| 754 | } |
| 755 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 756 | tb_invalidated_flag = 1; |
| 757 | |
| 758 | /* remove the TB from the hash list */ |
| 759 | h = tb_jmp_cache_hash_func(tb->pc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 760 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 761 | if (env->tb_jmp_cache[h] == tb) |
| 762 | env->tb_jmp_cache[h] = NULL; |
| 763 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 764 | |
| 765 | /* suppress this TB from the two jump lists */ |
| 766 | tb_jmp_remove(tb, 0); |
| 767 | tb_jmp_remove(tb, 1); |
| 768 | |
| 769 | /* suppress any remaining jumps to this TB */ |
| 770 | tb1 = tb->jmp_first; |
| 771 | for(;;) { |
| 772 | n1 = (long)tb1 & 3; |
| 773 | if (n1 == 2) |
| 774 | break; |
| 775 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 776 | tb2 = tb1->jmp_next[n1]; |
| 777 | tb_reset_jump(tb1, n1); |
| 778 | tb1->jmp_next[n1] = NULL; |
| 779 | tb1 = tb2; |
| 780 | } |
| 781 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ |
| 782 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 783 | tb_phys_invalidate_count++; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 784 | } |
| 785 | |
| 786 | static inline void set_bits(uint8_t *tab, int start, int len) |
| 787 | { |
| 788 | int end, mask, end1; |
| 789 | |
| 790 | end = start + len; |
| 791 | tab += start >> 3; |
| 792 | mask = 0xff << (start & 7); |
| 793 | if ((start & ~7) == (end & ~7)) { |
| 794 | if (start < end) { |
| 795 | mask &= ~(0xff << (end & 7)); |
| 796 | *tab |= mask; |
| 797 | } |
| 798 | } else { |
| 799 | *tab++ |= mask; |
| 800 | start = (start + 8) & ~7; |
| 801 | end1 = end & ~7; |
| 802 | while (start < end1) { |
| 803 | *tab++ = 0xff; |
| 804 | start += 8; |
| 805 | } |
| 806 | if (start < end) { |
| 807 | mask = ~(0xff << (end & 7)); |
| 808 | *tab |= mask; |
| 809 | } |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | static void build_page_bitmap(PageDesc *p) |
| 814 | { |
| 815 | int n, tb_start, tb_end; |
| 816 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 817 | |
pbrook | b2a7081 | 2008-06-09 13:57:23 +0000 | [diff] [blame] | 818 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 819 | if (!p->code_bitmap) |
| 820 | return; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 821 | |
| 822 | tb = p->first_tb; |
| 823 | while (tb != NULL) { |
| 824 | n = (long)tb & 3; |
| 825 | tb = (TranslationBlock *)((long)tb & ~3); |
| 826 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 827 | if (n == 0) { |
| 828 | /* NOTE: tb_end may be after the end of the page, but |
| 829 | it is not a problem */ |
| 830 | tb_start = tb->pc & ~TARGET_PAGE_MASK; |
| 831 | tb_end = tb_start + tb->size; |
| 832 | if (tb_end > TARGET_PAGE_SIZE) |
| 833 | tb_end = TARGET_PAGE_SIZE; |
| 834 | } else { |
| 835 | tb_start = 0; |
| 836 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 837 | } |
| 838 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); |
| 839 | tb = tb->page_next[n]; |
| 840 | } |
| 841 | } |
| 842 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 843 | TranslationBlock *tb_gen_code(CPUState *env, |
| 844 | target_ulong pc, target_ulong cs_base, |
| 845 | int flags, int cflags) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 846 | { |
| 847 | TranslationBlock *tb; |
| 848 | uint8_t *tc_ptr; |
| 849 | target_ulong phys_pc, phys_page2, virt_page2; |
| 850 | int code_gen_size; |
| 851 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 852 | phys_pc = get_phys_addr_code(env, pc); |
| 853 | tb = tb_alloc(pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 854 | if (!tb) { |
| 855 | /* flush must be done */ |
| 856 | tb_flush(env); |
| 857 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 858 | tb = tb_alloc(pc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 859 | /* Don't forget to invalidate previous TB info. */ |
| 860 | tb_invalidated_flag = 1; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 861 | } |
| 862 | tc_ptr = code_gen_ptr; |
| 863 | tb->tc_ptr = tc_ptr; |
| 864 | tb->cs_base = cs_base; |
| 865 | tb->flags = flags; |
| 866 | tb->cflags = cflags; |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 867 | cpu_gen_code(env, tb, &code_gen_size); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 868 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 869 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 870 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 871 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 872 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 873 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 874 | phys_page2 = get_phys_addr_code(env, virt_page2); |
| 875 | } |
| 876 | tb_link_phys(tb, phys_pc, phys_page2); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 877 | return tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 878 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 879 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 880 | /* invalidate all TBs which intersect with the target physical page |
| 881 | starting in range [start;end[. NOTE: start and end must refer to |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 882 | the same physical page. 'is_cpu_write_access' should be true if called |
| 883 | from a real cpu write access: the virtual CPU will exit the current |
| 884 | TB if code is modified inside this TB. */ |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 885 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 886 | int is_cpu_write_access) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 887 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 888 | TranslationBlock *tb, *tb_next, *saved_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 889 | CPUState *env = cpu_single_env; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 890 | target_ulong tb_start, tb_end; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 891 | PageDesc *p; |
| 892 | int n; |
| 893 | #ifdef TARGET_HAS_PRECISE_SMC |
| 894 | int current_tb_not_found = is_cpu_write_access; |
| 895 | TranslationBlock *current_tb = NULL; |
| 896 | int current_tb_modified = 0; |
| 897 | target_ulong current_pc = 0; |
| 898 | target_ulong current_cs_base = 0; |
| 899 | int current_flags = 0; |
| 900 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 901 | |
| 902 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 903 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 904 | return; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 905 | if (!p->code_bitmap && |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 906 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
| 907 | is_cpu_write_access) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 908 | /* build code bitmap */ |
| 909 | build_page_bitmap(p); |
| 910 | } |
| 911 | |
| 912 | /* we remove all the TBs in the range [start, end[ */ |
| 913 | /* XXX: see if in some cases it could be faster to invalidate all the code */ |
| 914 | tb = p->first_tb; |
| 915 | while (tb != NULL) { |
| 916 | n = (long)tb & 3; |
| 917 | tb = (TranslationBlock *)((long)tb & ~3); |
| 918 | tb_next = tb->page_next[n]; |
| 919 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 920 | if (n == 0) { |
| 921 | /* NOTE: tb_end may be after the end of the page, but |
| 922 | it is not a problem */ |
| 923 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 924 | tb_end = tb_start + tb->size; |
| 925 | } else { |
| 926 | tb_start = tb->page_addr[1]; |
| 927 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 928 | } |
| 929 | if (!(tb_end <= start || tb_start >= end)) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 930 | #ifdef TARGET_HAS_PRECISE_SMC |
| 931 | if (current_tb_not_found) { |
| 932 | current_tb_not_found = 0; |
| 933 | current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 934 | if (env->mem_io_pc) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 935 | /* now we have a real cpu fault */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 936 | current_tb = tb_find_pc(env->mem_io_pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 937 | } |
| 938 | } |
| 939 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 940 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 941 | /* If we are modifying the current TB, we must stop |
| 942 | its execution. We could be more precise by checking |
| 943 | that the modification is after the current PC, but it |
| 944 | would require a specialized function to partially |
| 945 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 946 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 947 | current_tb_modified = 1; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 948 | cpu_restore_state(current_tb, env, |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 949 | env->mem_io_pc, NULL); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 950 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 951 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 952 | } |
| 953 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 954 | /* we need to do that to handle the case where a signal |
| 955 | occurs while doing tb_phys_invalidate() */ |
| 956 | saved_tb = NULL; |
| 957 | if (env) { |
| 958 | saved_tb = env->current_tb; |
| 959 | env->current_tb = NULL; |
| 960 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 961 | tb_phys_invalidate(tb, -1); |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 962 | if (env) { |
| 963 | env->current_tb = saved_tb; |
| 964 | if (env->interrupt_request && env->current_tb) |
| 965 | cpu_interrupt(env, env->interrupt_request); |
| 966 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 967 | } |
| 968 | tb = tb_next; |
| 969 | } |
| 970 | #if !defined(CONFIG_USER_ONLY) |
| 971 | /* if no code remaining, no need to continue to use slow writes */ |
| 972 | if (!p->first_tb) { |
| 973 | invalidate_page_bitmap(p); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 974 | if (is_cpu_write_access) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 975 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 976 | } |
| 977 | } |
| 978 | #endif |
| 979 | #ifdef TARGET_HAS_PRECISE_SMC |
| 980 | if (current_tb_modified) { |
| 981 | /* we generate a block containing just the instruction |
| 982 | modifying the memory. It will ensure that it cannot modify |
| 983 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 984 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 985 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 986 | cpu_resume_from_signal(env, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 987 | } |
| 988 | #endif |
| 989 | } |
| 990 | |
| 991 | /* len must be <= 8 and start must be a multiple of len */ |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 992 | static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 993 | { |
| 994 | PageDesc *p; |
| 995 | int offset, b; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 996 | #if 0 |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 997 | if (1) { |
| 998 | if (loglevel) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 999 | fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1000 | cpu_single_env->mem_io_vaddr, len, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1001 | cpu_single_env->eip, |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 1002 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
| 1003 | } |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1004 | } |
| 1005 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1006 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1007 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1008 | return; |
| 1009 | if (p->code_bitmap) { |
| 1010 | offset = start & ~TARGET_PAGE_MASK; |
| 1011 | b = p->code_bitmap[offset >> 3] >> (offset & 7); |
| 1012 | if (b & ((1 << len) - 1)) |
| 1013 | goto do_invalidate; |
| 1014 | } else { |
| 1015 | do_invalidate: |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1016 | tb_invalidate_phys_page_range(start, start + len, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1017 | } |
| 1018 | } |
| 1019 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1020 | #if !defined(CONFIG_SOFTMMU) |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 1021 | static void tb_invalidate_phys_page(target_phys_addr_t addr, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1022 | unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1023 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1024 | TranslationBlock *tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1025 | PageDesc *p; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1026 | int n; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1027 | #ifdef TARGET_HAS_PRECISE_SMC |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1028 | TranslationBlock *current_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1029 | CPUState *env = cpu_single_env; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1030 | int current_tb_modified = 0; |
| 1031 | target_ulong current_pc = 0; |
| 1032 | target_ulong current_cs_base = 0; |
| 1033 | int current_flags = 0; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1034 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1035 | |
| 1036 | addr &= TARGET_PAGE_MASK; |
| 1037 | p = page_find(addr >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1038 | if (!p) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1039 | return; |
| 1040 | tb = p->first_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1041 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1042 | if (tb && pc != 0) { |
| 1043 | current_tb = tb_find_pc(pc); |
| 1044 | } |
| 1045 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1046 | while (tb != NULL) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1047 | n = (long)tb & 3; |
| 1048 | tb = (TranslationBlock *)((long)tb & ~3); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1049 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1050 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1051 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1052 | /* If we are modifying the current TB, we must stop |
| 1053 | its execution. We could be more precise by checking |
| 1054 | that the modification is after the current PC, but it |
| 1055 | would require a specialized function to partially |
| 1056 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1057 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1058 | current_tb_modified = 1; |
| 1059 | cpu_restore_state(current_tb, env, pc, puc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1060 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1061 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1062 | } |
| 1063 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1064 | tb_phys_invalidate(tb, addr); |
| 1065 | tb = tb->page_next[n]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1066 | } |
| 1067 | p->first_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1068 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1069 | if (current_tb_modified) { |
| 1070 | /* we generate a block containing just the instruction |
| 1071 | modifying the memory. It will ensure that it cannot modify |
| 1072 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1073 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1074 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1075 | cpu_resume_from_signal(env, puc); |
| 1076 | } |
| 1077 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1078 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1079 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1080 | |
| 1081 | /* add the tb in the target page and protect it if necessary */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1082 | static inline void tb_alloc_page(TranslationBlock *tb, |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1083 | unsigned int n, target_ulong page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1084 | { |
| 1085 | PageDesc *p; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1086 | TranslationBlock *last_first_tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1087 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1088 | tb->page_addr[n] = page_addr; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1089 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1090 | tb->page_next[n] = p->first_tb; |
| 1091 | last_first_tb = p->first_tb; |
| 1092 | p->first_tb = (TranslationBlock *)((long)tb | n); |
| 1093 | invalidate_page_bitmap(p); |
| 1094 | |
bellard | 107db44 | 2004-06-22 18:48:46 +0000 | [diff] [blame] | 1095 | #if defined(TARGET_HAS_SMC) || 1 |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1096 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1097 | #if defined(CONFIG_USER_ONLY) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1098 | if (p->flags & PAGE_WRITE) { |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1099 | target_ulong addr; |
| 1100 | PageDesc *p2; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1101 | int prot; |
| 1102 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1103 | /* force the host page as non writable (writes will have a |
| 1104 | page fault + mprotect overhead) */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1105 | page_addr &= qemu_host_page_mask; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1106 | prot = 0; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1107 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
| 1108 | addr += TARGET_PAGE_SIZE) { |
| 1109 | |
| 1110 | p2 = page_find (addr >> TARGET_PAGE_BITS); |
| 1111 | if (!p2) |
| 1112 | continue; |
| 1113 | prot |= p2->flags; |
| 1114 | p2->flags &= ~PAGE_WRITE; |
| 1115 | page_get_flags(addr); |
| 1116 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1117 | mprotect(g2h(page_addr), qemu_host_page_size, |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1118 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
| 1119 | #ifdef DEBUG_TB_INVALIDATE |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 1120 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1121 | page_addr); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1122 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1123 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1124 | #else |
| 1125 | /* if some code is already present, then the pages are already |
| 1126 | protected. So we handle the case where only the first TB is |
| 1127 | allocated in a physical page */ |
| 1128 | if (!last_first_tb) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1129 | tlb_protect_code(page_addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1130 | } |
| 1131 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1132 | |
| 1133 | #endif /* TARGET_HAS_SMC */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | /* Allocate a new translation block. Flush the translation buffer if |
| 1137 | too many translation blocks or too much generated code. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1138 | TranslationBlock *tb_alloc(target_ulong pc) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1139 | { |
| 1140 | TranslationBlock *tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1141 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 1142 | if (nb_tbs >= code_gen_max_blocks || |
| 1143 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1144 | return NULL; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1145 | tb = &tbs[nb_tbs++]; |
| 1146 | tb->pc = pc; |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 1147 | tb->cflags = 0; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1148 | return tb; |
| 1149 | } |
| 1150 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1151 | void tb_free(TranslationBlock *tb) |
| 1152 | { |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 1153 | /* In practice this is mostly used for single use temporary TB |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1154 | Ignore the hard cases and just back up if this TB happens to |
| 1155 | be the last one generated. */ |
| 1156 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { |
| 1157 | code_gen_ptr = tb->tc_ptr; |
| 1158 | nb_tbs--; |
| 1159 | } |
| 1160 | } |
| 1161 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1162 | /* add a new TB and link it to the physical page tables. phys_page2 is |
| 1163 | (-1) to indicate that only one page contains the TB. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1164 | void tb_link_phys(TranslationBlock *tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1165 | target_ulong phys_pc, target_ulong phys_page2) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1166 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1167 | unsigned int h; |
| 1168 | TranslationBlock **ptb; |
| 1169 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1170 | /* Grab the mmap lock to stop another thread invalidating this TB |
| 1171 | before we are done. */ |
| 1172 | mmap_lock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1173 | /* add in the physical hash table */ |
| 1174 | h = tb_phys_hash_func(phys_pc); |
| 1175 | ptb = &tb_phys_hash[h]; |
| 1176 | tb->phys_hash_next = *ptb; |
| 1177 | *ptb = tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1178 | |
| 1179 | /* add in the page list */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1180 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
| 1181 | if (phys_page2 != -1) |
| 1182 | tb_alloc_page(tb, 1, phys_page2); |
| 1183 | else |
| 1184 | tb->page_addr[1] = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1185 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1186 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
| 1187 | tb->jmp_next[0] = NULL; |
| 1188 | tb->jmp_next[1] = NULL; |
| 1189 | |
| 1190 | /* init original jump addresses */ |
| 1191 | if (tb->tb_next_offset[0] != 0xffff) |
| 1192 | tb_reset_jump(tb, 0); |
| 1193 | if (tb->tb_next_offset[1] != 0xffff) |
| 1194 | tb_reset_jump(tb, 1); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1195 | |
| 1196 | #ifdef DEBUG_TB_CHECK |
| 1197 | tb_page_check(); |
| 1198 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1199 | mmap_unlock(); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1200 | } |
| 1201 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1202 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
| 1203 | tb[1].tc_ptr. Return NULL if not found */ |
| 1204 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) |
| 1205 | { |
| 1206 | int m_min, m_max, m; |
| 1207 | unsigned long v; |
| 1208 | TranslationBlock *tb; |
| 1209 | |
| 1210 | if (nb_tbs <= 0) |
| 1211 | return NULL; |
| 1212 | if (tc_ptr < (unsigned long)code_gen_buffer || |
| 1213 | tc_ptr >= (unsigned long)code_gen_ptr) |
| 1214 | return NULL; |
| 1215 | /* binary search (cf Knuth) */ |
| 1216 | m_min = 0; |
| 1217 | m_max = nb_tbs - 1; |
| 1218 | while (m_min <= m_max) { |
| 1219 | m = (m_min + m_max) >> 1; |
| 1220 | tb = &tbs[m]; |
| 1221 | v = (unsigned long)tb->tc_ptr; |
| 1222 | if (v == tc_ptr) |
| 1223 | return tb; |
| 1224 | else if (tc_ptr < v) { |
| 1225 | m_max = m - 1; |
| 1226 | } else { |
| 1227 | m_min = m + 1; |
| 1228 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1229 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1230 | return &tbs[m_max]; |
| 1231 | } |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1232 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1233 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
| 1234 | |
| 1235 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) |
| 1236 | { |
| 1237 | TranslationBlock *tb1, *tb_next, **ptb; |
| 1238 | unsigned int n1; |
| 1239 | |
| 1240 | tb1 = tb->jmp_next[n]; |
| 1241 | if (tb1 != NULL) { |
| 1242 | /* find head of list */ |
| 1243 | for(;;) { |
| 1244 | n1 = (long)tb1 & 3; |
| 1245 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1246 | if (n1 == 2) |
| 1247 | break; |
| 1248 | tb1 = tb1->jmp_next[n1]; |
| 1249 | } |
| 1250 | /* we are now sure now that tb jumps to tb1 */ |
| 1251 | tb_next = tb1; |
| 1252 | |
| 1253 | /* remove tb from the jmp_first list */ |
| 1254 | ptb = &tb_next->jmp_first; |
| 1255 | for(;;) { |
| 1256 | tb1 = *ptb; |
| 1257 | n1 = (long)tb1 & 3; |
| 1258 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1259 | if (n1 == n && tb1 == tb) |
| 1260 | break; |
| 1261 | ptb = &tb1->jmp_next[n1]; |
| 1262 | } |
| 1263 | *ptb = tb->jmp_next[n]; |
| 1264 | tb->jmp_next[n] = NULL; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1265 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1266 | /* suppress the jump to next tb in generated code */ |
| 1267 | tb_reset_jump(tb, n); |
| 1268 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1269 | /* suppress jumps in the tb on which we could have jumped */ |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1270 | tb_reset_jump_recursive(tb_next); |
| 1271 | } |
| 1272 | } |
| 1273 | |
| 1274 | static void tb_reset_jump_recursive(TranslationBlock *tb) |
| 1275 | { |
| 1276 | tb_reset_jump_recursive2(tb, 0); |
| 1277 | tb_reset_jump_recursive2(tb, 1); |
| 1278 | } |
| 1279 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1280 | #if defined(TARGET_HAS_ICE) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1281 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1282 | { |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 1283 | target_phys_addr_t addr; |
| 1284 | target_ulong pd; |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1285 | ram_addr_t ram_addr; |
| 1286 | PhysPageDesc *p; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1287 | |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1288 | addr = cpu_get_phys_page_debug(env, pc); |
| 1289 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 1290 | if (!p) { |
| 1291 | pd = IO_MEM_UNASSIGNED; |
| 1292 | } else { |
| 1293 | pd = p->phys_offset; |
| 1294 | } |
| 1295 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); |
pbrook | 706cd4b | 2006-04-08 17:36:21 +0000 | [diff] [blame] | 1296 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1297 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1298 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1299 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1300 | /* Add a watchpoint. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1301 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1302 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1303 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1304 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1305 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1306 | |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1307 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
| 1308 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { |
| 1309 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
| 1310 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 1311 | return -EINVAL; |
| 1312 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1313 | wp = qemu_malloc(sizeof(*wp)); |
| 1314 | if (!wp) |
| 1315 | return -ENOBUFS; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1316 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1317 | wp->vaddr = addr; |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1318 | wp->len_mask = len_mask; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1319 | wp->flags = flags; |
| 1320 | |
| 1321 | wp->next = env->watchpoints; |
| 1322 | wp->prev = NULL; |
| 1323 | if (wp->next) |
| 1324 | wp->next->prev = wp; |
| 1325 | env->watchpoints = wp; |
| 1326 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1327 | tlb_flush_page(env, addr); |
| 1328 | /* FIXME: This flush is needed because of the hack to make memory ops |
| 1329 | terminate the TB. It can be removed once the proper IO trap and |
| 1330 | re-execute bits are in. */ |
| 1331 | tb_flush(env); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1332 | |
| 1333 | if (watchpoint) |
| 1334 | *watchpoint = wp; |
| 1335 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1336 | } |
| 1337 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1338 | /* Remove a specific watchpoint. */ |
| 1339 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, |
| 1340 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1341 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1342 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1343 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1344 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1345 | for (wp = env->watchpoints; wp != NULL; wp = wp->next) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1346 | if (addr == wp->vaddr && len_mask == wp->len_mask |
| 1347 | && flags == wp->flags) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1348 | cpu_watchpoint_remove_by_ref(env, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1349 | return 0; |
| 1350 | } |
| 1351 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1352 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1353 | } |
| 1354 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1355 | /* Remove a specific watchpoint by reference. */ |
| 1356 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) |
| 1357 | { |
| 1358 | if (watchpoint->next) |
| 1359 | watchpoint->next->prev = watchpoint->prev; |
| 1360 | if (watchpoint->prev) |
| 1361 | watchpoint->prev->next = watchpoint->next; |
| 1362 | else |
| 1363 | env->watchpoints = watchpoint->next; |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1364 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1365 | tlb_flush_page(env, watchpoint->vaddr); |
| 1366 | |
| 1367 | qemu_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1368 | } |
| 1369 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1370 | /* Remove all matching watchpoints. */ |
| 1371 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1372 | { |
| 1373 | CPUWatchpoint *wp; |
| 1374 | |
| 1375 | for (wp = env->watchpoints; wp != NULL; wp = wp->next) |
| 1376 | if (wp->flags & mask) |
| 1377 | cpu_watchpoint_remove_by_ref(env, wp); |
| 1378 | } |
| 1379 | |
| 1380 | /* Add a breakpoint. */ |
| 1381 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 1382 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1383 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1384 | #if defined(TARGET_HAS_ICE) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1385 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1386 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1387 | bp = qemu_malloc(sizeof(*bp)); |
| 1388 | if (!bp) |
| 1389 | return -ENOBUFS; |
| 1390 | |
| 1391 | bp->pc = pc; |
| 1392 | bp->flags = flags; |
| 1393 | |
| 1394 | bp->next = env->breakpoints; |
| 1395 | bp->prev = NULL; |
| 1396 | if (bp->next) |
| 1397 | bp->next->prev = bp; |
| 1398 | env->breakpoints = bp; |
| 1399 | |
| 1400 | breakpoint_invalidate(env, pc); |
| 1401 | |
| 1402 | if (breakpoint) |
| 1403 | *breakpoint = bp; |
| 1404 | return 0; |
| 1405 | #else |
| 1406 | return -ENOSYS; |
| 1407 | #endif |
| 1408 | } |
| 1409 | |
| 1410 | /* Remove a specific breakpoint. */ |
| 1411 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) |
| 1412 | { |
| 1413 | #if defined(TARGET_HAS_ICE) |
| 1414 | CPUBreakpoint *bp; |
| 1415 | |
| 1416 | for (bp = env->breakpoints; bp != NULL; bp = bp->next) { |
| 1417 | if (bp->pc == pc && bp->flags == flags) { |
| 1418 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1419 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1420 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1421 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1422 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1423 | #else |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1424 | return -ENOSYS; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1425 | #endif |
| 1426 | } |
| 1427 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1428 | /* Remove a specific breakpoint by reference. */ |
| 1429 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1430 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1431 | #if defined(TARGET_HAS_ICE) |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1432 | if (breakpoint->next) |
| 1433 | breakpoint->next->prev = breakpoint->prev; |
| 1434 | if (breakpoint->prev) |
| 1435 | breakpoint->prev->next = breakpoint->next; |
| 1436 | else |
| 1437 | env->breakpoints = breakpoint->next; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1438 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1439 | breakpoint_invalidate(env, breakpoint->pc); |
| 1440 | |
| 1441 | qemu_free(breakpoint); |
| 1442 | #endif |
| 1443 | } |
| 1444 | |
| 1445 | /* Remove all matching breakpoints. */ |
| 1446 | void cpu_breakpoint_remove_all(CPUState *env, int mask) |
| 1447 | { |
| 1448 | #if defined(TARGET_HAS_ICE) |
| 1449 | CPUBreakpoint *bp; |
| 1450 | |
| 1451 | for (bp = env->breakpoints; bp != NULL; bp = bp->next) |
| 1452 | if (bp->flags & mask) |
| 1453 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1454 | #endif |
| 1455 | } |
| 1456 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1457 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 1458 | CPU loop after each instruction */ |
| 1459 | void cpu_single_step(CPUState *env, int enabled) |
| 1460 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1461 | #if defined(TARGET_HAS_ICE) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1462 | if (env->singlestep_enabled != enabled) { |
| 1463 | env->singlestep_enabled = enabled; |
| 1464 | /* must flush all the translated code to avoid inconsistancies */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1465 | /* XXX: only flush what is necessary */ |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1466 | tb_flush(env); |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1467 | } |
| 1468 | #endif |
| 1469 | } |
| 1470 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1471 | /* enable or disable low levels log */ |
| 1472 | void cpu_set_log(int log_flags) |
| 1473 | { |
| 1474 | loglevel = log_flags; |
| 1475 | if (loglevel && !logfile) { |
pbrook | 11fcfab | 2007-07-01 18:21:11 +0000 | [diff] [blame] | 1476 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1477 | if (!logfile) { |
| 1478 | perror(logfilename); |
| 1479 | _exit(1); |
| 1480 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1481 | #if !defined(CONFIG_SOFTMMU) |
| 1482 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
| 1483 | { |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1484 | static char logfile_buf[4096]; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1485 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
| 1486 | } |
| 1487 | #else |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1488 | setvbuf(logfile, NULL, _IOLBF, 0); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1489 | #endif |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1490 | log_append = 1; |
| 1491 | } |
| 1492 | if (!loglevel && logfile) { |
| 1493 | fclose(logfile); |
| 1494 | logfile = NULL; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1495 | } |
| 1496 | } |
| 1497 | |
| 1498 | void cpu_set_log_filename(const char *filename) |
| 1499 | { |
| 1500 | logfilename = strdup(filename); |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1501 | if (logfile) { |
| 1502 | fclose(logfile); |
| 1503 | logfile = NULL; |
| 1504 | } |
| 1505 | cpu_set_log(loglevel); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1506 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1507 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1508 | /* mask must never be zero, except for A20 change call */ |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 1509 | void cpu_interrupt(CPUState *env, int mask) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1510 | { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1511 | #if !defined(USE_NPTL) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1512 | TranslationBlock *tb; |
aurel32 | 15a5115 | 2008-03-28 22:29:15 +0000 | [diff] [blame] | 1513 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1514 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1515 | int old_mask; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1516 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1517 | old_mask = env->interrupt_request; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1518 | /* FIXME: This is probably not threadsafe. A different thread could |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 1519 | be in the middle of a read-modify-write operation. */ |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 1520 | env->interrupt_request |= mask; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1521 | #if defined(USE_NPTL) |
| 1522 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
| 1523 | problem and hope the cpu will stop of its own accord. For userspace |
| 1524 | emulation this often isn't actually as bad as it sounds. Often |
| 1525 | signals are used primarily to interrupt blocking syscalls. */ |
| 1526 | #else |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1527 | if (use_icount) { |
pbrook | 266910c | 2008-07-09 15:31:50 +0000 | [diff] [blame] | 1528 | env->icount_decr.u16.high = 0xffff; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1529 | #ifndef CONFIG_USER_ONLY |
| 1530 | /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means |
| 1531 | an async event happened and we need to process it. */ |
| 1532 | if (!can_do_io(env) |
| 1533 | && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) { |
| 1534 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
| 1535 | } |
| 1536 | #endif |
| 1537 | } else { |
| 1538 | tb = env->current_tb; |
| 1539 | /* if the cpu is currently executing code, we must unlink it and |
| 1540 | all the potentially executing TB */ |
| 1541 | if (tb && !testandset(&interrupt_lock)) { |
| 1542 | env->current_tb = NULL; |
| 1543 | tb_reset_jump_recursive(tb); |
| 1544 | resetlock(&interrupt_lock); |
| 1545 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1546 | } |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1547 | #endif |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1548 | } |
| 1549 | |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 1550 | void cpu_reset_interrupt(CPUState *env, int mask) |
| 1551 | { |
| 1552 | env->interrupt_request &= ~mask; |
| 1553 | } |
| 1554 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1555 | const CPULogItem cpu_log_items[] = { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1556 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1557 | "show generated host assembly code for each compiled TB" }, |
| 1558 | { CPU_LOG_TB_IN_ASM, "in_asm", |
| 1559 | "show target assembly code for each compiled TB" }, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1560 | { CPU_LOG_TB_OP, "op", |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 1561 | "show micro ops for each compiled TB" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1562 | { CPU_LOG_TB_OP_OPT, "op_opt", |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1563 | "show micro ops " |
| 1564 | #ifdef TARGET_I386 |
| 1565 | "before eflags optimization and " |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1566 | #endif |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1567 | "after liveness analysis" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1568 | { CPU_LOG_INT, "int", |
| 1569 | "show interrupts/exceptions in short format" }, |
| 1570 | { CPU_LOG_EXEC, "exec", |
| 1571 | "show trace before each executed TB (lots of logs)" }, |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1572 | { CPU_LOG_TB_CPU, "cpu", |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 1573 | "show CPU state before block translation" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1574 | #ifdef TARGET_I386 |
| 1575 | { CPU_LOG_PCALL, "pcall", |
| 1576 | "show protected mode far calls/returns/exceptions" }, |
| 1577 | #endif |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1578 | #ifdef DEBUG_IOPORT |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 1579 | { CPU_LOG_IOPORT, "ioport", |
| 1580 | "show all i/o ports accesses" }, |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1581 | #endif |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1582 | { 0, NULL, NULL }, |
| 1583 | }; |
| 1584 | |
| 1585 | static int cmp1(const char *s1, int n, const char *s2) |
| 1586 | { |
| 1587 | if (strlen(s2) != n) |
| 1588 | return 0; |
| 1589 | return memcmp(s1, s2, n) == 0; |
| 1590 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1591 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1592 | /* takes a comma separated list of log masks. Return 0 if error. */ |
| 1593 | int cpu_str_to_log_mask(const char *str) |
| 1594 | { |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1595 | const CPULogItem *item; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1596 | int mask; |
| 1597 | const char *p, *p1; |
| 1598 | |
| 1599 | p = str; |
| 1600 | mask = 0; |
| 1601 | for(;;) { |
| 1602 | p1 = strchr(p, ','); |
| 1603 | if (!p1) |
| 1604 | p1 = p + strlen(p); |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1605 | if(cmp1(p,p1-p,"all")) { |
| 1606 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1607 | mask |= item->mask; |
| 1608 | } |
| 1609 | } else { |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1610 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1611 | if (cmp1(p, p1 - p, item->name)) |
| 1612 | goto found; |
| 1613 | } |
| 1614 | return 0; |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1615 | } |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1616 | found: |
| 1617 | mask |= item->mask; |
| 1618 | if (*p1 != ',') |
| 1619 | break; |
| 1620 | p = p1 + 1; |
| 1621 | } |
| 1622 | return mask; |
| 1623 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1624 | |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1625 | void cpu_abort(CPUState *env, const char *fmt, ...) |
| 1626 | { |
| 1627 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1628 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1629 | |
| 1630 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1631 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1632 | fprintf(stderr, "qemu: fatal: "); |
| 1633 | vfprintf(stderr, fmt, ap); |
| 1634 | fprintf(stderr, "\n"); |
| 1635 | #ifdef TARGET_I386 |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 1636 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1637 | #else |
| 1638 | cpu_dump_state(env, stderr, fprintf, 0); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1639 | #endif |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1640 | if (logfile) { |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1641 | fprintf(logfile, "qemu: fatal: "); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1642 | vfprintf(logfile, fmt, ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1643 | fprintf(logfile, "\n"); |
| 1644 | #ifdef TARGET_I386 |
| 1645 | cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1646 | #else |
| 1647 | cpu_dump_state(env, logfile, fprintf, 0); |
| 1648 | #endif |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1649 | fflush(logfile); |
| 1650 | fclose(logfile); |
| 1651 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1652 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1653 | va_end(ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1654 | abort(); |
| 1655 | } |
| 1656 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1657 | CPUState *cpu_copy(CPUState *env) |
| 1658 | { |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 1659 | CPUState *new_env = cpu_init(env->cpu_model_str); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1660 | /* preserve chaining and index */ |
| 1661 | CPUState *next_cpu = new_env->next_cpu; |
| 1662 | int cpu_index = new_env->cpu_index; |
| 1663 | memcpy(new_env, env, sizeof(CPUState)); |
| 1664 | new_env->next_cpu = next_cpu; |
| 1665 | new_env->cpu_index = cpu_index; |
| 1666 | return new_env; |
| 1667 | } |
| 1668 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1669 | #if !defined(CONFIG_USER_ONLY) |
| 1670 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1671 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
| 1672 | { |
| 1673 | unsigned int i; |
| 1674 | |
| 1675 | /* Discard jump cache entries for any tb which might potentially |
| 1676 | overlap the flushed page. */ |
| 1677 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); |
| 1678 | memset (&env->tb_jmp_cache[i], 0, |
| 1679 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
| 1680 | |
| 1681 | i = tb_jmp_cache_hash_page(addr); |
| 1682 | memset (&env->tb_jmp_cache[i], 0, |
| 1683 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
| 1684 | } |
| 1685 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 1686 | /* NOTE: if flush_global is true, also flush global entries (not |
| 1687 | implemented yet) */ |
| 1688 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1689 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1690 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1691 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1692 | #if defined(DEBUG_TLB) |
| 1693 | printf("tlb_flush:\n"); |
| 1694 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1695 | /* must reset current TB so that interrupts cannot modify the |
| 1696 | links while we are modifying them */ |
| 1697 | env->current_tb = NULL; |
| 1698 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1699 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1700 | env->tlb_table[0][i].addr_read = -1; |
| 1701 | env->tlb_table[0][i].addr_write = -1; |
| 1702 | env->tlb_table[0][i].addr_code = -1; |
| 1703 | env->tlb_table[1][i].addr_read = -1; |
| 1704 | env->tlb_table[1][i].addr_write = -1; |
| 1705 | env->tlb_table[1][i].addr_code = -1; |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1706 | #if (NB_MMU_MODES >= 3) |
| 1707 | env->tlb_table[2][i].addr_read = -1; |
| 1708 | env->tlb_table[2][i].addr_write = -1; |
| 1709 | env->tlb_table[2][i].addr_code = -1; |
| 1710 | #if (NB_MMU_MODES == 4) |
| 1711 | env->tlb_table[3][i].addr_read = -1; |
| 1712 | env->tlb_table[3][i].addr_write = -1; |
| 1713 | env->tlb_table[3][i].addr_code = -1; |
| 1714 | #endif |
| 1715 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1716 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1717 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1718 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1719 | |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 1720 | #ifdef USE_KQEMU |
| 1721 | if (env->kqemu_enabled) { |
| 1722 | kqemu_flush(env, flush_global); |
| 1723 | } |
| 1724 | #endif |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 1725 | tlb_flush_count++; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1726 | } |
| 1727 | |
bellard | 274da6b | 2004-05-20 21:56:27 +0000 | [diff] [blame] | 1728 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1729 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1730 | if (addr == (tlb_entry->addr_read & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1731 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1732 | addr == (tlb_entry->addr_write & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1733 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1734 | addr == (tlb_entry->addr_code & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1735 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
| 1736 | tlb_entry->addr_read = -1; |
| 1737 | tlb_entry->addr_write = -1; |
| 1738 | tlb_entry->addr_code = -1; |
| 1739 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1740 | } |
| 1741 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 1742 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1743 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1744 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1745 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1746 | #if defined(DEBUG_TLB) |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 1747 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1748 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1749 | /* must reset current TB so that interrupts cannot modify the |
| 1750 | links while we are modifying them */ |
| 1751 | env->current_tb = NULL; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1752 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1753 | addr &= TARGET_PAGE_MASK; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1754 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1755 | tlb_flush_entry(&env->tlb_table[0][i], addr); |
| 1756 | tlb_flush_entry(&env->tlb_table[1][i], addr); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1757 | #if (NB_MMU_MODES >= 3) |
| 1758 | tlb_flush_entry(&env->tlb_table[2][i], addr); |
| 1759 | #if (NB_MMU_MODES == 4) |
| 1760 | tlb_flush_entry(&env->tlb_table[3][i], addr); |
| 1761 | #endif |
| 1762 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1763 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1764 | tlb_flush_jmp_cache(env, addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1765 | |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 1766 | #ifdef USE_KQEMU |
| 1767 | if (env->kqemu_enabled) { |
| 1768 | kqemu_flush_page(env, addr); |
| 1769 | } |
| 1770 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1771 | } |
| 1772 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1773 | /* update the TLBs so that writes to code in the virtual page 'addr' |
| 1774 | can be detected */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1775 | static void tlb_protect_code(ram_addr_t ram_addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1776 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1777 | cpu_physical_memory_reset_dirty(ram_addr, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1778 | ram_addr + TARGET_PAGE_SIZE, |
| 1779 | CODE_DIRTY_FLAG); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1780 | } |
| 1781 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1782 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1783 | tested for self modifying code */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1784 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1785 | target_ulong vaddr) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1786 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1787 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1788 | } |
| 1789 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1790 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1791 | unsigned long start, unsigned long length) |
| 1792 | { |
| 1793 | unsigned long addr; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1794 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
| 1795 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1796 | if ((addr - start) < length) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1797 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1798 | } |
| 1799 | } |
| 1800 | } |
| 1801 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1802 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 1803 | int dirty_flags) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1804 | { |
| 1805 | CPUState *env; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 1806 | unsigned long length, start1; |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 1807 | int i, mask, len; |
| 1808 | uint8_t *p; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1809 | |
| 1810 | start &= TARGET_PAGE_MASK; |
| 1811 | end = TARGET_PAGE_ALIGN(end); |
| 1812 | |
| 1813 | length = end - start; |
| 1814 | if (length == 0) |
| 1815 | return; |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 1816 | len = length >> TARGET_PAGE_BITS; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1817 | #ifdef USE_KQEMU |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1818 | /* XXX: should not depend on cpu context */ |
| 1819 | env = first_cpu; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1820 | if (env->kqemu_enabled) { |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 1821 | ram_addr_t addr; |
| 1822 | addr = start; |
| 1823 | for(i = 0; i < len; i++) { |
| 1824 | kqemu_set_notdirty(env, addr); |
| 1825 | addr += TARGET_PAGE_SIZE; |
| 1826 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1827 | } |
| 1828 | #endif |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 1829 | mask = ~dirty_flags; |
| 1830 | p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); |
| 1831 | for(i = 0; i < len; i++) |
| 1832 | p[i] &= mask; |
| 1833 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1834 | /* we modify the TLB cache so that the dirty bit will be set again |
| 1835 | when accessing the range */ |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1836 | start1 = start + (unsigned long)phys_ram_base; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1837 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 1838 | for(i = 0; i < CPU_TLB_SIZE; i++) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1839 | tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1840 | for(i = 0; i < CPU_TLB_SIZE; i++) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1841 | tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1842 | #if (NB_MMU_MODES >= 3) |
| 1843 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 1844 | tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length); |
| 1845 | #if (NB_MMU_MODES == 4) |
| 1846 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 1847 | tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length); |
| 1848 | #endif |
| 1849 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1850 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1851 | } |
| 1852 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 1853 | int cpu_physical_memory_set_dirty_tracking(int enable) |
| 1854 | { |
| 1855 | in_migration = enable; |
| 1856 | return 0; |
| 1857 | } |
| 1858 | |
| 1859 | int cpu_physical_memory_get_dirty_tracking(void) |
| 1860 | { |
| 1861 | return in_migration; |
| 1862 | } |
| 1863 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1864 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
| 1865 | { |
| 1866 | ram_addr_t ram_addr; |
| 1867 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1868 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1869 | ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1870 | tlb_entry->addend - (unsigned long)phys_ram_base; |
| 1871 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1872 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1873 | } |
| 1874 | } |
| 1875 | } |
| 1876 | |
| 1877 | /* update the TLB according to the current state of the dirty bits */ |
| 1878 | void cpu_tlb_update_dirty(CPUState *env) |
| 1879 | { |
| 1880 | int i; |
| 1881 | for(i = 0; i < CPU_TLB_SIZE; i++) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1882 | tlb_update_dirty(&env->tlb_table[0][i]); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1883 | for(i = 0; i < CPU_TLB_SIZE; i++) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1884 | tlb_update_dirty(&env->tlb_table[1][i]); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1885 | #if (NB_MMU_MODES >= 3) |
| 1886 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 1887 | tlb_update_dirty(&env->tlb_table[2][i]); |
| 1888 | #if (NB_MMU_MODES == 4) |
| 1889 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 1890 | tlb_update_dirty(&env->tlb_table[3][i]); |
| 1891 | #endif |
| 1892 | #endif |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 1893 | } |
| 1894 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1895 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1896 | { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1897 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
| 1898 | tlb_entry->addr_write = vaddr; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1899 | } |
| 1900 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1901 | /* update the TLB corresponding to virtual page vaddr |
| 1902 | so that it is no longer dirty */ |
| 1903 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1904 | { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1905 | int i; |
| 1906 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1907 | vaddr &= TARGET_PAGE_MASK; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 1908 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1909 | tlb_set_dirty1(&env->tlb_table[0][i], vaddr); |
| 1910 | tlb_set_dirty1(&env->tlb_table[1][i], vaddr); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1911 | #if (NB_MMU_MODES >= 3) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1912 | tlb_set_dirty1(&env->tlb_table[2][i], vaddr); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1913 | #if (NB_MMU_MODES == 4) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1914 | tlb_set_dirty1(&env->tlb_table[3][i], vaddr); |
j_mayer | 6fa4cea | 2007-04-05 06:43:27 +0000 | [diff] [blame] | 1915 | #endif |
| 1916 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1917 | } |
| 1918 | |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1919 | /* add a new TLB entry. At most one entry for a given virtual address |
| 1920 | is permitted. Return 0 if OK or 2 if the page could not be mapped |
| 1921 | (can only happen in non SOFTMMU mode for I/O pages or pages |
| 1922 | conflicting with the host address space). */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1923 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
| 1924 | target_phys_addr_t paddr, int prot, |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1925 | int mmu_idx, int is_softmmu) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1926 | { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 1927 | PhysPageDesc *p; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 1928 | unsigned long pd; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1929 | unsigned int index; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 1930 | target_ulong address; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1931 | target_ulong code_address; |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 1932 | target_phys_addr_t addend; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1933 | int ret; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1934 | CPUTLBEntry *te; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1935 | CPUWatchpoint *wp; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1936 | target_phys_addr_t iotlb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1937 | |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 1938 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1939 | if (!p) { |
| 1940 | pd = IO_MEM_UNASSIGNED; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1941 | } else { |
| 1942 | pd = p->phys_offset; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1943 | } |
| 1944 | #if defined(DEBUG_TLB) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1945 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
| 1946 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1947 | #endif |
| 1948 | |
| 1949 | ret = 0; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1950 | address = vaddr; |
| 1951 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
| 1952 | /* IO memory case (romd handled later) */ |
| 1953 | address |= TLB_MMIO; |
| 1954 | } |
| 1955 | addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK); |
| 1956 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
| 1957 | /* Normal RAM. */ |
| 1958 | iotlb = pd & TARGET_PAGE_MASK; |
| 1959 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 1960 | iotlb |= IO_MEM_NOTDIRTY; |
| 1961 | else |
| 1962 | iotlb |= IO_MEM_ROM; |
| 1963 | } else { |
| 1964 | /* IO handlers are currently passed a phsical address. |
| 1965 | It would be nice to pass an offset from the base address |
| 1966 | of that region. This would avoid having to special case RAM, |
| 1967 | and avoid full address decoding in every device. |
| 1968 | We can't use the high bits of pd for this because |
| 1969 | IO_MEM_ROMD uses these as a ram address. */ |
| 1970 | iotlb = (pd & ~TARGET_PAGE_MASK) + paddr; |
| 1971 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1972 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1973 | code_address = address; |
| 1974 | /* Make accesses to pages with watchpoints go via the |
| 1975 | watchpoint trap routines. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1976 | for (wp = env->watchpoints; wp != NULL; wp = wp->next) { |
| 1977 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1978 | iotlb = io_mem_watch + paddr; |
| 1979 | /* TODO: The memory case can be optimized by not trapping |
| 1980 | reads of pages with a write breakpoint. */ |
| 1981 | address |= TLB_MMIO; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1982 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1983 | } |
balrog | d79acba | 2007-06-26 20:01:13 +0000 | [diff] [blame] | 1984 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1985 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 1986 | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
| 1987 | te = &env->tlb_table[mmu_idx][index]; |
| 1988 | te->addend = addend - vaddr; |
| 1989 | if (prot & PAGE_READ) { |
| 1990 | te->addr_read = address; |
| 1991 | } else { |
| 1992 | te->addr_read = -1; |
| 1993 | } |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1994 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 1995 | if (prot & PAGE_EXEC) { |
| 1996 | te->addr_code = code_address; |
| 1997 | } else { |
| 1998 | te->addr_code = -1; |
| 1999 | } |
| 2000 | if (prot & PAGE_WRITE) { |
| 2001 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
| 2002 | (pd & IO_MEM_ROMD)) { |
| 2003 | /* Write access calls the I/O callback. */ |
| 2004 | te->addr_write = address | TLB_MMIO; |
| 2005 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
| 2006 | !cpu_physical_memory_is_dirty(pd)) { |
| 2007 | te->addr_write = address | TLB_NOTDIRTY; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2008 | } else { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2009 | te->addr_write = address; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2010 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2011 | } else { |
| 2012 | te->addr_write = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2013 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2014 | return ret; |
| 2015 | } |
| 2016 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2017 | #else |
| 2018 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 2019 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2020 | { |
| 2021 | } |
| 2022 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2023 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2024 | { |
| 2025 | } |
| 2026 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2027 | int tlb_set_page_exec(CPUState *env, target_ulong vaddr, |
| 2028 | target_phys_addr_t paddr, int prot, |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 2029 | int mmu_idx, int is_softmmu) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2030 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2031 | return 0; |
| 2032 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2033 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2034 | /* dump memory mappings */ |
| 2035 | void page_dump(FILE *f) |
| 2036 | { |
| 2037 | unsigned long start, end; |
| 2038 | int i, j, prot, prot1; |
| 2039 | PageDesc *p; |
| 2040 | |
| 2041 | fprintf(f, "%-8s %-8s %-8s %s\n", |
| 2042 | "start", "end", "size", "prot"); |
| 2043 | start = -1; |
| 2044 | end = -1; |
| 2045 | prot = 0; |
| 2046 | for(i = 0; i <= L1_SIZE; i++) { |
| 2047 | if (i < L1_SIZE) |
| 2048 | p = l1_map[i]; |
| 2049 | else |
| 2050 | p = NULL; |
| 2051 | for(j = 0;j < L2_SIZE; j++) { |
| 2052 | if (!p) |
| 2053 | prot1 = 0; |
| 2054 | else |
| 2055 | prot1 = p[j].flags; |
| 2056 | if (prot1 != prot) { |
| 2057 | end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS); |
| 2058 | if (start != -1) { |
| 2059 | fprintf(f, "%08lx-%08lx %08lx %c%c%c\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2060 | start, end, end - start, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2061 | prot & PAGE_READ ? 'r' : '-', |
| 2062 | prot & PAGE_WRITE ? 'w' : '-', |
| 2063 | prot & PAGE_EXEC ? 'x' : '-'); |
| 2064 | } |
| 2065 | if (prot1 != 0) |
| 2066 | start = end; |
| 2067 | else |
| 2068 | start = -1; |
| 2069 | prot = prot1; |
| 2070 | } |
| 2071 | if (!p) |
| 2072 | break; |
| 2073 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2074 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2075 | } |
| 2076 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2077 | int page_get_flags(target_ulong address) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2078 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2079 | PageDesc *p; |
| 2080 | |
| 2081 | p = page_find(address >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2082 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2083 | return 0; |
| 2084 | return p->flags; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2085 | } |
| 2086 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2087 | /* modify the flags of a page and invalidate the code if |
| 2088 | necessary. The flag PAGE_WRITE_ORG is positionned automatically |
| 2089 | depending on PAGE_WRITE */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2090 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2091 | { |
| 2092 | PageDesc *p; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2093 | target_ulong addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2094 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2095 | /* mmap_lock should already be held. */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2096 | start = start & TARGET_PAGE_MASK; |
| 2097 | end = TARGET_PAGE_ALIGN(end); |
| 2098 | if (flags & PAGE_WRITE) |
| 2099 | flags |= PAGE_WRITE_ORG; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2100 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
| 2101 | p = page_find_alloc(addr >> TARGET_PAGE_BITS); |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 2102 | /* We may be called for host regions that are outside guest |
| 2103 | address space. */ |
| 2104 | if (!p) |
| 2105 | return; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2106 | /* if the write protection is set, then we invalidate the code |
| 2107 | inside */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2108 | if (!(p->flags & PAGE_WRITE) && |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2109 | (flags & PAGE_WRITE) && |
| 2110 | p->first_tb) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2111 | tb_invalidate_phys_page(addr, 0, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2112 | } |
| 2113 | p->flags = flags; |
| 2114 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2115 | } |
| 2116 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2117 | int page_check_range(target_ulong start, target_ulong len, int flags) |
| 2118 | { |
| 2119 | PageDesc *p; |
| 2120 | target_ulong end; |
| 2121 | target_ulong addr; |
| 2122 | |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2123 | if (start + len < start) |
| 2124 | /* we've wrapped around */ |
| 2125 | return -1; |
| 2126 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2127 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
| 2128 | start = start & TARGET_PAGE_MASK; |
| 2129 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2130 | for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) { |
| 2131 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2132 | if( !p ) |
| 2133 | return -1; |
| 2134 | if( !(p->flags & PAGE_VALID) ) |
| 2135 | return -1; |
| 2136 | |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2137 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2138 | return -1; |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2139 | if (flags & PAGE_WRITE) { |
| 2140 | if (!(p->flags & PAGE_WRITE_ORG)) |
| 2141 | return -1; |
| 2142 | /* unprotect the page if it was put read-only because it |
| 2143 | contains translated code */ |
| 2144 | if (!(p->flags & PAGE_WRITE)) { |
| 2145 | if (!page_unprotect(addr, 0, NULL)) |
| 2146 | return -1; |
| 2147 | } |
| 2148 | return 0; |
| 2149 | } |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2150 | } |
| 2151 | return 0; |
| 2152 | } |
| 2153 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2154 | /* called from signal handler: invalidate the code and unprotect the |
| 2155 | page. Return TRUE if the fault was succesfully handled. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2156 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2157 | { |
| 2158 | unsigned int page_index, prot, pindex; |
| 2159 | PageDesc *p, *p1; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2160 | target_ulong host_start, host_end, addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2161 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2162 | /* Technically this isn't safe inside a signal handler. However we |
| 2163 | know this only ever happens in a synchronous SEGV handler, so in |
| 2164 | practice it seems to be ok. */ |
| 2165 | mmap_lock(); |
| 2166 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 2167 | host_start = address & qemu_host_page_mask; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2168 | page_index = host_start >> TARGET_PAGE_BITS; |
| 2169 | p1 = page_find(page_index); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2170 | if (!p1) { |
| 2171 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2172 | return 0; |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2173 | } |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 2174 | host_end = host_start + qemu_host_page_size; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2175 | p = p1; |
| 2176 | prot = 0; |
| 2177 | for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) { |
| 2178 | prot |= p->flags; |
| 2179 | p++; |
| 2180 | } |
| 2181 | /* if the page was really writable, then we change its |
| 2182 | protection back to writable */ |
| 2183 | if (prot & PAGE_WRITE_ORG) { |
| 2184 | pindex = (address - host_start) >> TARGET_PAGE_BITS; |
| 2185 | if (!(p1[pindex].flags & PAGE_WRITE)) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2186 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2187 | (prot & PAGE_BITS) | PAGE_WRITE); |
| 2188 | p1[pindex].flags |= PAGE_WRITE; |
| 2189 | /* and since the content will be modified, we must invalidate |
| 2190 | the corresponding translated code. */ |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2191 | tb_invalidate_phys_page(address, pc, puc); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2192 | #ifdef DEBUG_TB_CHECK |
| 2193 | tb_invalidate_check(address); |
| 2194 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2195 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2196 | return 1; |
| 2197 | } |
| 2198 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2199 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2200 | return 0; |
| 2201 | } |
| 2202 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2203 | static inline void tlb_set_dirty(CPUState *env, |
| 2204 | unsigned long addr, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2205 | { |
| 2206 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2207 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 2208 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2209 | #if !defined(CONFIG_USER_ONLY) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2210 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2211 | ram_addr_t memory); |
| 2212 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2213 | ram_addr_t orig_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2214 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2215 | need_subpage) \ |
| 2216 | do { \ |
| 2217 | if (addr > start_addr) \ |
| 2218 | start_addr2 = 0; \ |
| 2219 | else { \ |
| 2220 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ |
| 2221 | if (start_addr2 > 0) \ |
| 2222 | need_subpage = 1; \ |
| 2223 | } \ |
| 2224 | \ |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2225 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2226 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
| 2227 | else { \ |
| 2228 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ |
| 2229 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ |
| 2230 | need_subpage = 1; \ |
| 2231 | } \ |
| 2232 | } while (0) |
| 2233 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2234 | /* register physical memory. 'size' must be a multiple of the target |
| 2235 | page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
| 2236 | io memory page */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2237 | void cpu_register_physical_memory(target_phys_addr_t start_addr, |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2238 | ram_addr_t size, |
| 2239 | ram_addr_t phys_offset) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2240 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 2241 | target_phys_addr_t addr, end_addr; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2242 | PhysPageDesc *p; |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2243 | CPUState *env; |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2244 | ram_addr_t orig_size = size; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2245 | void *subpage; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2246 | |
bellard | da26024 | 2008-05-30 20:48:25 +0000 | [diff] [blame] | 2247 | #ifdef USE_KQEMU |
| 2248 | /* XXX: should not depend on cpu context */ |
| 2249 | env = first_cpu; |
| 2250 | if (env->kqemu_enabled) { |
| 2251 | kqemu_set_phys_mem(start_addr, size, phys_offset); |
| 2252 | } |
| 2253 | #endif |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 2254 | if (kvm_enabled()) |
| 2255 | kvm_set_phys_mem(start_addr, size, phys_offset); |
| 2256 | |
bellard | 5fd386f | 2004-05-23 21:11:22 +0000 | [diff] [blame] | 2257 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2258 | end_addr = start_addr + (target_phys_addr_t)size; |
| 2259 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2260 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2261 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2262 | ram_addr_t orig_memory = p->phys_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2263 | target_phys_addr_t start_addr2, end_addr2; |
| 2264 | int need_subpage = 0; |
| 2265 | |
| 2266 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, |
| 2267 | need_subpage); |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2268 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2269 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
| 2270 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
| 2271 | &p->phys_offset, orig_memory); |
| 2272 | } else { |
| 2273 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) |
| 2274 | >> IO_MEM_SHIFT]; |
| 2275 | } |
| 2276 | subpage_register(subpage, start_addr2, end_addr2, phys_offset); |
| 2277 | } else { |
| 2278 | p->phys_offset = phys_offset; |
| 2279 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2280 | (phys_offset & IO_MEM_ROMD)) |
| 2281 | phys_offset += TARGET_PAGE_SIZE; |
| 2282 | } |
| 2283 | } else { |
| 2284 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2285 | p->phys_offset = phys_offset; |
| 2286 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2287 | (phys_offset & IO_MEM_ROMD)) |
| 2288 | phys_offset += TARGET_PAGE_SIZE; |
| 2289 | else { |
| 2290 | target_phys_addr_t start_addr2, end_addr2; |
| 2291 | int need_subpage = 0; |
| 2292 | |
| 2293 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, |
| 2294 | end_addr2, need_subpage); |
| 2295 | |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2296 | if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2297 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
| 2298 | &p->phys_offset, IO_MEM_UNASSIGNED); |
| 2299 | subpage_register(subpage, start_addr2, end_addr2, |
| 2300 | phys_offset); |
| 2301 | } |
| 2302 | } |
| 2303 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2304 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2305 | |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2306 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2307 | reset the modified entries */ |
| 2308 | /* XXX: slow ! */ |
| 2309 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 2310 | tlb_flush(env, 1); |
| 2311 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2312 | } |
| 2313 | |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2314 | /* XXX: temporary until new memory mapping API */ |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2315 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2316 | { |
| 2317 | PhysPageDesc *p; |
| 2318 | |
| 2319 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2320 | if (!p) |
| 2321 | return IO_MEM_UNASSIGNED; |
| 2322 | return p->phys_offset; |
| 2323 | } |
| 2324 | |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2325 | /* XXX: better than nothing */ |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2326 | ram_addr_t qemu_ram_alloc(ram_addr_t size) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2327 | { |
| 2328 | ram_addr_t addr; |
balrog | 7fb4fdc | 2008-04-24 17:59:27 +0000 | [diff] [blame] | 2329 | if ((phys_ram_alloc_offset + size) > phys_ram_size) { |
ths | 012a704 | 2008-10-02 17:34:21 +0000 | [diff] [blame] | 2330 | fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n", |
bellard | ed44146 | 2008-05-23 11:56:45 +0000 | [diff] [blame] | 2331 | (uint64_t)size, (uint64_t)phys_ram_size); |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2332 | abort(); |
| 2333 | } |
| 2334 | addr = phys_ram_alloc_offset; |
| 2335 | phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size); |
| 2336 | return addr; |
| 2337 | } |
| 2338 | |
| 2339 | void qemu_ram_free(ram_addr_t addr) |
| 2340 | { |
| 2341 | } |
| 2342 | |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2343 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2344 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2345 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 2346 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2347 | #endif |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2348 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2349 | do_unassigned_access(addr, 0, 0, 0, 1); |
| 2350 | #endif |
| 2351 | return 0; |
| 2352 | } |
| 2353 | |
| 2354 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
| 2355 | { |
| 2356 | #ifdef DEBUG_UNASSIGNED |
| 2357 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 2358 | #endif |
| 2359 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2360 | do_unassigned_access(addr, 0, 0, 0, 2); |
| 2361 | #endif |
| 2362 | return 0; |
| 2363 | } |
| 2364 | |
| 2365 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
| 2366 | { |
| 2367 | #ifdef DEBUG_UNASSIGNED |
| 2368 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 2369 | #endif |
| 2370 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2371 | do_unassigned_access(addr, 0, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 2372 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2373 | return 0; |
| 2374 | } |
| 2375 | |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2376 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2377 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2378 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 2379 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2380 | #endif |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2381 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2382 | do_unassigned_access(addr, 1, 0, 0, 1); |
| 2383 | #endif |
| 2384 | } |
| 2385 | |
| 2386 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 2387 | { |
| 2388 | #ifdef DEBUG_UNASSIGNED |
| 2389 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 2390 | #endif |
| 2391 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2392 | do_unassigned_access(addr, 1, 0, 0, 2); |
| 2393 | #endif |
| 2394 | } |
| 2395 | |
| 2396 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 2397 | { |
| 2398 | #ifdef DEBUG_UNASSIGNED |
| 2399 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 2400 | #endif |
| 2401 | #if defined(TARGET_SPARC) || defined(TARGET_CRIS) |
| 2402 | do_unassigned_access(addr, 1, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 2403 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2404 | } |
| 2405 | |
| 2406 | static CPUReadMemoryFunc *unassigned_mem_read[3] = { |
| 2407 | unassigned_mem_readb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2408 | unassigned_mem_readw, |
| 2409 | unassigned_mem_readl, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2410 | }; |
| 2411 | |
| 2412 | static CPUWriteMemoryFunc *unassigned_mem_write[3] = { |
| 2413 | unassigned_mem_writeb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2414 | unassigned_mem_writew, |
| 2415 | unassigned_mem_writel, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2416 | }; |
| 2417 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2418 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
| 2419 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2420 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2421 | int dirty_flags; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2422 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2423 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 2424 | #if !defined(CONFIG_USER_ONLY) |
| 2425 | tb_invalidate_phys_page_fast(ram_addr, 1); |
| 2426 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2427 | #endif |
| 2428 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2429 | stb_p(phys_ram_base + ram_addr, val); |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 2430 | #ifdef USE_KQEMU |
| 2431 | if (cpu_single_env->kqemu_enabled && |
| 2432 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) |
| 2433 | kqemu_modify_page(cpu_single_env, ram_addr); |
| 2434 | #endif |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2435 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
| 2436 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; |
| 2437 | /* we remove the notdirty callback only if the code has been |
| 2438 | flushed */ |
| 2439 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 2440 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2441 | } |
| 2442 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2443 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
| 2444 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2445 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2446 | int dirty_flags; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2447 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2448 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 2449 | #if !defined(CONFIG_USER_ONLY) |
| 2450 | tb_invalidate_phys_page_fast(ram_addr, 2); |
| 2451 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2452 | #endif |
| 2453 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2454 | stw_p(phys_ram_base + ram_addr, val); |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 2455 | #ifdef USE_KQEMU |
| 2456 | if (cpu_single_env->kqemu_enabled && |
| 2457 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) |
| 2458 | kqemu_modify_page(cpu_single_env, ram_addr); |
| 2459 | #endif |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2460 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
| 2461 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; |
| 2462 | /* we remove the notdirty callback only if the code has been |
| 2463 | flushed */ |
| 2464 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 2465 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2466 | } |
| 2467 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2468 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
| 2469 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2470 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2471 | int dirty_flags; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2472 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2473 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 2474 | #if !defined(CONFIG_USER_ONLY) |
| 2475 | tb_invalidate_phys_page_fast(ram_addr, 4); |
| 2476 | dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS]; |
| 2477 | #endif |
| 2478 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2479 | stl_p(phys_ram_base + ram_addr, val); |
bellard | f32fc64 | 2006-02-08 22:43:39 +0000 | [diff] [blame] | 2480 | #ifdef USE_KQEMU |
| 2481 | if (cpu_single_env->kqemu_enabled && |
| 2482 | (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK) |
| 2483 | kqemu_modify_page(cpu_single_env, ram_addr); |
| 2484 | #endif |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2485 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
| 2486 | phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags; |
| 2487 | /* we remove the notdirty callback only if the code has been |
| 2488 | flushed */ |
| 2489 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 2490 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2491 | } |
| 2492 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2493 | static CPUReadMemoryFunc *error_mem_read[3] = { |
| 2494 | NULL, /* never used */ |
| 2495 | NULL, /* never used */ |
| 2496 | NULL, /* never used */ |
| 2497 | }; |
| 2498 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2499 | static CPUWriteMemoryFunc *notdirty_mem_write[3] = { |
| 2500 | notdirty_mem_writeb, |
| 2501 | notdirty_mem_writew, |
| 2502 | notdirty_mem_writel, |
| 2503 | }; |
| 2504 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2505 | /* Generate a debug exception if a watchpoint has been hit. */ |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2506 | static void check_watchpoint(int offset, int len_mask, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2507 | { |
| 2508 | CPUState *env = cpu_single_env; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame^] | 2509 | target_ulong pc, cs_base; |
| 2510 | TranslationBlock *tb; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2511 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2512 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame^] | 2513 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2514 | |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame^] | 2515 | if (env->watchpoint_hit) { |
| 2516 | /* We re-entered the check after replacing the TB. Now raise |
| 2517 | * the debug interrupt so that is will trigger after the |
| 2518 | * current instruction. */ |
| 2519 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); |
| 2520 | return; |
| 2521 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 2522 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2523 | for (wp = env->watchpoints; wp != NULL; wp = wp->next) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2524 | if ((vaddr == (wp->vaddr & len_mask) || |
| 2525 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2526 | env->watchpoint_hit = wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame^] | 2527 | tb = tb_find_pc(env->mem_io_pc); |
| 2528 | if (!tb) { |
| 2529 | cpu_abort(env, "check_watchpoint: could not find TB for pc=%p", |
| 2530 | (void *)env->mem_io_pc); |
| 2531 | } |
| 2532 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); |
| 2533 | tb_phys_invalidate(tb, -1); |
| 2534 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
| 2535 | env->exception_index = EXCP_DEBUG; |
| 2536 | } else { |
| 2537 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 2538 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); |
| 2539 | } |
| 2540 | cpu_resume_from_signal(env, NULL); |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2541 | } |
| 2542 | } |
| 2543 | } |
| 2544 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2545 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 2546 | so these check for a hit then pass through to the normal out-of-line |
| 2547 | phys routines. */ |
| 2548 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
| 2549 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2550 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2551 | return ldub_phys(addr); |
| 2552 | } |
| 2553 | |
| 2554 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
| 2555 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2556 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2557 | return lduw_phys(addr); |
| 2558 | } |
| 2559 | |
| 2560 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
| 2561 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2562 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2563 | return ldl_phys(addr); |
| 2564 | } |
| 2565 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2566 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
| 2567 | uint32_t val) |
| 2568 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2569 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2570 | stb_phys(addr, val); |
| 2571 | } |
| 2572 | |
| 2573 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
| 2574 | uint32_t val) |
| 2575 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2576 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2577 | stw_phys(addr, val); |
| 2578 | } |
| 2579 | |
| 2580 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
| 2581 | uint32_t val) |
| 2582 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 2583 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2584 | stl_phys(addr, val); |
| 2585 | } |
| 2586 | |
| 2587 | static CPUReadMemoryFunc *watch_mem_read[3] = { |
| 2588 | watch_mem_readb, |
| 2589 | watch_mem_readw, |
| 2590 | watch_mem_readl, |
| 2591 | }; |
| 2592 | |
| 2593 | static CPUWriteMemoryFunc *watch_mem_write[3] = { |
| 2594 | watch_mem_writeb, |
| 2595 | watch_mem_writew, |
| 2596 | watch_mem_writel, |
| 2597 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2598 | |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2599 | static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr, |
| 2600 | unsigned int len) |
| 2601 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2602 | uint32_t ret; |
| 2603 | unsigned int idx; |
| 2604 | |
| 2605 | idx = SUBPAGE_IDX(addr - mmio->base); |
| 2606 | #if defined(DEBUG_SUBPAGE) |
| 2607 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, |
| 2608 | mmio, len, addr, idx); |
| 2609 | #endif |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 2610 | ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2611 | |
| 2612 | return ret; |
| 2613 | } |
| 2614 | |
| 2615 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
| 2616 | uint32_t value, unsigned int len) |
| 2617 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2618 | unsigned int idx; |
| 2619 | |
| 2620 | idx = SUBPAGE_IDX(addr - mmio->base); |
| 2621 | #if defined(DEBUG_SUBPAGE) |
| 2622 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__, |
| 2623 | mmio, len, addr, idx, value); |
| 2624 | #endif |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 2625 | (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2626 | } |
| 2627 | |
| 2628 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
| 2629 | { |
| 2630 | #if defined(DEBUG_SUBPAGE) |
| 2631 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
| 2632 | #endif |
| 2633 | |
| 2634 | return subpage_readlen(opaque, addr, 0); |
| 2635 | } |
| 2636 | |
| 2637 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
| 2638 | uint32_t value) |
| 2639 | { |
| 2640 | #if defined(DEBUG_SUBPAGE) |
| 2641 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); |
| 2642 | #endif |
| 2643 | subpage_writelen(opaque, addr, value, 0); |
| 2644 | } |
| 2645 | |
| 2646 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
| 2647 | { |
| 2648 | #if defined(DEBUG_SUBPAGE) |
| 2649 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
| 2650 | #endif |
| 2651 | |
| 2652 | return subpage_readlen(opaque, addr, 1); |
| 2653 | } |
| 2654 | |
| 2655 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
| 2656 | uint32_t value) |
| 2657 | { |
| 2658 | #if defined(DEBUG_SUBPAGE) |
| 2659 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); |
| 2660 | #endif |
| 2661 | subpage_writelen(opaque, addr, value, 1); |
| 2662 | } |
| 2663 | |
| 2664 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
| 2665 | { |
| 2666 | #if defined(DEBUG_SUBPAGE) |
| 2667 | printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
| 2668 | #endif |
| 2669 | |
| 2670 | return subpage_readlen(opaque, addr, 2); |
| 2671 | } |
| 2672 | |
| 2673 | static void subpage_writel (void *opaque, |
| 2674 | target_phys_addr_t addr, uint32_t value) |
| 2675 | { |
| 2676 | #if defined(DEBUG_SUBPAGE) |
| 2677 | printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value); |
| 2678 | #endif |
| 2679 | subpage_writelen(opaque, addr, value, 2); |
| 2680 | } |
| 2681 | |
| 2682 | static CPUReadMemoryFunc *subpage_read[] = { |
| 2683 | &subpage_readb, |
| 2684 | &subpage_readw, |
| 2685 | &subpage_readl, |
| 2686 | }; |
| 2687 | |
| 2688 | static CPUWriteMemoryFunc *subpage_write[] = { |
| 2689 | &subpage_writeb, |
| 2690 | &subpage_writew, |
| 2691 | &subpage_writel, |
| 2692 | }; |
| 2693 | |
| 2694 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2695 | ram_addr_t memory) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2696 | { |
| 2697 | int idx, eidx; |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2698 | unsigned int i; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2699 | |
| 2700 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 2701 | return -1; |
| 2702 | idx = SUBPAGE_IDX(start); |
| 2703 | eidx = SUBPAGE_IDX(end); |
| 2704 | #if defined(DEBUG_SUBPAGE) |
| 2705 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__, |
| 2706 | mmio, start, end, idx, eidx, memory); |
| 2707 | #endif |
| 2708 | memory >>= IO_MEM_SHIFT; |
| 2709 | for (; idx <= eidx; idx++) { |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2710 | for (i = 0; i < 4; i++) { |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 2711 | if (io_mem_read[memory][i]) { |
| 2712 | mmio->mem_read[idx][i] = &io_mem_read[memory][i]; |
| 2713 | mmio->opaque[idx][0][i] = io_mem_opaque[memory]; |
| 2714 | } |
| 2715 | if (io_mem_write[memory][i]) { |
| 2716 | mmio->mem_write[idx][i] = &io_mem_write[memory][i]; |
| 2717 | mmio->opaque[idx][1][i] = io_mem_opaque[memory]; |
| 2718 | } |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2719 | } |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2720 | } |
| 2721 | |
| 2722 | return 0; |
| 2723 | } |
| 2724 | |
aurel32 | 00f82b8 | 2008-04-27 21:12:55 +0000 | [diff] [blame] | 2725 | static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2726 | ram_addr_t orig_memory) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2727 | { |
| 2728 | subpage_t *mmio; |
| 2729 | int subpage_memory; |
| 2730 | |
| 2731 | mmio = qemu_mallocz(sizeof(subpage_t)); |
| 2732 | if (mmio != NULL) { |
| 2733 | mmio->base = base; |
| 2734 | subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio); |
| 2735 | #if defined(DEBUG_SUBPAGE) |
| 2736 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
| 2737 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
| 2738 | #endif |
| 2739 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
| 2740 | subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory); |
| 2741 | } |
| 2742 | |
| 2743 | return mmio; |
| 2744 | } |
| 2745 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2746 | static void io_mem_init(void) |
| 2747 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2748 | cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL); |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2749 | cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2750 | cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2751 | io_mem_nb = 5; |
| 2752 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2753 | io_mem_watch = cpu_register_io_memory(0, watch_mem_read, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2754 | watch_mem_write, NULL); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2755 | /* alloc dirty bits array */ |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 2756 | phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2757 | memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2758 | } |
| 2759 | |
| 2760 | /* mem_read and mem_write are arrays of functions containing the |
| 2761 | function to access byte (index 0), word (index 1) and dword (index |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 2762 | 2). Functions can be omitted with a NULL function pointer. The |
| 2763 | registered functions may be modified dynamically later. |
| 2764 | If io_index is non zero, the corresponding io zone is |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2765 | modified. If it is zero, a new io zone is allocated. The return |
| 2766 | value can be used with cpu_register_physical_memory(). (-1) is |
| 2767 | returned if error. */ |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2768 | int cpu_register_io_memory(int io_index, |
| 2769 | CPUReadMemoryFunc **mem_read, |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2770 | CPUWriteMemoryFunc **mem_write, |
| 2771 | void *opaque) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2772 | { |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2773 | int i, subwidth = 0; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2774 | |
| 2775 | if (io_index <= 0) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2776 | if (io_mem_nb >= IO_MEM_NB_ENTRIES) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2777 | return -1; |
| 2778 | io_index = io_mem_nb++; |
| 2779 | } else { |
| 2780 | if (io_index >= IO_MEM_NB_ENTRIES) |
| 2781 | return -1; |
| 2782 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2783 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2784 | for(i = 0;i < 3; i++) { |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2785 | if (!mem_read[i] || !mem_write[i]) |
| 2786 | subwidth = IO_MEM_SUBWIDTH; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2787 | io_mem_read[io_index][i] = mem_read[i]; |
| 2788 | io_mem_write[io_index][i] = mem_write[i]; |
| 2789 | } |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2790 | io_mem_opaque[io_index] = opaque; |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 2791 | return (io_index << IO_MEM_SHIFT) | subwidth; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2792 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2793 | |
bellard | 8926b51 | 2004-10-10 15:14:20 +0000 | [diff] [blame] | 2794 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index) |
| 2795 | { |
| 2796 | return io_mem_write[io_index >> IO_MEM_SHIFT]; |
| 2797 | } |
| 2798 | |
| 2799 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index) |
| 2800 | { |
| 2801 | return io_mem_read[io_index >> IO_MEM_SHIFT]; |
| 2802 | } |
| 2803 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2804 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 2805 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2806 | /* physical memory access (slow version, mainly for debug) */ |
| 2807 | #if defined(CONFIG_USER_ONLY) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2808 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2809 | int len, int is_write) |
| 2810 | { |
| 2811 | int l, flags; |
| 2812 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2813 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2814 | |
| 2815 | while (len > 0) { |
| 2816 | page = addr & TARGET_PAGE_MASK; |
| 2817 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 2818 | if (l > len) |
| 2819 | l = len; |
| 2820 | flags = page_get_flags(page); |
| 2821 | if (!(flags & PAGE_VALID)) |
| 2822 | return; |
| 2823 | if (is_write) { |
| 2824 | if (!(flags & PAGE_WRITE)) |
| 2825 | return; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2826 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2827 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2828 | /* FIXME - should this return an error rather than just fail? */ |
| 2829 | return; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2830 | memcpy(p, buf, l); |
| 2831 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2832 | } else { |
| 2833 | if (!(flags & PAGE_READ)) |
| 2834 | return; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2835 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2836 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 2837 | /* FIXME - should this return an error rather than just fail? */ |
| 2838 | return; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 2839 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 2840 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2841 | } |
| 2842 | len -= l; |
| 2843 | buf += l; |
| 2844 | addr += l; |
| 2845 | } |
| 2846 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2847 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2848 | #else |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2849 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2850 | int len, int is_write) |
| 2851 | { |
| 2852 | int l, io_index; |
| 2853 | uint8_t *ptr; |
| 2854 | uint32_t val; |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2855 | target_phys_addr_t page; |
| 2856 | unsigned long pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2857 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2858 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2859 | while (len > 0) { |
| 2860 | page = addr & TARGET_PAGE_MASK; |
| 2861 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 2862 | if (l > len) |
| 2863 | l = len; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2864 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2865 | if (!p) { |
| 2866 | pd = IO_MEM_UNASSIGNED; |
| 2867 | } else { |
| 2868 | pd = p->phys_offset; |
| 2869 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2870 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2871 | if (is_write) { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2872 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2873 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2874 | /* XXX: could force cpu_single_env to NULL to avoid |
| 2875 | potential bugs */ |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2876 | if (l >= 4 && ((addr & 3) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2877 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2878 | val = ldl_p(buf); |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2879 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2880 | l = 4; |
| 2881 | } else if (l >= 2 && ((addr & 1) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2882 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2883 | val = lduw_p(buf); |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2884 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2885 | l = 2; |
| 2886 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2887 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2888 | val = ldub_p(buf); |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2889 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2890 | l = 1; |
| 2891 | } |
| 2892 | } else { |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 2893 | unsigned long addr1; |
| 2894 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2895 | /* RAM case */ |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 2896 | ptr = phys_ram_base + addr1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2897 | memcpy(ptr, buf, l); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2898 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 2899 | /* invalidate code */ |
| 2900 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 2901 | /* set dirty bit */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2902 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2903 | (0xff & ~CODE_DIRTY_FLAG); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2904 | } |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2905 | } |
| 2906 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2907 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 2908 | !(pd & IO_MEM_ROMD)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2909 | /* I/O case */ |
| 2910 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 2911 | if (l >= 4 && ((addr & 3) == 0)) { |
| 2912 | /* 32 bit read access */ |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2913 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2914 | stl_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2915 | l = 4; |
| 2916 | } else if (l >= 2 && ((addr & 1) == 0)) { |
| 2917 | /* 16 bit read access */ |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2918 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2919 | stw_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2920 | l = 2; |
| 2921 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 2922 | /* 8 bit read access */ |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 2923 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 2924 | stb_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2925 | l = 1; |
| 2926 | } |
| 2927 | } else { |
| 2928 | /* RAM case */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2929 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 2930 | (addr & ~TARGET_PAGE_MASK); |
| 2931 | memcpy(buf, ptr, l); |
| 2932 | } |
| 2933 | } |
| 2934 | len -= l; |
| 2935 | buf += l; |
| 2936 | addr += l; |
| 2937 | } |
| 2938 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2939 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2940 | /* used for ROM loading : can write in RAM and ROM */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2941 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2942 | const uint8_t *buf, int len) |
| 2943 | { |
| 2944 | int l; |
| 2945 | uint8_t *ptr; |
| 2946 | target_phys_addr_t page; |
| 2947 | unsigned long pd; |
| 2948 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2949 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2950 | while (len > 0) { |
| 2951 | page = addr & TARGET_PAGE_MASK; |
| 2952 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 2953 | if (l > len) |
| 2954 | l = len; |
| 2955 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 2956 | if (!p) { |
| 2957 | pd = IO_MEM_UNASSIGNED; |
| 2958 | } else { |
| 2959 | pd = p->phys_offset; |
| 2960 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2961 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2962 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 2963 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
| 2964 | !(pd & IO_MEM_ROMD)) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 2965 | /* do nothing */ |
| 2966 | } else { |
| 2967 | unsigned long addr1; |
| 2968 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 2969 | /* ROM/RAM case */ |
| 2970 | ptr = phys_ram_base + addr1; |
| 2971 | memcpy(ptr, buf, l); |
| 2972 | } |
| 2973 | len -= l; |
| 2974 | buf += l; |
| 2975 | addr += l; |
| 2976 | } |
| 2977 | } |
| 2978 | |
| 2979 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2980 | /* warning: addr must be aligned */ |
| 2981 | uint32_t ldl_phys(target_phys_addr_t addr) |
| 2982 | { |
| 2983 | int io_index; |
| 2984 | uint8_t *ptr; |
| 2985 | uint32_t val; |
| 2986 | unsigned long pd; |
| 2987 | PhysPageDesc *p; |
| 2988 | |
| 2989 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2990 | if (!p) { |
| 2991 | pd = IO_MEM_UNASSIGNED; |
| 2992 | } else { |
| 2993 | pd = p->phys_offset; |
| 2994 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2995 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2996 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 2997 | !(pd & IO_MEM_ROMD)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 2998 | /* I/O case */ |
| 2999 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3000 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 3001 | } else { |
| 3002 | /* RAM case */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3003 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3004 | (addr & ~TARGET_PAGE_MASK); |
| 3005 | val = ldl_p(ptr); |
| 3006 | } |
| 3007 | return val; |
| 3008 | } |
| 3009 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3010 | /* warning: addr must be aligned */ |
| 3011 | uint64_t ldq_phys(target_phys_addr_t addr) |
| 3012 | { |
| 3013 | int io_index; |
| 3014 | uint8_t *ptr; |
| 3015 | uint64_t val; |
| 3016 | unsigned long pd; |
| 3017 | PhysPageDesc *p; |
| 3018 | |
| 3019 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3020 | if (!p) { |
| 3021 | pd = IO_MEM_UNASSIGNED; |
| 3022 | } else { |
| 3023 | pd = p->phys_offset; |
| 3024 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3025 | |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3026 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 3027 | !(pd & IO_MEM_ROMD)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3028 | /* I/O case */ |
| 3029 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3030 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3031 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; |
| 3032 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); |
| 3033 | #else |
| 3034 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 3035 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; |
| 3036 | #endif |
| 3037 | } else { |
| 3038 | /* RAM case */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3039 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3040 | (addr & ~TARGET_PAGE_MASK); |
| 3041 | val = ldq_p(ptr); |
| 3042 | } |
| 3043 | return val; |
| 3044 | } |
| 3045 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3046 | /* XXX: optimize */ |
| 3047 | uint32_t ldub_phys(target_phys_addr_t addr) |
| 3048 | { |
| 3049 | uint8_t val; |
| 3050 | cpu_physical_memory_read(addr, &val, 1); |
| 3051 | return val; |
| 3052 | } |
| 3053 | |
| 3054 | /* XXX: optimize */ |
| 3055 | uint32_t lduw_phys(target_phys_addr_t addr) |
| 3056 | { |
| 3057 | uint16_t val; |
| 3058 | cpu_physical_memory_read(addr, (uint8_t *)&val, 2); |
| 3059 | return tswap16(val); |
| 3060 | } |
| 3061 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3062 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 3063 | and the code inside is not invalidated. It is useful if the dirty |
| 3064 | bits are used to track modified PTEs */ |
| 3065 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
| 3066 | { |
| 3067 | int io_index; |
| 3068 | uint8_t *ptr; |
| 3069 | unsigned long pd; |
| 3070 | PhysPageDesc *p; |
| 3071 | |
| 3072 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3073 | if (!p) { |
| 3074 | pd = IO_MEM_UNASSIGNED; |
| 3075 | } else { |
| 3076 | pd = p->phys_offset; |
| 3077 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3078 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3079 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3080 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3081 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3082 | } else { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 3083 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3084 | ptr = phys_ram_base + addr1; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3085 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 3086 | |
| 3087 | if (unlikely(in_migration)) { |
| 3088 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3089 | /* invalidate code */ |
| 3090 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 3091 | /* set dirty bit */ |
| 3092 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
| 3093 | (0xff & ~CODE_DIRTY_FLAG); |
| 3094 | } |
| 3095 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3096 | } |
| 3097 | } |
| 3098 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3099 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
| 3100 | { |
| 3101 | int io_index; |
| 3102 | uint8_t *ptr; |
| 3103 | unsigned long pd; |
| 3104 | PhysPageDesc *p; |
| 3105 | |
| 3106 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3107 | if (!p) { |
| 3108 | pd = IO_MEM_UNASSIGNED; |
| 3109 | } else { |
| 3110 | pd = p->phys_offset; |
| 3111 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3112 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3113 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 3114 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3115 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3116 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); |
| 3117 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); |
| 3118 | #else |
| 3119 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3120 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); |
| 3121 | #endif |
| 3122 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3123 | ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3124 | (addr & ~TARGET_PAGE_MASK); |
| 3125 | stq_p(ptr, val); |
| 3126 | } |
| 3127 | } |
| 3128 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3129 | /* warning: addr must be aligned */ |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3130 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
| 3131 | { |
| 3132 | int io_index; |
| 3133 | uint8_t *ptr; |
| 3134 | unsigned long pd; |
| 3135 | PhysPageDesc *p; |
| 3136 | |
| 3137 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3138 | if (!p) { |
| 3139 | pd = IO_MEM_UNASSIGNED; |
| 3140 | } else { |
| 3141 | pd = p->phys_offset; |
| 3142 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3143 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3144 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3145 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3146 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3147 | } else { |
| 3148 | unsigned long addr1; |
| 3149 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3150 | /* RAM case */ |
| 3151 | ptr = phys_ram_base + addr1; |
| 3152 | stl_p(ptr, val); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3153 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3154 | /* invalidate code */ |
| 3155 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 3156 | /* set dirty bit */ |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3157 | phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |= |
| 3158 | (0xff & ~CODE_DIRTY_FLAG); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3159 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3160 | } |
| 3161 | } |
| 3162 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3163 | /* XXX: optimize */ |
| 3164 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
| 3165 | { |
| 3166 | uint8_t v = val; |
| 3167 | cpu_physical_memory_write(addr, &v, 1); |
| 3168 | } |
| 3169 | |
| 3170 | /* XXX: optimize */ |
| 3171 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
| 3172 | { |
| 3173 | uint16_t v = tswap16(val); |
| 3174 | cpu_physical_memory_write(addr, (const uint8_t *)&v, 2); |
| 3175 | } |
| 3176 | |
| 3177 | /* XXX: optimize */ |
| 3178 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
| 3179 | { |
| 3180 | val = tswap64(val); |
| 3181 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); |
| 3182 | } |
| 3183 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3184 | #endif |
| 3185 | |
| 3186 | /* virtual memory access for debug */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3187 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3188 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3189 | { |
| 3190 | int l; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 3191 | target_phys_addr_t phys_addr; |
| 3192 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3193 | |
| 3194 | while (len > 0) { |
| 3195 | page = addr & TARGET_PAGE_MASK; |
| 3196 | phys_addr = cpu_get_phys_page_debug(env, page); |
| 3197 | /* if no physical page mapped, return an error */ |
| 3198 | if (phys_addr == -1) |
| 3199 | return -1; |
| 3200 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3201 | if (l > len) |
| 3202 | l = len; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3203 | cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK), |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3204 | buf, l, is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3205 | len -= l; |
| 3206 | buf += l; |
| 3207 | addr += l; |
| 3208 | } |
| 3209 | return 0; |
| 3210 | } |
| 3211 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3212 | /* in deterministic execution mode, instructions doing device I/Os |
| 3213 | must be at the end of the TB */ |
| 3214 | void cpu_io_recompile(CPUState *env, void *retaddr) |
| 3215 | { |
| 3216 | TranslationBlock *tb; |
| 3217 | uint32_t n, cflags; |
| 3218 | target_ulong pc, cs_base; |
| 3219 | uint64_t flags; |
| 3220 | |
| 3221 | tb = tb_find_pc((unsigned long)retaddr); |
| 3222 | if (!tb) { |
| 3223 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", |
| 3224 | retaddr); |
| 3225 | } |
| 3226 | n = env->icount_decr.u16.low + tb->icount; |
| 3227 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); |
| 3228 | /* Calculate how many instructions had been executed before the fault |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 3229 | occurred. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3230 | n = n - env->icount_decr.u16.low; |
| 3231 | /* Generate a new TB ending on the I/O insn. */ |
| 3232 | n++; |
| 3233 | /* On MIPS and SH, delay slot instructions can only be restarted if |
| 3234 | they were already the first instruction in the TB. If this is not |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 3235 | the first instruction in a TB then re-execute the preceding |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3236 | branch. */ |
| 3237 | #if defined(TARGET_MIPS) |
| 3238 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { |
| 3239 | env->active_tc.PC -= 4; |
| 3240 | env->icount_decr.u16.low++; |
| 3241 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 3242 | } |
| 3243 | #elif defined(TARGET_SH4) |
| 3244 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
| 3245 | && n > 1) { |
| 3246 | env->pc -= 2; |
| 3247 | env->icount_decr.u16.low++; |
| 3248 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 3249 | } |
| 3250 | #endif |
| 3251 | /* This should never happen. */ |
| 3252 | if (n > CF_COUNT_MASK) |
| 3253 | cpu_abort(env, "TB too big during recompile"); |
| 3254 | |
| 3255 | cflags = n | CF_LAST_IO; |
| 3256 | pc = tb->pc; |
| 3257 | cs_base = tb->cs_base; |
| 3258 | flags = tb->flags; |
| 3259 | tb_phys_invalidate(tb, -1); |
| 3260 | /* FIXME: In theory this could raise an exception. In practice |
| 3261 | we have already translated the block once so it's probably ok. */ |
| 3262 | tb_gen_code(env, pc, cs_base, flags, cflags); |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 3263 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3264 | the first in the TB) then we end up generating a whole new TB and |
| 3265 | repeating the fault, which is horribly inefficient. |
| 3266 | Better would be to execute just this insn uncached, or generate a |
| 3267 | second new TB. */ |
| 3268 | cpu_resume_from_signal(env, NULL); |
| 3269 | } |
| 3270 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3271 | void dump_exec_info(FILE *f, |
| 3272 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| 3273 | { |
| 3274 | int i, target_code_size, max_target_code_size; |
| 3275 | int direct_jmp_count, direct_jmp2_count, cross_page; |
| 3276 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3277 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3278 | target_code_size = 0; |
| 3279 | max_target_code_size = 0; |
| 3280 | cross_page = 0; |
| 3281 | direct_jmp_count = 0; |
| 3282 | direct_jmp2_count = 0; |
| 3283 | for(i = 0; i < nb_tbs; i++) { |
| 3284 | tb = &tbs[i]; |
| 3285 | target_code_size += tb->size; |
| 3286 | if (tb->size > max_target_code_size) |
| 3287 | max_target_code_size = tb->size; |
| 3288 | if (tb->page_addr[1] != -1) |
| 3289 | cross_page++; |
| 3290 | if (tb->tb_next_offset[0] != 0xffff) { |
| 3291 | direct_jmp_count++; |
| 3292 | if (tb->tb_next_offset[1] != 0xffff) { |
| 3293 | direct_jmp2_count++; |
| 3294 | } |
| 3295 | } |
| 3296 | } |
| 3297 | /* XXX: avoid using doubles ? */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3298 | cpu_fprintf(f, "Translation buffer state:\n"); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 3299 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
| 3300 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
| 3301 | cpu_fprintf(f, "TB count %d/%d\n", |
| 3302 | nb_tbs, code_gen_max_blocks); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3303 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3304 | nb_tbs ? target_code_size / nb_tbs : 0, |
| 3305 | max_target_code_size); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3306 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3307 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
| 3308 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3309 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
| 3310 | cross_page, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3311 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
| 3312 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3313 | direct_jmp_count, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3314 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
| 3315 | direct_jmp2_count, |
| 3316 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3317 | cpu_fprintf(f, "\nStatistics:\n"); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3318 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
| 3319 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); |
| 3320 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 3321 | tcg_dump_info(f, cpu_fprintf); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 3322 | } |
| 3323 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3324 | #if !defined(CONFIG_USER_ONLY) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3325 | |
| 3326 | #define MMUSUFFIX _cmmu |
| 3327 | #define GETPC() NULL |
| 3328 | #define env cpu_single_env |
bellard | b769d8f | 2004-10-03 15:07:13 +0000 | [diff] [blame] | 3329 | #define SOFTMMU_CODE_ACCESS |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3330 | |
| 3331 | #define SHIFT 0 |
| 3332 | #include "softmmu_template.h" |
| 3333 | |
| 3334 | #define SHIFT 1 |
| 3335 | #include "softmmu_template.h" |
| 3336 | |
| 3337 | #define SHIFT 2 |
| 3338 | #include "softmmu_template.h" |
| 3339 | |
| 3340 | #define SHIFT 3 |
| 3341 | #include "softmmu_template.h" |
| 3342 | |
| 3343 | #undef env |
| 3344 | |
| 3345 | #endif |