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bellard54936002003-05-13 00:25:15 +00001/*
bellardfd6ce8f2003-05-14 19:00:11 +00002 * virtual page mapping and translated block handling
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard54936002003-05-13 00:25:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
bellard67b915a2004-03-31 23:37:16 +000020#include "config.h"
bellardd5a8f072004-09-29 21:15:28 +000021#ifdef _WIN32
ths4fddf622007-12-17 04:42:29 +000022#define WIN32_LEAN_AND_MEAN
bellardd5a8f072004-09-29 21:15:28 +000023#include <windows.h>
24#else
bellarda98d49b2004-11-14 16:22:05 +000025#include <sys/types.h>
bellardd5a8f072004-09-29 21:15:28 +000026#include <sys/mman.h>
27#endif
bellard54936002003-05-13 00:25:15 +000028#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <errno.h>
33#include <unistd.h>
34#include <inttypes.h>
35
bellard6180a182003-09-30 21:04:53 +000036#include "cpu.h"
37#include "exec-all.h"
aurel32ca10f862008-04-11 21:35:42 +000038#include "qemu-common.h"
bellardb67d9a52008-05-23 09:57:34 +000039#include "tcg.h"
pbrookb3c77242008-06-30 16:31:04 +000040#include "hw/hw.h"
aliguori74576192008-10-06 14:02:03 +000041#include "osdep.h"
aliguori7ba1e612008-11-05 16:04:33 +000042#include "kvm.h"
pbrook53a59602006-03-25 19:31:22 +000043#if defined(CONFIG_USER_ONLY)
44#include <qemu.h>
45#endif
bellard54936002003-05-13 00:25:15 +000046
bellardfd6ce8f2003-05-14 19:00:11 +000047//#define DEBUG_TB_INVALIDATE
bellard66e85a22003-06-24 13:28:12 +000048//#define DEBUG_FLUSH
bellard9fa3e852004-01-04 18:06:42 +000049//#define DEBUG_TLB
pbrook67d3b952006-12-18 05:03:52 +000050//#define DEBUG_UNASSIGNED
bellardfd6ce8f2003-05-14 19:00:11 +000051
52/* make various TB consistency checks */
ths5fafdf22007-09-16 21:08:06 +000053//#define DEBUG_TB_CHECK
54//#define DEBUG_TLB_CHECK
bellardfd6ce8f2003-05-14 19:00:11 +000055
ths1196be32007-03-17 15:17:58 +000056//#define DEBUG_IOPORT
blueswir1db7b5422007-05-26 17:36:03 +000057//#define DEBUG_SUBPAGE
ths1196be32007-03-17 15:17:58 +000058
pbrook99773bd2006-04-16 15:14:59 +000059#if !defined(CONFIG_USER_ONLY)
60/* TB consistency checks only implemented for usermode emulation. */
61#undef DEBUG_TB_CHECK
62#endif
63
bellard9fa3e852004-01-04 18:06:42 +000064#define SMC_BITMAP_USE_THRESHOLD 10
65
66#define MMAP_AREA_START 0x00000000
67#define MMAP_AREA_END 0xa8000000
bellardfd6ce8f2003-05-14 19:00:11 +000068
bellard108c49b2005-07-24 12:55:09 +000069#if defined(TARGET_SPARC64)
70#define TARGET_PHYS_ADDR_SPACE_BITS 41
blueswir15dcb6b92007-05-19 12:58:30 +000071#elif defined(TARGET_SPARC)
72#define TARGET_PHYS_ADDR_SPACE_BITS 36
j_mayerbedb69e2007-04-05 20:08:21 +000073#elif defined(TARGET_ALPHA)
74#define TARGET_PHYS_ADDR_SPACE_BITS 42
75#define TARGET_VIRT_ADDR_SPACE_BITS 42
bellard108c49b2005-07-24 12:55:09 +000076#elif defined(TARGET_PPC64)
77#define TARGET_PHYS_ADDR_SPACE_BITS 42
aurel3200f82b82008-04-27 21:12:55 +000078#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
79#define TARGET_PHYS_ADDR_SPACE_BITS 42
80#elif defined(TARGET_I386) && !defined(USE_KQEMU)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
bellard108c49b2005-07-24 12:55:09 +000082#else
83/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
84#define TARGET_PHYS_ADDR_SPACE_BITS 32
85#endif
86
blueswir1bdaf78e2008-10-04 07:24:27 +000087static TranslationBlock *tbs;
bellard26a5f132008-05-28 12:30:31 +000088int code_gen_max_blocks;
bellard9fa3e852004-01-04 18:06:42 +000089TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +000090static int nb_tbs;
bellardeb51d102003-05-14 21:51:13 +000091/* any access to the tbs or the page table must use this lock */
92spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
bellardfd6ce8f2003-05-14 19:00:11 +000093
blueswir1141ac462008-07-26 15:05:57 +000094#if defined(__arm__) || defined(__sparc_v9__)
95/* The prologue must be reachable with a direct jump. ARM and Sparc64
96 have limited branch ranges (possibly also PPC) so place it in a
blueswir1d03d8602008-07-10 17:21:31 +000097 section close to code segment. */
98#define code_gen_section \
99 __attribute__((__section__(".gen_code"))) \
100 __attribute__((aligned (32)))
101#else
102#define code_gen_section \
103 __attribute__((aligned (32)))
104#endif
105
106uint8_t code_gen_prologue[1024] code_gen_section;
blueswir1bdaf78e2008-10-04 07:24:27 +0000107static uint8_t *code_gen_buffer;
108static unsigned long code_gen_buffer_size;
bellard26a5f132008-05-28 12:30:31 +0000109/* threshold to flush the translated code buffer */
blueswir1bdaf78e2008-10-04 07:24:27 +0000110static unsigned long code_gen_buffer_max_size;
bellardfd6ce8f2003-05-14 19:00:11 +0000111uint8_t *code_gen_ptr;
112
pbrooke2eef172008-06-08 01:09:01 +0000113#if !defined(CONFIG_USER_ONLY)
aurel3200f82b82008-04-27 21:12:55 +0000114ram_addr_t phys_ram_size;
bellard9fa3e852004-01-04 18:06:42 +0000115int phys_ram_fd;
116uint8_t *phys_ram_base;
bellard1ccde1c2004-02-06 19:46:14 +0000117uint8_t *phys_ram_dirty;
aliguori74576192008-10-06 14:02:03 +0000118static int in_migration;
bellarde9a1ab12007-02-08 23:08:38 +0000119static ram_addr_t phys_ram_alloc_offset = 0;
pbrooke2eef172008-06-08 01:09:01 +0000120#endif
bellard9fa3e852004-01-04 18:06:42 +0000121
bellard6a00d602005-11-21 23:25:50 +0000122CPUState *first_cpu;
123/* current CPU in the current thread. It is only valid inside
124 cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000125CPUState *cpu_single_env;
pbrook2e70f6e2008-06-29 01:03:05 +0000126/* 0 = Do not count executed instructions.
thsbf20dc02008-06-30 17:22:19 +0000127 1 = Precise instruction counting.
pbrook2e70f6e2008-06-29 01:03:05 +0000128 2 = Adaptive rate instruction counting. */
129int use_icount = 0;
130/* Current instruction counter. While executing translated code this may
131 include some instructions that have not yet been executed. */
132int64_t qemu_icount;
bellard6a00d602005-11-21 23:25:50 +0000133
bellard54936002003-05-13 00:25:15 +0000134typedef struct PageDesc {
bellard92e873b2004-05-21 14:52:29 +0000135 /* list of TBs intersecting this ram page */
bellardfd6ce8f2003-05-14 19:00:11 +0000136 TranslationBlock *first_tb;
bellard9fa3e852004-01-04 18:06:42 +0000137 /* in order to optimize self modifying code, we count the number
138 of lookups we do to a given page to use a bitmap */
139 unsigned int code_write_count;
140 uint8_t *code_bitmap;
141#if defined(CONFIG_USER_ONLY)
142 unsigned long flags;
143#endif
bellard54936002003-05-13 00:25:15 +0000144} PageDesc;
145
bellard92e873b2004-05-21 14:52:29 +0000146typedef struct PhysPageDesc {
pbrook0f459d12008-06-09 00:20:13 +0000147 /* offset in host memory of the page + io_index in the low bits */
aurel3200f82b82008-04-27 21:12:55 +0000148 ram_addr_t phys_offset;
bellard92e873b2004-05-21 14:52:29 +0000149} PhysPageDesc;
150
bellard54936002003-05-13 00:25:15 +0000151#define L2_BITS 10
j_mayerbedb69e2007-04-05 20:08:21 +0000152#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
153/* XXX: this is a temporary hack for alpha target.
154 * In the future, this is to be replaced by a multi-level table
155 * to actually be able to handle the complete 64 bits address space.
156 */
157#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
158#else
aurel3203875442008-04-22 20:45:18 +0000159#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
j_mayerbedb69e2007-04-05 20:08:21 +0000160#endif
bellard54936002003-05-13 00:25:15 +0000161
162#define L1_SIZE (1 << L1_BITS)
163#define L2_SIZE (1 << L2_BITS)
164
bellard83fb7ad2004-07-05 21:25:26 +0000165unsigned long qemu_real_host_page_size;
166unsigned long qemu_host_page_bits;
167unsigned long qemu_host_page_size;
168unsigned long qemu_host_page_mask;
bellard54936002003-05-13 00:25:15 +0000169
bellard92e873b2004-05-21 14:52:29 +0000170/* XXX: for system emulation, it could just be an array */
bellard54936002003-05-13 00:25:15 +0000171static PageDesc *l1_map[L1_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +0000172static PhysPageDesc **l1_phys_map;
bellard54936002003-05-13 00:25:15 +0000173
pbrooke2eef172008-06-08 01:09:01 +0000174#if !defined(CONFIG_USER_ONLY)
175static void io_mem_init(void);
176
bellard33417e72003-08-10 21:47:01 +0000177/* io memory support */
bellard33417e72003-08-10 21:47:01 +0000178CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
179CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000180void *io_mem_opaque[IO_MEM_NB_ENTRIES];
bellard33417e72003-08-10 21:47:01 +0000181static int io_mem_nb;
pbrook6658ffb2007-03-16 23:58:11 +0000182static int io_mem_watch;
183#endif
bellard33417e72003-08-10 21:47:01 +0000184
bellard34865132003-10-05 14:28:56 +0000185/* log support */
blueswir1d9b630f2008-10-05 09:57:08 +0000186static const char *logfilename = "/tmp/qemu.log";
bellard34865132003-10-05 14:28:56 +0000187FILE *logfile;
188int loglevel;
pbrooke735b912007-06-30 13:53:24 +0000189static int log_append = 0;
bellard34865132003-10-05 14:28:56 +0000190
bellarde3db7222005-01-26 22:00:47 +0000191/* statistics */
192static int tlb_flush_count;
193static int tb_flush_count;
194static int tb_phys_invalidate_count;
195
blueswir1db7b5422007-05-26 17:36:03 +0000196#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
197typedef struct subpage_t {
198 target_phys_addr_t base;
blueswir13ee89922008-01-02 19:45:26 +0000199 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
200 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
201 void *opaque[TARGET_PAGE_SIZE][2][4];
blueswir1db7b5422007-05-26 17:36:03 +0000202} subpage_t;
203
bellard7cb69ca2008-05-10 10:55:51 +0000204#ifdef _WIN32
205static void map_exec(void *addr, long size)
206{
207 DWORD old_protect;
208 VirtualProtect(addr, size,
209 PAGE_EXECUTE_READWRITE, &old_protect);
210
211}
212#else
213static void map_exec(void *addr, long size)
214{
bellard43694152008-05-29 09:35:57 +0000215 unsigned long start, end, page_size;
bellard7cb69ca2008-05-10 10:55:51 +0000216
bellard43694152008-05-29 09:35:57 +0000217 page_size = getpagesize();
bellard7cb69ca2008-05-10 10:55:51 +0000218 start = (unsigned long)addr;
bellard43694152008-05-29 09:35:57 +0000219 start &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000220
221 end = (unsigned long)addr + size;
bellard43694152008-05-29 09:35:57 +0000222 end += page_size - 1;
223 end &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000224
225 mprotect((void *)start, end - start,
226 PROT_READ | PROT_WRITE | PROT_EXEC);
227}
228#endif
229
bellardb346ff42003-06-15 20:05:50 +0000230static void page_init(void)
bellard54936002003-05-13 00:25:15 +0000231{
bellard83fb7ad2004-07-05 21:25:26 +0000232 /* NOTE: we can always suppose that qemu_host_page_size >=
bellard54936002003-05-13 00:25:15 +0000233 TARGET_PAGE_SIZE */
aliguoric2b48b62008-11-11 22:06:42 +0000234#ifdef _WIN32
235 {
236 SYSTEM_INFO system_info;
237
238 GetSystemInfo(&system_info);
239 qemu_real_host_page_size = system_info.dwPageSize;
240 }
241#else
242 qemu_real_host_page_size = getpagesize();
243#endif
bellard83fb7ad2004-07-05 21:25:26 +0000244 if (qemu_host_page_size == 0)
245 qemu_host_page_size = qemu_real_host_page_size;
246 if (qemu_host_page_size < TARGET_PAGE_SIZE)
247 qemu_host_page_size = TARGET_PAGE_SIZE;
248 qemu_host_page_bits = 0;
249 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
250 qemu_host_page_bits++;
251 qemu_host_page_mask = ~(qemu_host_page_size - 1);
bellard108c49b2005-07-24 12:55:09 +0000252 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
253 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
balrog50a95692007-12-12 01:16:23 +0000254
255#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
256 {
257 long long startaddr, endaddr;
258 FILE *f;
259 int n;
260
pbrookc8a706f2008-06-02 16:16:42 +0000261 mmap_lock();
pbrook07765902008-05-31 16:33:53 +0000262 last_brk = (unsigned long)sbrk(0);
balrog50a95692007-12-12 01:16:23 +0000263 f = fopen("/proc/self/maps", "r");
264 if (f) {
265 do {
266 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
267 if (n == 2) {
blueswir1e0b8d652008-05-03 17:51:24 +0000268 startaddr = MIN(startaddr,
269 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
270 endaddr = MIN(endaddr,
271 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
pbrookb5fc9092008-05-29 13:56:10 +0000272 page_set_flags(startaddr & TARGET_PAGE_MASK,
balrog50a95692007-12-12 01:16:23 +0000273 TARGET_PAGE_ALIGN(endaddr),
274 PAGE_RESERVED);
275 }
276 } while (!feof(f));
277 fclose(f);
278 }
pbrookc8a706f2008-06-02 16:16:42 +0000279 mmap_unlock();
balrog50a95692007-12-12 01:16:23 +0000280 }
281#endif
bellard54936002003-05-13 00:25:15 +0000282}
283
aliguori434929b2008-09-15 15:56:30 +0000284static inline PageDesc **page_l1_map(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000285{
pbrook17e23772008-06-09 13:47:45 +0000286#if TARGET_LONG_BITS > 32
287 /* Host memory outside guest VM. For 32-bit targets we have already
288 excluded high addresses. */
thsd8173e02008-08-29 13:10:00 +0000289 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
pbrook17e23772008-06-09 13:47:45 +0000290 return NULL;
291#endif
aliguori434929b2008-09-15 15:56:30 +0000292 return &l1_map[index >> L2_BITS];
293}
294
295static inline PageDesc *page_find_alloc(target_ulong index)
296{
297 PageDesc **lp, *p;
298 lp = page_l1_map(index);
299 if (!lp)
300 return NULL;
301
bellard54936002003-05-13 00:25:15 +0000302 p = *lp;
303 if (!p) {
304 /* allocate if not found */
pbrook17e23772008-06-09 13:47:45 +0000305#if defined(CONFIG_USER_ONLY)
306 unsigned long addr;
307 size_t len = sizeof(PageDesc) * L2_SIZE;
308 /* Don't use qemu_malloc because it may recurse. */
309 p = mmap(0, len, PROT_READ | PROT_WRITE,
310 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
bellard54936002003-05-13 00:25:15 +0000311 *lp = p;
pbrook17e23772008-06-09 13:47:45 +0000312 addr = h2g(p);
313 if (addr == (target_ulong)addr) {
314 page_set_flags(addr & TARGET_PAGE_MASK,
315 TARGET_PAGE_ALIGN(addr + len),
316 PAGE_RESERVED);
317 }
318#else
319 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
320 *lp = p;
321#endif
bellard54936002003-05-13 00:25:15 +0000322 }
323 return p + (index & (L2_SIZE - 1));
324}
325
aurel3200f82b82008-04-27 21:12:55 +0000326static inline PageDesc *page_find(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000327{
aliguori434929b2008-09-15 15:56:30 +0000328 PageDesc **lp, *p;
329 lp = page_l1_map(index);
330 if (!lp)
331 return NULL;
bellard54936002003-05-13 00:25:15 +0000332
aliguori434929b2008-09-15 15:56:30 +0000333 p = *lp;
bellard54936002003-05-13 00:25:15 +0000334 if (!p)
335 return 0;
bellardfd6ce8f2003-05-14 19:00:11 +0000336 return p + (index & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000337}
338
bellard108c49b2005-07-24 12:55:09 +0000339static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
bellard92e873b2004-05-21 14:52:29 +0000340{
bellard108c49b2005-07-24 12:55:09 +0000341 void **lp, **p;
pbrooke3f4e2a2006-04-08 20:02:06 +0000342 PhysPageDesc *pd;
bellard92e873b2004-05-21 14:52:29 +0000343
bellard108c49b2005-07-24 12:55:09 +0000344 p = (void **)l1_phys_map;
345#if TARGET_PHYS_ADDR_SPACE_BITS > 32
346
347#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
348#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
349#endif
350 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000351 p = *lp;
352 if (!p) {
353 /* allocate if not found */
bellard108c49b2005-07-24 12:55:09 +0000354 if (!alloc)
355 return NULL;
356 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
357 memset(p, 0, sizeof(void *) * L1_SIZE);
358 *lp = p;
359 }
360#endif
361 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pbrooke3f4e2a2006-04-08 20:02:06 +0000362 pd = *lp;
363 if (!pd) {
364 int i;
bellard108c49b2005-07-24 12:55:09 +0000365 /* allocate if not found */
366 if (!alloc)
367 return NULL;
pbrooke3f4e2a2006-04-08 20:02:06 +0000368 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
369 *lp = pd;
370 for (i = 0; i < L2_SIZE; i++)
371 pd[i].phys_offset = IO_MEM_UNASSIGNED;
bellard92e873b2004-05-21 14:52:29 +0000372 }
pbrooke3f4e2a2006-04-08 20:02:06 +0000373 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000374}
375
bellard108c49b2005-07-24 12:55:09 +0000376static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
bellard92e873b2004-05-21 14:52:29 +0000377{
bellard108c49b2005-07-24 12:55:09 +0000378 return phys_page_find_alloc(index, 0);
bellard92e873b2004-05-21 14:52:29 +0000379}
380
bellard9fa3e852004-01-04 18:06:42 +0000381#if !defined(CONFIG_USER_ONLY)
bellard6a00d602005-11-21 23:25:50 +0000382static void tlb_protect_code(ram_addr_t ram_addr);
ths5fafdf22007-09-16 21:08:06 +0000383static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +0000384 target_ulong vaddr);
pbrookc8a706f2008-06-02 16:16:42 +0000385#define mmap_lock() do { } while(0)
386#define mmap_unlock() do { } while(0)
bellard9fa3e852004-01-04 18:06:42 +0000387#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000388
bellard43694152008-05-29 09:35:57 +0000389#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
390
391#if defined(CONFIG_USER_ONLY)
392/* Currently it is not recommanded to allocate big chunks of data in
393 user mode. It will change when a dedicated libc will be used */
394#define USE_STATIC_CODE_GEN_BUFFER
395#endif
396
397#ifdef USE_STATIC_CODE_GEN_BUFFER
398static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
399#endif
400
blueswir18fcd3692008-08-17 20:26:25 +0000401static void code_gen_alloc(unsigned long tb_size)
bellard26a5f132008-05-28 12:30:31 +0000402{
bellard43694152008-05-29 09:35:57 +0000403#ifdef USE_STATIC_CODE_GEN_BUFFER
404 code_gen_buffer = static_code_gen_buffer;
405 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
406 map_exec(code_gen_buffer, code_gen_buffer_size);
407#else
bellard26a5f132008-05-28 12:30:31 +0000408 code_gen_buffer_size = tb_size;
409 if (code_gen_buffer_size == 0) {
bellard43694152008-05-29 09:35:57 +0000410#if defined(CONFIG_USER_ONLY)
411 /* in user mode, phys_ram_size is not meaningful */
412 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
413#else
bellard26a5f132008-05-28 12:30:31 +0000414 /* XXX: needs ajustments */
aliguori174a9a12008-09-24 14:10:36 +0000415 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
bellard43694152008-05-29 09:35:57 +0000416#endif
bellard26a5f132008-05-28 12:30:31 +0000417 }
418 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
419 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
420 /* The code gen buffer location may have constraints depending on
421 the host cpu and OS */
422#if defined(__linux__)
423 {
424 int flags;
blueswir1141ac462008-07-26 15:05:57 +0000425 void *start = NULL;
426
bellard26a5f132008-05-28 12:30:31 +0000427 flags = MAP_PRIVATE | MAP_ANONYMOUS;
428#if defined(__x86_64__)
429 flags |= MAP_32BIT;
430 /* Cannot map more than that */
431 if (code_gen_buffer_size > (800 * 1024 * 1024))
432 code_gen_buffer_size = (800 * 1024 * 1024);
blueswir1141ac462008-07-26 15:05:57 +0000433#elif defined(__sparc_v9__)
434 // Map the buffer below 2G, so we can use direct calls and branches
435 flags |= MAP_FIXED;
436 start = (void *) 0x60000000UL;
437 if (code_gen_buffer_size > (512 * 1024 * 1024))
438 code_gen_buffer_size = (512 * 1024 * 1024);
bellard26a5f132008-05-28 12:30:31 +0000439#endif
blueswir1141ac462008-07-26 15:05:57 +0000440 code_gen_buffer = mmap(start, code_gen_buffer_size,
441 PROT_WRITE | PROT_READ | PROT_EXEC,
bellard26a5f132008-05-28 12:30:31 +0000442 flags, -1, 0);
443 if (code_gen_buffer == MAP_FAILED) {
444 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
445 exit(1);
446 }
447 }
aliguori06e67a82008-09-27 15:32:41 +0000448#elif defined(__FreeBSD__)
449 {
450 int flags;
451 void *addr = NULL;
452 flags = MAP_PRIVATE | MAP_ANONYMOUS;
453#if defined(__x86_64__)
454 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
455 * 0x40000000 is free */
456 flags |= MAP_FIXED;
457 addr = (void *)0x40000000;
458 /* Cannot map more than that */
459 if (code_gen_buffer_size > (800 * 1024 * 1024))
460 code_gen_buffer_size = (800 * 1024 * 1024);
461#endif
462 code_gen_buffer = mmap(addr, code_gen_buffer_size,
463 PROT_WRITE | PROT_READ | PROT_EXEC,
464 flags, -1, 0);
465 if (code_gen_buffer == MAP_FAILED) {
466 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
467 exit(1);
468 }
469 }
bellard26a5f132008-05-28 12:30:31 +0000470#else
471 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
472 if (!code_gen_buffer) {
473 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
474 exit(1);
475 }
476 map_exec(code_gen_buffer, code_gen_buffer_size);
477#endif
bellard43694152008-05-29 09:35:57 +0000478#endif /* !USE_STATIC_CODE_GEN_BUFFER */
bellard26a5f132008-05-28 12:30:31 +0000479 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
480 code_gen_buffer_max_size = code_gen_buffer_size -
481 code_gen_max_block_size();
482 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
483 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
484}
485
486/* Must be called before using the QEMU cpus. 'tb_size' is the size
487 (in bytes) allocated to the translation buffer. Zero means default
488 size. */
489void cpu_exec_init_all(unsigned long tb_size)
490{
bellard26a5f132008-05-28 12:30:31 +0000491 cpu_gen_init();
492 code_gen_alloc(tb_size);
493 code_gen_ptr = code_gen_buffer;
bellard43694152008-05-29 09:35:57 +0000494 page_init();
pbrooke2eef172008-06-08 01:09:01 +0000495#if !defined(CONFIG_USER_ONLY)
bellard26a5f132008-05-28 12:30:31 +0000496 io_mem_init();
pbrooke2eef172008-06-08 01:09:01 +0000497#endif
bellard26a5f132008-05-28 12:30:31 +0000498}
499
pbrook9656f322008-07-01 20:01:19 +0000500#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
501
502#define CPU_COMMON_SAVE_VERSION 1
503
504static void cpu_common_save(QEMUFile *f, void *opaque)
505{
506 CPUState *env = opaque;
507
508 qemu_put_be32s(f, &env->halted);
509 qemu_put_be32s(f, &env->interrupt_request);
510}
511
512static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
513{
514 CPUState *env = opaque;
515
516 if (version_id != CPU_COMMON_SAVE_VERSION)
517 return -EINVAL;
518
519 qemu_get_be32s(f, &env->halted);
pbrook75f482a2008-07-01 21:53:33 +0000520 qemu_get_be32s(f, &env->interrupt_request);
pbrook9656f322008-07-01 20:01:19 +0000521 tlb_flush(env, 1);
522
523 return 0;
524}
525#endif
526
bellard6a00d602005-11-21 23:25:50 +0000527void cpu_exec_init(CPUState *env)
bellardfd6ce8f2003-05-14 19:00:11 +0000528{
bellard6a00d602005-11-21 23:25:50 +0000529 CPUState **penv;
530 int cpu_index;
531
bellard6a00d602005-11-21 23:25:50 +0000532 env->next_cpu = NULL;
533 penv = &first_cpu;
534 cpu_index = 0;
535 while (*penv != NULL) {
536 penv = (CPUState **)&(*penv)->next_cpu;
537 cpu_index++;
538 }
539 env->cpu_index = cpu_index;
540 *penv = env;
pbrookb3c77242008-06-30 16:31:04 +0000541#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
pbrook9656f322008-07-01 20:01:19 +0000542 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
543 cpu_common_save, cpu_common_load, env);
pbrookb3c77242008-06-30 16:31:04 +0000544 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
545 cpu_save, cpu_load, env);
546#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000547}
548
bellard9fa3e852004-01-04 18:06:42 +0000549static inline void invalidate_page_bitmap(PageDesc *p)
550{
551 if (p->code_bitmap) {
bellard59817cc2004-02-16 22:01:13 +0000552 qemu_free(p->code_bitmap);
bellard9fa3e852004-01-04 18:06:42 +0000553 p->code_bitmap = NULL;
554 }
555 p->code_write_count = 0;
556}
557
bellardfd6ce8f2003-05-14 19:00:11 +0000558/* set to NULL all the 'first_tb' fields in all PageDescs */
559static void page_flush_tb(void)
560{
561 int i, j;
562 PageDesc *p;
563
564 for(i = 0; i < L1_SIZE; i++) {
565 p = l1_map[i];
566 if (p) {
bellard9fa3e852004-01-04 18:06:42 +0000567 for(j = 0; j < L2_SIZE; j++) {
568 p->first_tb = NULL;
569 invalidate_page_bitmap(p);
570 p++;
571 }
bellardfd6ce8f2003-05-14 19:00:11 +0000572 }
573 }
574}
575
576/* flush all the translation blocks */
bellardd4e81642003-05-25 16:46:15 +0000577/* XXX: tb_flush is currently not thread safe */
bellard6a00d602005-11-21 23:25:50 +0000578void tb_flush(CPUState *env1)
bellardfd6ce8f2003-05-14 19:00:11 +0000579{
bellard6a00d602005-11-21 23:25:50 +0000580 CPUState *env;
bellard01243112004-01-04 15:48:17 +0000581#if defined(DEBUG_FLUSH)
blueswir1ab3d1722007-11-04 07:31:40 +0000582 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
583 (unsigned long)(code_gen_ptr - code_gen_buffer),
584 nb_tbs, nb_tbs > 0 ?
585 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
bellardfd6ce8f2003-05-14 19:00:11 +0000586#endif
bellard26a5f132008-05-28 12:30:31 +0000587 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
pbrooka208e542008-03-31 17:07:36 +0000588 cpu_abort(env1, "Internal error: code buffer overflow\n");
589
bellardfd6ce8f2003-05-14 19:00:11 +0000590 nb_tbs = 0;
ths3b46e622007-09-17 08:09:54 +0000591
bellard6a00d602005-11-21 23:25:50 +0000592 for(env = first_cpu; env != NULL; env = env->next_cpu) {
593 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
594 }
bellard9fa3e852004-01-04 18:06:42 +0000595
bellard8a8a6082004-10-03 13:36:49 +0000596 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
bellardfd6ce8f2003-05-14 19:00:11 +0000597 page_flush_tb();
bellard9fa3e852004-01-04 18:06:42 +0000598
bellardfd6ce8f2003-05-14 19:00:11 +0000599 code_gen_ptr = code_gen_buffer;
bellardd4e81642003-05-25 16:46:15 +0000600 /* XXX: flush processor icache at this point if cache flush is
601 expensive */
bellarde3db7222005-01-26 22:00:47 +0000602 tb_flush_count++;
bellardfd6ce8f2003-05-14 19:00:11 +0000603}
604
605#ifdef DEBUG_TB_CHECK
606
j_mayerbc98a7e2007-04-04 07:55:12 +0000607static void tb_invalidate_check(target_ulong address)
bellardfd6ce8f2003-05-14 19:00:11 +0000608{
609 TranslationBlock *tb;
610 int i;
611 address &= TARGET_PAGE_MASK;
pbrook99773bd2006-04-16 15:14:59 +0000612 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
613 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000614 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
615 address >= tb->pc + tb->size)) {
616 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
pbrook99773bd2006-04-16 15:14:59 +0000617 address, (long)tb->pc, tb->size);
bellardfd6ce8f2003-05-14 19:00:11 +0000618 }
619 }
620 }
621}
622
623/* verify that all the pages have correct rights for code */
624static void tb_page_check(void)
625{
626 TranslationBlock *tb;
627 int i, flags1, flags2;
ths3b46e622007-09-17 08:09:54 +0000628
pbrook99773bd2006-04-16 15:14:59 +0000629 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
630 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000631 flags1 = page_get_flags(tb->pc);
632 flags2 = page_get_flags(tb->pc + tb->size - 1);
633 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
634 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
pbrook99773bd2006-04-16 15:14:59 +0000635 (long)tb->pc, tb->size, flags1, flags2);
bellardfd6ce8f2003-05-14 19:00:11 +0000636 }
637 }
638 }
639}
640
blueswir1bdaf78e2008-10-04 07:24:27 +0000641static void tb_jmp_check(TranslationBlock *tb)
bellardd4e81642003-05-25 16:46:15 +0000642{
643 TranslationBlock *tb1;
644 unsigned int n1;
645
646 /* suppress any remaining jumps to this TB */
647 tb1 = tb->jmp_first;
648 for(;;) {
649 n1 = (long)tb1 & 3;
650 tb1 = (TranslationBlock *)((long)tb1 & ~3);
651 if (n1 == 2)
652 break;
653 tb1 = tb1->jmp_next[n1];
654 }
655 /* check end of list */
656 if (tb1 != tb) {
657 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
658 }
659}
660
bellardfd6ce8f2003-05-14 19:00:11 +0000661#endif
662
663/* invalidate one TB */
664static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
665 int next_offset)
666{
667 TranslationBlock *tb1;
668 for(;;) {
669 tb1 = *ptb;
670 if (tb1 == tb) {
671 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
672 break;
673 }
674 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
675 }
676}
677
bellard9fa3e852004-01-04 18:06:42 +0000678static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
679{
680 TranslationBlock *tb1;
681 unsigned int n1;
682
683 for(;;) {
684 tb1 = *ptb;
685 n1 = (long)tb1 & 3;
686 tb1 = (TranslationBlock *)((long)tb1 & ~3);
687 if (tb1 == tb) {
688 *ptb = tb1->page_next[n1];
689 break;
690 }
691 ptb = &tb1->page_next[n1];
692 }
693}
694
bellardd4e81642003-05-25 16:46:15 +0000695static inline void tb_jmp_remove(TranslationBlock *tb, int n)
696{
697 TranslationBlock *tb1, **ptb;
698 unsigned int n1;
699
700 ptb = &tb->jmp_next[n];
701 tb1 = *ptb;
702 if (tb1) {
703 /* find tb(n) in circular list */
704 for(;;) {
705 tb1 = *ptb;
706 n1 = (long)tb1 & 3;
707 tb1 = (TranslationBlock *)((long)tb1 & ~3);
708 if (n1 == n && tb1 == tb)
709 break;
710 if (n1 == 2) {
711 ptb = &tb1->jmp_first;
712 } else {
713 ptb = &tb1->jmp_next[n1];
714 }
715 }
716 /* now we can suppress tb(n) from the list */
717 *ptb = tb->jmp_next[n];
718
719 tb->jmp_next[n] = NULL;
720 }
721}
722
723/* reset the jump entry 'n' of a TB so that it is not chained to
724 another TB */
725static inline void tb_reset_jump(TranslationBlock *tb, int n)
726{
727 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
728}
729
pbrook2e70f6e2008-06-29 01:03:05 +0000730void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000731{
bellard6a00d602005-11-21 23:25:50 +0000732 CPUState *env;
bellardfd6ce8f2003-05-14 19:00:11 +0000733 PageDesc *p;
bellard8a40a182005-11-20 10:35:40 +0000734 unsigned int h, n1;
aurel3200f82b82008-04-27 21:12:55 +0000735 target_phys_addr_t phys_pc;
bellard8a40a182005-11-20 10:35:40 +0000736 TranslationBlock *tb1, *tb2;
ths3b46e622007-09-17 08:09:54 +0000737
bellard9fa3e852004-01-04 18:06:42 +0000738 /* remove the TB from the hash list */
739 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
740 h = tb_phys_hash_func(phys_pc);
ths5fafdf22007-09-16 21:08:06 +0000741 tb_remove(&tb_phys_hash[h], tb,
bellard9fa3e852004-01-04 18:06:42 +0000742 offsetof(TranslationBlock, phys_hash_next));
bellardfd6ce8f2003-05-14 19:00:11 +0000743
bellard9fa3e852004-01-04 18:06:42 +0000744 /* remove the TB from the page list */
745 if (tb->page_addr[0] != page_addr) {
746 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
747 tb_page_remove(&p->first_tb, tb);
748 invalidate_page_bitmap(p);
749 }
750 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
751 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
752 tb_page_remove(&p->first_tb, tb);
753 invalidate_page_bitmap(p);
754 }
755
bellard8a40a182005-11-20 10:35:40 +0000756 tb_invalidated_flag = 1;
757
758 /* remove the TB from the hash list */
759 h = tb_jmp_cache_hash_func(tb->pc);
bellard6a00d602005-11-21 23:25:50 +0000760 for(env = first_cpu; env != NULL; env = env->next_cpu) {
761 if (env->tb_jmp_cache[h] == tb)
762 env->tb_jmp_cache[h] = NULL;
763 }
bellard8a40a182005-11-20 10:35:40 +0000764
765 /* suppress this TB from the two jump lists */
766 tb_jmp_remove(tb, 0);
767 tb_jmp_remove(tb, 1);
768
769 /* suppress any remaining jumps to this TB */
770 tb1 = tb->jmp_first;
771 for(;;) {
772 n1 = (long)tb1 & 3;
773 if (n1 == 2)
774 break;
775 tb1 = (TranslationBlock *)((long)tb1 & ~3);
776 tb2 = tb1->jmp_next[n1];
777 tb_reset_jump(tb1, n1);
778 tb1->jmp_next[n1] = NULL;
779 tb1 = tb2;
780 }
781 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
782
bellarde3db7222005-01-26 22:00:47 +0000783 tb_phys_invalidate_count++;
bellard9fa3e852004-01-04 18:06:42 +0000784}
785
786static inline void set_bits(uint8_t *tab, int start, int len)
787{
788 int end, mask, end1;
789
790 end = start + len;
791 tab += start >> 3;
792 mask = 0xff << (start & 7);
793 if ((start & ~7) == (end & ~7)) {
794 if (start < end) {
795 mask &= ~(0xff << (end & 7));
796 *tab |= mask;
797 }
798 } else {
799 *tab++ |= mask;
800 start = (start + 8) & ~7;
801 end1 = end & ~7;
802 while (start < end1) {
803 *tab++ = 0xff;
804 start += 8;
805 }
806 if (start < end) {
807 mask = ~(0xff << (end & 7));
808 *tab |= mask;
809 }
810 }
811}
812
813static void build_page_bitmap(PageDesc *p)
814{
815 int n, tb_start, tb_end;
816 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +0000817
pbrookb2a70812008-06-09 13:57:23 +0000818 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
bellard9fa3e852004-01-04 18:06:42 +0000819 if (!p->code_bitmap)
820 return;
bellard9fa3e852004-01-04 18:06:42 +0000821
822 tb = p->first_tb;
823 while (tb != NULL) {
824 n = (long)tb & 3;
825 tb = (TranslationBlock *)((long)tb & ~3);
826 /* NOTE: this is subtle as a TB may span two physical pages */
827 if (n == 0) {
828 /* NOTE: tb_end may be after the end of the page, but
829 it is not a problem */
830 tb_start = tb->pc & ~TARGET_PAGE_MASK;
831 tb_end = tb_start + tb->size;
832 if (tb_end > TARGET_PAGE_SIZE)
833 tb_end = TARGET_PAGE_SIZE;
834 } else {
835 tb_start = 0;
836 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
837 }
838 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
839 tb = tb->page_next[n];
840 }
841}
842
pbrook2e70f6e2008-06-29 01:03:05 +0000843TranslationBlock *tb_gen_code(CPUState *env,
844 target_ulong pc, target_ulong cs_base,
845 int flags, int cflags)
bellardd720b932004-04-25 17:57:43 +0000846{
847 TranslationBlock *tb;
848 uint8_t *tc_ptr;
849 target_ulong phys_pc, phys_page2, virt_page2;
850 int code_gen_size;
851
bellardc27004e2005-01-03 23:35:10 +0000852 phys_pc = get_phys_addr_code(env, pc);
853 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000854 if (!tb) {
855 /* flush must be done */
856 tb_flush(env);
857 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000858 tb = tb_alloc(pc);
pbrook2e70f6e2008-06-29 01:03:05 +0000859 /* Don't forget to invalidate previous TB info. */
860 tb_invalidated_flag = 1;
bellardd720b932004-04-25 17:57:43 +0000861 }
862 tc_ptr = code_gen_ptr;
863 tb->tc_ptr = tc_ptr;
864 tb->cs_base = cs_base;
865 tb->flags = flags;
866 tb->cflags = cflags;
blueswir1d07bde82007-12-11 19:35:45 +0000867 cpu_gen_code(env, tb, &code_gen_size);
bellardd720b932004-04-25 17:57:43 +0000868 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000869
bellardd720b932004-04-25 17:57:43 +0000870 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000871 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellardd720b932004-04-25 17:57:43 +0000872 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000873 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
bellardd720b932004-04-25 17:57:43 +0000874 phys_page2 = get_phys_addr_code(env, virt_page2);
875 }
876 tb_link_phys(tb, phys_pc, phys_page2);
pbrook2e70f6e2008-06-29 01:03:05 +0000877 return tb;
bellardd720b932004-04-25 17:57:43 +0000878}
ths3b46e622007-09-17 08:09:54 +0000879
bellard9fa3e852004-01-04 18:06:42 +0000880/* invalidate all TBs which intersect with the target physical page
881 starting in range [start;end[. NOTE: start and end must refer to
bellardd720b932004-04-25 17:57:43 +0000882 the same physical page. 'is_cpu_write_access' should be true if called
883 from a real cpu write access: the virtual CPU will exit the current
884 TB if code is modified inside this TB. */
aurel3200f82b82008-04-27 21:12:55 +0000885void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
bellardd720b932004-04-25 17:57:43 +0000886 int is_cpu_write_access)
bellard9fa3e852004-01-04 18:06:42 +0000887{
aliguori6b917542008-11-18 19:46:41 +0000888 TranslationBlock *tb, *tb_next, *saved_tb;
bellardd720b932004-04-25 17:57:43 +0000889 CPUState *env = cpu_single_env;
bellard9fa3e852004-01-04 18:06:42 +0000890 target_ulong tb_start, tb_end;
aliguori6b917542008-11-18 19:46:41 +0000891 PageDesc *p;
892 int n;
893#ifdef TARGET_HAS_PRECISE_SMC
894 int current_tb_not_found = is_cpu_write_access;
895 TranslationBlock *current_tb = NULL;
896 int current_tb_modified = 0;
897 target_ulong current_pc = 0;
898 target_ulong current_cs_base = 0;
899 int current_flags = 0;
900#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +0000901
902 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000903 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000904 return;
ths5fafdf22007-09-16 21:08:06 +0000905 if (!p->code_bitmap &&
bellardd720b932004-04-25 17:57:43 +0000906 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
907 is_cpu_write_access) {
bellard9fa3e852004-01-04 18:06:42 +0000908 /* build code bitmap */
909 build_page_bitmap(p);
910 }
911
912 /* we remove all the TBs in the range [start, end[ */
913 /* XXX: see if in some cases it could be faster to invalidate all the code */
914 tb = p->first_tb;
915 while (tb != NULL) {
916 n = (long)tb & 3;
917 tb = (TranslationBlock *)((long)tb & ~3);
918 tb_next = tb->page_next[n];
919 /* NOTE: this is subtle as a TB may span two physical pages */
920 if (n == 0) {
921 /* NOTE: tb_end may be after the end of the page, but
922 it is not a problem */
923 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
924 tb_end = tb_start + tb->size;
925 } else {
926 tb_start = tb->page_addr[1];
927 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
928 }
929 if (!(tb_end <= start || tb_start >= end)) {
bellardd720b932004-04-25 17:57:43 +0000930#ifdef TARGET_HAS_PRECISE_SMC
931 if (current_tb_not_found) {
932 current_tb_not_found = 0;
933 current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000934 if (env->mem_io_pc) {
bellardd720b932004-04-25 17:57:43 +0000935 /* now we have a real cpu fault */
pbrook2e70f6e2008-06-29 01:03:05 +0000936 current_tb = tb_find_pc(env->mem_io_pc);
bellardd720b932004-04-25 17:57:43 +0000937 }
938 }
939 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +0000940 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +0000941 /* If we are modifying the current TB, we must stop
942 its execution. We could be more precise by checking
943 that the modification is after the current PC, but it
944 would require a specialized function to partially
945 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +0000946
bellardd720b932004-04-25 17:57:43 +0000947 current_tb_modified = 1;
ths5fafdf22007-09-16 21:08:06 +0000948 cpu_restore_state(current_tb, env,
pbrook2e70f6e2008-06-29 01:03:05 +0000949 env->mem_io_pc, NULL);
aliguori6b917542008-11-18 19:46:41 +0000950 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
951 &current_flags);
bellardd720b932004-04-25 17:57:43 +0000952 }
953#endif /* TARGET_HAS_PRECISE_SMC */
bellard6f5a9f72005-11-26 20:12:28 +0000954 /* we need to do that to handle the case where a signal
955 occurs while doing tb_phys_invalidate() */
956 saved_tb = NULL;
957 if (env) {
958 saved_tb = env->current_tb;
959 env->current_tb = NULL;
960 }
bellard9fa3e852004-01-04 18:06:42 +0000961 tb_phys_invalidate(tb, -1);
bellard6f5a9f72005-11-26 20:12:28 +0000962 if (env) {
963 env->current_tb = saved_tb;
964 if (env->interrupt_request && env->current_tb)
965 cpu_interrupt(env, env->interrupt_request);
966 }
bellard9fa3e852004-01-04 18:06:42 +0000967 }
968 tb = tb_next;
969 }
970#if !defined(CONFIG_USER_ONLY)
971 /* if no code remaining, no need to continue to use slow writes */
972 if (!p->first_tb) {
973 invalidate_page_bitmap(p);
bellardd720b932004-04-25 17:57:43 +0000974 if (is_cpu_write_access) {
pbrook2e70f6e2008-06-29 01:03:05 +0000975 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
bellardd720b932004-04-25 17:57:43 +0000976 }
977 }
978#endif
979#ifdef TARGET_HAS_PRECISE_SMC
980 if (current_tb_modified) {
981 /* we generate a block containing just the instruction
982 modifying the memory. It will ensure that it cannot modify
983 itself */
bellardea1c1802004-06-14 18:56:36 +0000984 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000985 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +0000986 cpu_resume_from_signal(env, NULL);
bellard9fa3e852004-01-04 18:06:42 +0000987 }
988#endif
989}
990
991/* len must be <= 8 and start must be a multiple of len */
aurel3200f82b82008-04-27 21:12:55 +0000992static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
bellard9fa3e852004-01-04 18:06:42 +0000993{
994 PageDesc *p;
995 int offset, b;
bellard59817cc2004-02-16 22:01:13 +0000996#if 0
bellarda4193c82004-06-03 14:01:43 +0000997 if (1) {
998 if (loglevel) {
ths5fafdf22007-09-16 21:08:06 +0000999 fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
pbrook2e70f6e2008-06-29 01:03:05 +00001000 cpu_single_env->mem_io_vaddr, len,
ths5fafdf22007-09-16 21:08:06 +00001001 cpu_single_env->eip,
bellarda4193c82004-06-03 14:01:43 +00001002 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1003 }
bellard59817cc2004-02-16 22:01:13 +00001004 }
1005#endif
bellard9fa3e852004-01-04 18:06:42 +00001006 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001007 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00001008 return;
1009 if (p->code_bitmap) {
1010 offset = start & ~TARGET_PAGE_MASK;
1011 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1012 if (b & ((1 << len) - 1))
1013 goto do_invalidate;
1014 } else {
1015 do_invalidate:
bellardd720b932004-04-25 17:57:43 +00001016 tb_invalidate_phys_page_range(start, start + len, 1);
bellard9fa3e852004-01-04 18:06:42 +00001017 }
1018}
1019
bellard9fa3e852004-01-04 18:06:42 +00001020#if !defined(CONFIG_SOFTMMU)
aurel3200f82b82008-04-27 21:12:55 +00001021static void tb_invalidate_phys_page(target_phys_addr_t addr,
bellardd720b932004-04-25 17:57:43 +00001022 unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001023{
aliguori6b917542008-11-18 19:46:41 +00001024 TranslationBlock *tb;
bellard9fa3e852004-01-04 18:06:42 +00001025 PageDesc *p;
aliguori6b917542008-11-18 19:46:41 +00001026 int n;
bellardd720b932004-04-25 17:57:43 +00001027#ifdef TARGET_HAS_PRECISE_SMC
aliguori6b917542008-11-18 19:46:41 +00001028 TranslationBlock *current_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001029 CPUState *env = cpu_single_env;
aliguori6b917542008-11-18 19:46:41 +00001030 int current_tb_modified = 0;
1031 target_ulong current_pc = 0;
1032 target_ulong current_cs_base = 0;
1033 int current_flags = 0;
bellardd720b932004-04-25 17:57:43 +00001034#endif
bellard9fa3e852004-01-04 18:06:42 +00001035
1036 addr &= TARGET_PAGE_MASK;
1037 p = page_find(addr >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001038 if (!p)
bellardfd6ce8f2003-05-14 19:00:11 +00001039 return;
1040 tb = p->first_tb;
bellardd720b932004-04-25 17:57:43 +00001041#ifdef TARGET_HAS_PRECISE_SMC
1042 if (tb && pc != 0) {
1043 current_tb = tb_find_pc(pc);
1044 }
1045#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001046 while (tb != NULL) {
bellard9fa3e852004-01-04 18:06:42 +00001047 n = (long)tb & 3;
1048 tb = (TranslationBlock *)((long)tb & ~3);
bellardd720b932004-04-25 17:57:43 +00001049#ifdef TARGET_HAS_PRECISE_SMC
1050 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +00001051 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +00001052 /* If we are modifying the current TB, we must stop
1053 its execution. We could be more precise by checking
1054 that the modification is after the current PC, but it
1055 would require a specialized function to partially
1056 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +00001057
bellardd720b932004-04-25 17:57:43 +00001058 current_tb_modified = 1;
1059 cpu_restore_state(current_tb, env, pc, puc);
aliguori6b917542008-11-18 19:46:41 +00001060 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1061 &current_flags);
bellardd720b932004-04-25 17:57:43 +00001062 }
1063#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +00001064 tb_phys_invalidate(tb, addr);
1065 tb = tb->page_next[n];
bellardfd6ce8f2003-05-14 19:00:11 +00001066 }
1067 p->first_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001068#ifdef TARGET_HAS_PRECISE_SMC
1069 if (current_tb_modified) {
1070 /* we generate a block containing just the instruction
1071 modifying the memory. It will ensure that it cannot modify
1072 itself */
bellardea1c1802004-06-14 18:56:36 +00001073 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001074 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001075 cpu_resume_from_signal(env, puc);
1076 }
1077#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001078}
bellard9fa3e852004-01-04 18:06:42 +00001079#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001080
1081/* add the tb in the target page and protect it if necessary */
ths5fafdf22007-09-16 21:08:06 +00001082static inline void tb_alloc_page(TranslationBlock *tb,
pbrook53a59602006-03-25 19:31:22 +00001083 unsigned int n, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +00001084{
1085 PageDesc *p;
bellard9fa3e852004-01-04 18:06:42 +00001086 TranslationBlock *last_first_tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001087
bellard9fa3e852004-01-04 18:06:42 +00001088 tb->page_addr[n] = page_addr;
bellard3a7d9292005-08-21 09:26:42 +00001089 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001090 tb->page_next[n] = p->first_tb;
1091 last_first_tb = p->first_tb;
1092 p->first_tb = (TranslationBlock *)((long)tb | n);
1093 invalidate_page_bitmap(p);
1094
bellard107db442004-06-22 18:48:46 +00001095#if defined(TARGET_HAS_SMC) || 1
bellardd720b932004-04-25 17:57:43 +00001096
bellard9fa3e852004-01-04 18:06:42 +00001097#if defined(CONFIG_USER_ONLY)
bellardfd6ce8f2003-05-14 19:00:11 +00001098 if (p->flags & PAGE_WRITE) {
pbrook53a59602006-03-25 19:31:22 +00001099 target_ulong addr;
1100 PageDesc *p2;
bellard9fa3e852004-01-04 18:06:42 +00001101 int prot;
1102
bellardfd6ce8f2003-05-14 19:00:11 +00001103 /* force the host page as non writable (writes will have a
1104 page fault + mprotect overhead) */
pbrook53a59602006-03-25 19:31:22 +00001105 page_addr &= qemu_host_page_mask;
bellardfd6ce8f2003-05-14 19:00:11 +00001106 prot = 0;
pbrook53a59602006-03-25 19:31:22 +00001107 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1108 addr += TARGET_PAGE_SIZE) {
1109
1110 p2 = page_find (addr >> TARGET_PAGE_BITS);
1111 if (!p2)
1112 continue;
1113 prot |= p2->flags;
1114 p2->flags &= ~PAGE_WRITE;
1115 page_get_flags(addr);
1116 }
ths5fafdf22007-09-16 21:08:06 +00001117 mprotect(g2h(page_addr), qemu_host_page_size,
bellardfd6ce8f2003-05-14 19:00:11 +00001118 (prot & PAGE_BITS) & ~PAGE_WRITE);
1119#ifdef DEBUG_TB_INVALIDATE
blueswir1ab3d1722007-11-04 07:31:40 +00001120 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
pbrook53a59602006-03-25 19:31:22 +00001121 page_addr);
bellardfd6ce8f2003-05-14 19:00:11 +00001122#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001123 }
bellard9fa3e852004-01-04 18:06:42 +00001124#else
1125 /* if some code is already present, then the pages are already
1126 protected. So we handle the case where only the first TB is
1127 allocated in a physical page */
1128 if (!last_first_tb) {
bellard6a00d602005-11-21 23:25:50 +00001129 tlb_protect_code(page_addr);
bellard9fa3e852004-01-04 18:06:42 +00001130 }
1131#endif
bellardd720b932004-04-25 17:57:43 +00001132
1133#endif /* TARGET_HAS_SMC */
bellardfd6ce8f2003-05-14 19:00:11 +00001134}
1135
1136/* Allocate a new translation block. Flush the translation buffer if
1137 too many translation blocks or too much generated code. */
bellardc27004e2005-01-03 23:35:10 +00001138TranslationBlock *tb_alloc(target_ulong pc)
bellardfd6ce8f2003-05-14 19:00:11 +00001139{
1140 TranslationBlock *tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001141
bellard26a5f132008-05-28 12:30:31 +00001142 if (nb_tbs >= code_gen_max_blocks ||
1143 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
bellardd4e81642003-05-25 16:46:15 +00001144 return NULL;
bellardfd6ce8f2003-05-14 19:00:11 +00001145 tb = &tbs[nb_tbs++];
1146 tb->pc = pc;
bellardb448f2f2004-02-25 23:24:04 +00001147 tb->cflags = 0;
bellardd4e81642003-05-25 16:46:15 +00001148 return tb;
1149}
1150
pbrook2e70f6e2008-06-29 01:03:05 +00001151void tb_free(TranslationBlock *tb)
1152{
thsbf20dc02008-06-30 17:22:19 +00001153 /* In practice this is mostly used for single use temporary TB
pbrook2e70f6e2008-06-29 01:03:05 +00001154 Ignore the hard cases and just back up if this TB happens to
1155 be the last one generated. */
1156 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1157 code_gen_ptr = tb->tc_ptr;
1158 nb_tbs--;
1159 }
1160}
1161
bellard9fa3e852004-01-04 18:06:42 +00001162/* add a new TB and link it to the physical page tables. phys_page2 is
1163 (-1) to indicate that only one page contains the TB. */
ths5fafdf22007-09-16 21:08:06 +00001164void tb_link_phys(TranslationBlock *tb,
bellard9fa3e852004-01-04 18:06:42 +00001165 target_ulong phys_pc, target_ulong phys_page2)
bellardd4e81642003-05-25 16:46:15 +00001166{
bellard9fa3e852004-01-04 18:06:42 +00001167 unsigned int h;
1168 TranslationBlock **ptb;
1169
pbrookc8a706f2008-06-02 16:16:42 +00001170 /* Grab the mmap lock to stop another thread invalidating this TB
1171 before we are done. */
1172 mmap_lock();
bellard9fa3e852004-01-04 18:06:42 +00001173 /* add in the physical hash table */
1174 h = tb_phys_hash_func(phys_pc);
1175 ptb = &tb_phys_hash[h];
1176 tb->phys_hash_next = *ptb;
1177 *ptb = tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001178
1179 /* add in the page list */
bellard9fa3e852004-01-04 18:06:42 +00001180 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1181 if (phys_page2 != -1)
1182 tb_alloc_page(tb, 1, phys_page2);
1183 else
1184 tb->page_addr[1] = -1;
bellard9fa3e852004-01-04 18:06:42 +00001185
bellardd4e81642003-05-25 16:46:15 +00001186 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1187 tb->jmp_next[0] = NULL;
1188 tb->jmp_next[1] = NULL;
1189
1190 /* init original jump addresses */
1191 if (tb->tb_next_offset[0] != 0xffff)
1192 tb_reset_jump(tb, 0);
1193 if (tb->tb_next_offset[1] != 0xffff)
1194 tb_reset_jump(tb, 1);
bellard8a40a182005-11-20 10:35:40 +00001195
1196#ifdef DEBUG_TB_CHECK
1197 tb_page_check();
1198#endif
pbrookc8a706f2008-06-02 16:16:42 +00001199 mmap_unlock();
bellardfd6ce8f2003-05-14 19:00:11 +00001200}
1201
bellarda513fe12003-05-27 23:29:48 +00001202/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1203 tb[1].tc_ptr. Return NULL if not found */
1204TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1205{
1206 int m_min, m_max, m;
1207 unsigned long v;
1208 TranslationBlock *tb;
1209
1210 if (nb_tbs <= 0)
1211 return NULL;
1212 if (tc_ptr < (unsigned long)code_gen_buffer ||
1213 tc_ptr >= (unsigned long)code_gen_ptr)
1214 return NULL;
1215 /* binary search (cf Knuth) */
1216 m_min = 0;
1217 m_max = nb_tbs - 1;
1218 while (m_min <= m_max) {
1219 m = (m_min + m_max) >> 1;
1220 tb = &tbs[m];
1221 v = (unsigned long)tb->tc_ptr;
1222 if (v == tc_ptr)
1223 return tb;
1224 else if (tc_ptr < v) {
1225 m_max = m - 1;
1226 } else {
1227 m_min = m + 1;
1228 }
ths5fafdf22007-09-16 21:08:06 +00001229 }
bellarda513fe12003-05-27 23:29:48 +00001230 return &tbs[m_max];
1231}
bellard75012672003-06-21 13:11:07 +00001232
bellardea041c02003-06-25 16:16:50 +00001233static void tb_reset_jump_recursive(TranslationBlock *tb);
1234
1235static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1236{
1237 TranslationBlock *tb1, *tb_next, **ptb;
1238 unsigned int n1;
1239
1240 tb1 = tb->jmp_next[n];
1241 if (tb1 != NULL) {
1242 /* find head of list */
1243 for(;;) {
1244 n1 = (long)tb1 & 3;
1245 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1246 if (n1 == 2)
1247 break;
1248 tb1 = tb1->jmp_next[n1];
1249 }
1250 /* we are now sure now that tb jumps to tb1 */
1251 tb_next = tb1;
1252
1253 /* remove tb from the jmp_first list */
1254 ptb = &tb_next->jmp_first;
1255 for(;;) {
1256 tb1 = *ptb;
1257 n1 = (long)tb1 & 3;
1258 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1259 if (n1 == n && tb1 == tb)
1260 break;
1261 ptb = &tb1->jmp_next[n1];
1262 }
1263 *ptb = tb->jmp_next[n];
1264 tb->jmp_next[n] = NULL;
ths3b46e622007-09-17 08:09:54 +00001265
bellardea041c02003-06-25 16:16:50 +00001266 /* suppress the jump to next tb in generated code */
1267 tb_reset_jump(tb, n);
1268
bellard01243112004-01-04 15:48:17 +00001269 /* suppress jumps in the tb on which we could have jumped */
bellardea041c02003-06-25 16:16:50 +00001270 tb_reset_jump_recursive(tb_next);
1271 }
1272}
1273
1274static void tb_reset_jump_recursive(TranslationBlock *tb)
1275{
1276 tb_reset_jump_recursive2(tb, 0);
1277 tb_reset_jump_recursive2(tb, 1);
1278}
1279
bellard1fddef42005-04-17 19:16:13 +00001280#if defined(TARGET_HAS_ICE)
bellardd720b932004-04-25 17:57:43 +00001281static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1282{
j_mayer9b3c35e2007-04-07 11:21:28 +00001283 target_phys_addr_t addr;
1284 target_ulong pd;
pbrookc2f07f82006-04-08 17:14:56 +00001285 ram_addr_t ram_addr;
1286 PhysPageDesc *p;
bellardd720b932004-04-25 17:57:43 +00001287
pbrookc2f07f82006-04-08 17:14:56 +00001288 addr = cpu_get_phys_page_debug(env, pc);
1289 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1290 if (!p) {
1291 pd = IO_MEM_UNASSIGNED;
1292 } else {
1293 pd = p->phys_offset;
1294 }
1295 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
pbrook706cd4b2006-04-08 17:36:21 +00001296 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
bellardd720b932004-04-25 17:57:43 +00001297}
bellardc27004e2005-01-03 23:35:10 +00001298#endif
bellardd720b932004-04-25 17:57:43 +00001299
pbrook6658ffb2007-03-16 23:58:11 +00001300/* Add a watchpoint. */
aliguoria1d1bb32008-11-18 20:07:32 +00001301int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1302 int flags, CPUWatchpoint **watchpoint)
pbrook6658ffb2007-03-16 23:58:11 +00001303{
aliguorib4051332008-11-18 20:14:20 +00001304 target_ulong len_mask = ~(len - 1);
aliguoria1d1bb32008-11-18 20:07:32 +00001305 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001306
aliguorib4051332008-11-18 20:14:20 +00001307 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1308 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1309 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1310 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1311 return -EINVAL;
1312 }
aliguoria1d1bb32008-11-18 20:07:32 +00001313 wp = qemu_malloc(sizeof(*wp));
1314 if (!wp)
1315 return -ENOBUFS;
pbrook6658ffb2007-03-16 23:58:11 +00001316
aliguoria1d1bb32008-11-18 20:07:32 +00001317 wp->vaddr = addr;
aliguorib4051332008-11-18 20:14:20 +00001318 wp->len_mask = len_mask;
aliguoria1d1bb32008-11-18 20:07:32 +00001319 wp->flags = flags;
1320
1321 wp->next = env->watchpoints;
1322 wp->prev = NULL;
1323 if (wp->next)
1324 wp->next->prev = wp;
1325 env->watchpoints = wp;
1326
pbrook6658ffb2007-03-16 23:58:11 +00001327 tlb_flush_page(env, addr);
1328 /* FIXME: This flush is needed because of the hack to make memory ops
1329 terminate the TB. It can be removed once the proper IO trap and
1330 re-execute bits are in. */
1331 tb_flush(env);
aliguoria1d1bb32008-11-18 20:07:32 +00001332
1333 if (watchpoint)
1334 *watchpoint = wp;
1335 return 0;
pbrook6658ffb2007-03-16 23:58:11 +00001336}
1337
aliguoria1d1bb32008-11-18 20:07:32 +00001338/* Remove a specific watchpoint. */
1339int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1340 int flags)
pbrook6658ffb2007-03-16 23:58:11 +00001341{
aliguorib4051332008-11-18 20:14:20 +00001342 target_ulong len_mask = ~(len - 1);
aliguoria1d1bb32008-11-18 20:07:32 +00001343 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001344
aliguoria1d1bb32008-11-18 20:07:32 +00001345 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
aliguorib4051332008-11-18 20:14:20 +00001346 if (addr == wp->vaddr && len_mask == wp->len_mask
1347 && flags == wp->flags) {
aliguoria1d1bb32008-11-18 20:07:32 +00001348 cpu_watchpoint_remove_by_ref(env, wp);
pbrook6658ffb2007-03-16 23:58:11 +00001349 return 0;
1350 }
1351 }
aliguoria1d1bb32008-11-18 20:07:32 +00001352 return -ENOENT;
pbrook6658ffb2007-03-16 23:58:11 +00001353}
1354
aliguoria1d1bb32008-11-18 20:07:32 +00001355/* Remove a specific watchpoint by reference. */
1356void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1357{
1358 if (watchpoint->next)
1359 watchpoint->next->prev = watchpoint->prev;
1360 if (watchpoint->prev)
1361 watchpoint->prev->next = watchpoint->next;
1362 else
1363 env->watchpoints = watchpoint->next;
edgar_igl7d03f822008-05-17 18:58:29 +00001364
aliguoria1d1bb32008-11-18 20:07:32 +00001365 tlb_flush_page(env, watchpoint->vaddr);
1366
1367 qemu_free(watchpoint);
edgar_igl7d03f822008-05-17 18:58:29 +00001368}
1369
aliguoria1d1bb32008-11-18 20:07:32 +00001370/* Remove all matching watchpoints. */
1371void cpu_watchpoint_remove_all(CPUState *env, int mask)
1372{
1373 CPUWatchpoint *wp;
1374
1375 for (wp = env->watchpoints; wp != NULL; wp = wp->next)
1376 if (wp->flags & mask)
1377 cpu_watchpoint_remove_by_ref(env, wp);
1378}
1379
1380/* Add a breakpoint. */
1381int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1382 CPUBreakpoint **breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001383{
bellard1fddef42005-04-17 19:16:13 +00001384#if defined(TARGET_HAS_ICE)
aliguoria1d1bb32008-11-18 20:07:32 +00001385 CPUBreakpoint *bp;
ths3b46e622007-09-17 08:09:54 +00001386
aliguoria1d1bb32008-11-18 20:07:32 +00001387 bp = qemu_malloc(sizeof(*bp));
1388 if (!bp)
1389 return -ENOBUFS;
1390
1391 bp->pc = pc;
1392 bp->flags = flags;
1393
1394 bp->next = env->breakpoints;
1395 bp->prev = NULL;
1396 if (bp->next)
1397 bp->next->prev = bp;
1398 env->breakpoints = bp;
1399
1400 breakpoint_invalidate(env, pc);
1401
1402 if (breakpoint)
1403 *breakpoint = bp;
1404 return 0;
1405#else
1406 return -ENOSYS;
1407#endif
1408}
1409
1410/* Remove a specific breakpoint. */
1411int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1412{
1413#if defined(TARGET_HAS_ICE)
1414 CPUBreakpoint *bp;
1415
1416 for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
1417 if (bp->pc == pc && bp->flags == flags) {
1418 cpu_breakpoint_remove_by_ref(env, bp);
bellard4c3a88a2003-07-26 12:06:08 +00001419 return 0;
aliguoria1d1bb32008-11-18 20:07:32 +00001420 }
bellard4c3a88a2003-07-26 12:06:08 +00001421 }
aliguoria1d1bb32008-11-18 20:07:32 +00001422 return -ENOENT;
bellard4c3a88a2003-07-26 12:06:08 +00001423#else
aliguoria1d1bb32008-11-18 20:07:32 +00001424 return -ENOSYS;
bellard4c3a88a2003-07-26 12:06:08 +00001425#endif
1426}
1427
aliguoria1d1bb32008-11-18 20:07:32 +00001428/* Remove a specific breakpoint by reference. */
1429void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001430{
bellard1fddef42005-04-17 19:16:13 +00001431#if defined(TARGET_HAS_ICE)
aliguoria1d1bb32008-11-18 20:07:32 +00001432 if (breakpoint->next)
1433 breakpoint->next->prev = breakpoint->prev;
1434 if (breakpoint->prev)
1435 breakpoint->prev->next = breakpoint->next;
1436 else
1437 env->breakpoints = breakpoint->next;
bellardd720b932004-04-25 17:57:43 +00001438
aliguoria1d1bb32008-11-18 20:07:32 +00001439 breakpoint_invalidate(env, breakpoint->pc);
1440
1441 qemu_free(breakpoint);
1442#endif
1443}
1444
1445/* Remove all matching breakpoints. */
1446void cpu_breakpoint_remove_all(CPUState *env, int mask)
1447{
1448#if defined(TARGET_HAS_ICE)
1449 CPUBreakpoint *bp;
1450
1451 for (bp = env->breakpoints; bp != NULL; bp = bp->next)
1452 if (bp->flags & mask)
1453 cpu_breakpoint_remove_by_ref(env, bp);
bellard4c3a88a2003-07-26 12:06:08 +00001454#endif
1455}
1456
bellardc33a3462003-07-29 20:50:33 +00001457/* enable or disable single step mode. EXCP_DEBUG is returned by the
1458 CPU loop after each instruction */
1459void cpu_single_step(CPUState *env, int enabled)
1460{
bellard1fddef42005-04-17 19:16:13 +00001461#if defined(TARGET_HAS_ICE)
bellardc33a3462003-07-29 20:50:33 +00001462 if (env->singlestep_enabled != enabled) {
1463 env->singlestep_enabled = enabled;
1464 /* must flush all the translated code to avoid inconsistancies */
bellard9fa3e852004-01-04 18:06:42 +00001465 /* XXX: only flush what is necessary */
bellard01243112004-01-04 15:48:17 +00001466 tb_flush(env);
bellardc33a3462003-07-29 20:50:33 +00001467 }
1468#endif
1469}
1470
bellard34865132003-10-05 14:28:56 +00001471/* enable or disable low levels log */
1472void cpu_set_log(int log_flags)
1473{
1474 loglevel = log_flags;
1475 if (loglevel && !logfile) {
pbrook11fcfab2007-07-01 18:21:11 +00001476 logfile = fopen(logfilename, log_append ? "a" : "w");
bellard34865132003-10-05 14:28:56 +00001477 if (!logfile) {
1478 perror(logfilename);
1479 _exit(1);
1480 }
bellard9fa3e852004-01-04 18:06:42 +00001481#if !defined(CONFIG_SOFTMMU)
1482 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1483 {
blueswir1b55266b2008-09-20 08:07:15 +00001484 static char logfile_buf[4096];
bellard9fa3e852004-01-04 18:06:42 +00001485 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1486 }
1487#else
bellard34865132003-10-05 14:28:56 +00001488 setvbuf(logfile, NULL, _IOLBF, 0);
bellard9fa3e852004-01-04 18:06:42 +00001489#endif
pbrooke735b912007-06-30 13:53:24 +00001490 log_append = 1;
1491 }
1492 if (!loglevel && logfile) {
1493 fclose(logfile);
1494 logfile = NULL;
bellard34865132003-10-05 14:28:56 +00001495 }
1496}
1497
1498void cpu_set_log_filename(const char *filename)
1499{
1500 logfilename = strdup(filename);
pbrooke735b912007-06-30 13:53:24 +00001501 if (logfile) {
1502 fclose(logfile);
1503 logfile = NULL;
1504 }
1505 cpu_set_log(loglevel);
bellard34865132003-10-05 14:28:56 +00001506}
bellardc33a3462003-07-29 20:50:33 +00001507
bellard01243112004-01-04 15:48:17 +00001508/* mask must never be zero, except for A20 change call */
bellard68a79312003-06-30 13:12:32 +00001509void cpu_interrupt(CPUState *env, int mask)
bellardea041c02003-06-25 16:16:50 +00001510{
pbrookd5975362008-06-07 20:50:51 +00001511#if !defined(USE_NPTL)
bellardea041c02003-06-25 16:16:50 +00001512 TranslationBlock *tb;
aurel3215a51152008-03-28 22:29:15 +00001513 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
pbrookd5975362008-06-07 20:50:51 +00001514#endif
pbrook2e70f6e2008-06-29 01:03:05 +00001515 int old_mask;
bellard59817cc2004-02-16 22:01:13 +00001516
pbrook2e70f6e2008-06-29 01:03:05 +00001517 old_mask = env->interrupt_request;
pbrookd5975362008-06-07 20:50:51 +00001518 /* FIXME: This is probably not threadsafe. A different thread could
thsbf20dc02008-06-30 17:22:19 +00001519 be in the middle of a read-modify-write operation. */
bellard68a79312003-06-30 13:12:32 +00001520 env->interrupt_request |= mask;
pbrookd5975362008-06-07 20:50:51 +00001521#if defined(USE_NPTL)
1522 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1523 problem and hope the cpu will stop of its own accord. For userspace
1524 emulation this often isn't actually as bad as it sounds. Often
1525 signals are used primarily to interrupt blocking syscalls. */
1526#else
pbrook2e70f6e2008-06-29 01:03:05 +00001527 if (use_icount) {
pbrook266910c2008-07-09 15:31:50 +00001528 env->icount_decr.u16.high = 0xffff;
pbrook2e70f6e2008-06-29 01:03:05 +00001529#ifndef CONFIG_USER_ONLY
1530 /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
1531 an async event happened and we need to process it. */
1532 if (!can_do_io(env)
1533 && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
1534 cpu_abort(env, "Raised interrupt while not in I/O function");
1535 }
1536#endif
1537 } else {
1538 tb = env->current_tb;
1539 /* if the cpu is currently executing code, we must unlink it and
1540 all the potentially executing TB */
1541 if (tb && !testandset(&interrupt_lock)) {
1542 env->current_tb = NULL;
1543 tb_reset_jump_recursive(tb);
1544 resetlock(&interrupt_lock);
1545 }
bellardea041c02003-06-25 16:16:50 +00001546 }
pbrookd5975362008-06-07 20:50:51 +00001547#endif
bellardea041c02003-06-25 16:16:50 +00001548}
1549
bellardb54ad042004-05-20 13:42:52 +00001550void cpu_reset_interrupt(CPUState *env, int mask)
1551{
1552 env->interrupt_request &= ~mask;
1553}
1554
blueswir1c7cd6a32008-10-02 18:27:46 +00001555const CPULogItem cpu_log_items[] = {
ths5fafdf22007-09-16 21:08:06 +00001556 { CPU_LOG_TB_OUT_ASM, "out_asm",
bellardf193c792004-03-21 17:06:25 +00001557 "show generated host assembly code for each compiled TB" },
1558 { CPU_LOG_TB_IN_ASM, "in_asm",
1559 "show target assembly code for each compiled TB" },
ths5fafdf22007-09-16 21:08:06 +00001560 { CPU_LOG_TB_OP, "op",
bellard57fec1f2008-02-01 10:50:11 +00001561 "show micro ops for each compiled TB" },
bellardf193c792004-03-21 17:06:25 +00001562 { CPU_LOG_TB_OP_OPT, "op_opt",
blueswir1e01a1152008-03-14 17:37:11 +00001563 "show micro ops "
1564#ifdef TARGET_I386
1565 "before eflags optimization and "
bellardf193c792004-03-21 17:06:25 +00001566#endif
blueswir1e01a1152008-03-14 17:37:11 +00001567 "after liveness analysis" },
bellardf193c792004-03-21 17:06:25 +00001568 { CPU_LOG_INT, "int",
1569 "show interrupts/exceptions in short format" },
1570 { CPU_LOG_EXEC, "exec",
1571 "show trace before each executed TB (lots of logs)" },
bellard9fddaa02004-05-21 12:59:32 +00001572 { CPU_LOG_TB_CPU, "cpu",
thse91c8a72007-06-03 13:35:16 +00001573 "show CPU state before block translation" },
bellardf193c792004-03-21 17:06:25 +00001574#ifdef TARGET_I386
1575 { CPU_LOG_PCALL, "pcall",
1576 "show protected mode far calls/returns/exceptions" },
1577#endif
bellard8e3a9fd2004-10-09 17:32:58 +00001578#ifdef DEBUG_IOPORT
bellardfd872592004-05-12 19:11:15 +00001579 { CPU_LOG_IOPORT, "ioport",
1580 "show all i/o ports accesses" },
bellard8e3a9fd2004-10-09 17:32:58 +00001581#endif
bellardf193c792004-03-21 17:06:25 +00001582 { 0, NULL, NULL },
1583};
1584
1585static int cmp1(const char *s1, int n, const char *s2)
1586{
1587 if (strlen(s2) != n)
1588 return 0;
1589 return memcmp(s1, s2, n) == 0;
1590}
ths3b46e622007-09-17 08:09:54 +00001591
bellardf193c792004-03-21 17:06:25 +00001592/* takes a comma separated list of log masks. Return 0 if error. */
1593int cpu_str_to_log_mask(const char *str)
1594{
blueswir1c7cd6a32008-10-02 18:27:46 +00001595 const CPULogItem *item;
bellardf193c792004-03-21 17:06:25 +00001596 int mask;
1597 const char *p, *p1;
1598
1599 p = str;
1600 mask = 0;
1601 for(;;) {
1602 p1 = strchr(p, ',');
1603 if (!p1)
1604 p1 = p + strlen(p);
bellard8e3a9fd2004-10-09 17:32:58 +00001605 if(cmp1(p,p1-p,"all")) {
1606 for(item = cpu_log_items; item->mask != 0; item++) {
1607 mask |= item->mask;
1608 }
1609 } else {
bellardf193c792004-03-21 17:06:25 +00001610 for(item = cpu_log_items; item->mask != 0; item++) {
1611 if (cmp1(p, p1 - p, item->name))
1612 goto found;
1613 }
1614 return 0;
bellard8e3a9fd2004-10-09 17:32:58 +00001615 }
bellardf193c792004-03-21 17:06:25 +00001616 found:
1617 mask |= item->mask;
1618 if (*p1 != ',')
1619 break;
1620 p = p1 + 1;
1621 }
1622 return mask;
1623}
bellardea041c02003-06-25 16:16:50 +00001624
bellard75012672003-06-21 13:11:07 +00001625void cpu_abort(CPUState *env, const char *fmt, ...)
1626{
1627 va_list ap;
pbrook493ae1f2007-11-23 16:53:59 +00001628 va_list ap2;
bellard75012672003-06-21 13:11:07 +00001629
1630 va_start(ap, fmt);
pbrook493ae1f2007-11-23 16:53:59 +00001631 va_copy(ap2, ap);
bellard75012672003-06-21 13:11:07 +00001632 fprintf(stderr, "qemu: fatal: ");
1633 vfprintf(stderr, fmt, ap);
1634 fprintf(stderr, "\n");
1635#ifdef TARGET_I386
bellard7fe48482004-10-09 18:08:01 +00001636 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1637#else
1638 cpu_dump_state(env, stderr, fprintf, 0);
bellard75012672003-06-21 13:11:07 +00001639#endif
balrog924edca2007-06-10 14:07:13 +00001640 if (logfile) {
j_mayerf9373292007-09-29 12:18:20 +00001641 fprintf(logfile, "qemu: fatal: ");
pbrook493ae1f2007-11-23 16:53:59 +00001642 vfprintf(logfile, fmt, ap2);
j_mayerf9373292007-09-29 12:18:20 +00001643 fprintf(logfile, "\n");
1644#ifdef TARGET_I386
1645 cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1646#else
1647 cpu_dump_state(env, logfile, fprintf, 0);
1648#endif
balrog924edca2007-06-10 14:07:13 +00001649 fflush(logfile);
1650 fclose(logfile);
1651 }
pbrook493ae1f2007-11-23 16:53:59 +00001652 va_end(ap2);
j_mayerf9373292007-09-29 12:18:20 +00001653 va_end(ap);
bellard75012672003-06-21 13:11:07 +00001654 abort();
1655}
1656
thsc5be9f02007-02-28 20:20:53 +00001657CPUState *cpu_copy(CPUState *env)
1658{
ths01ba9812007-12-09 02:22:57 +00001659 CPUState *new_env = cpu_init(env->cpu_model_str);
thsc5be9f02007-02-28 20:20:53 +00001660 /* preserve chaining and index */
1661 CPUState *next_cpu = new_env->next_cpu;
1662 int cpu_index = new_env->cpu_index;
1663 memcpy(new_env, env, sizeof(CPUState));
1664 new_env->next_cpu = next_cpu;
1665 new_env->cpu_index = cpu_index;
1666 return new_env;
1667}
1668
bellard01243112004-01-04 15:48:17 +00001669#if !defined(CONFIG_USER_ONLY)
1670
edgar_igl5c751e92008-05-06 08:44:21 +00001671static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1672{
1673 unsigned int i;
1674
1675 /* Discard jump cache entries for any tb which might potentially
1676 overlap the flushed page. */
1677 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1678 memset (&env->tb_jmp_cache[i], 0,
1679 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1680
1681 i = tb_jmp_cache_hash_page(addr);
1682 memset (&env->tb_jmp_cache[i], 0,
1683 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1684}
1685
bellardee8b7022004-02-03 23:35:10 +00001686/* NOTE: if flush_global is true, also flush global entries (not
1687 implemented yet) */
1688void tlb_flush(CPUState *env, int flush_global)
bellard33417e72003-08-10 21:47:01 +00001689{
bellard33417e72003-08-10 21:47:01 +00001690 int i;
bellard01243112004-01-04 15:48:17 +00001691
bellard9fa3e852004-01-04 18:06:42 +00001692#if defined(DEBUG_TLB)
1693 printf("tlb_flush:\n");
1694#endif
bellard01243112004-01-04 15:48:17 +00001695 /* must reset current TB so that interrupts cannot modify the
1696 links while we are modifying them */
1697 env->current_tb = NULL;
1698
bellard33417e72003-08-10 21:47:01 +00001699 for(i = 0; i < CPU_TLB_SIZE; i++) {
bellard84b7b8e2005-11-28 21:19:04 +00001700 env->tlb_table[0][i].addr_read = -1;
1701 env->tlb_table[0][i].addr_write = -1;
1702 env->tlb_table[0][i].addr_code = -1;
1703 env->tlb_table[1][i].addr_read = -1;
1704 env->tlb_table[1][i].addr_write = -1;
1705 env->tlb_table[1][i].addr_code = -1;
j_mayer6fa4cea2007-04-05 06:43:27 +00001706#if (NB_MMU_MODES >= 3)
1707 env->tlb_table[2][i].addr_read = -1;
1708 env->tlb_table[2][i].addr_write = -1;
1709 env->tlb_table[2][i].addr_code = -1;
1710#if (NB_MMU_MODES == 4)
1711 env->tlb_table[3][i].addr_read = -1;
1712 env->tlb_table[3][i].addr_write = -1;
1713 env->tlb_table[3][i].addr_code = -1;
1714#endif
1715#endif
bellard33417e72003-08-10 21:47:01 +00001716 }
bellard9fa3e852004-01-04 18:06:42 +00001717
bellard8a40a182005-11-20 10:35:40 +00001718 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
bellard9fa3e852004-01-04 18:06:42 +00001719
bellard0a962c02005-02-10 22:00:27 +00001720#ifdef USE_KQEMU
1721 if (env->kqemu_enabled) {
1722 kqemu_flush(env, flush_global);
1723 }
1724#endif
bellarde3db7222005-01-26 22:00:47 +00001725 tlb_flush_count++;
bellard33417e72003-08-10 21:47:01 +00001726}
1727
bellard274da6b2004-05-20 21:56:27 +00001728static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
bellard61382a52003-10-27 21:22:23 +00001729{
ths5fafdf22007-09-16 21:08:06 +00001730 if (addr == (tlb_entry->addr_read &
bellard84b7b8e2005-11-28 21:19:04 +00001731 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001732 addr == (tlb_entry->addr_write &
bellard84b7b8e2005-11-28 21:19:04 +00001733 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001734 addr == (tlb_entry->addr_code &
bellard84b7b8e2005-11-28 21:19:04 +00001735 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1736 tlb_entry->addr_read = -1;
1737 tlb_entry->addr_write = -1;
1738 tlb_entry->addr_code = -1;
1739 }
bellard61382a52003-10-27 21:22:23 +00001740}
1741
bellard2e126692004-04-25 21:28:44 +00001742void tlb_flush_page(CPUState *env, target_ulong addr)
bellard33417e72003-08-10 21:47:01 +00001743{
bellard8a40a182005-11-20 10:35:40 +00001744 int i;
bellard01243112004-01-04 15:48:17 +00001745
bellard9fa3e852004-01-04 18:06:42 +00001746#if defined(DEBUG_TLB)
bellard108c49b2005-07-24 12:55:09 +00001747 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
bellard9fa3e852004-01-04 18:06:42 +00001748#endif
bellard01243112004-01-04 15:48:17 +00001749 /* must reset current TB so that interrupts cannot modify the
1750 links while we are modifying them */
1751 env->current_tb = NULL;
bellard33417e72003-08-10 21:47:01 +00001752
bellard61382a52003-10-27 21:22:23 +00001753 addr &= TARGET_PAGE_MASK;
bellard33417e72003-08-10 21:47:01 +00001754 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard84b7b8e2005-11-28 21:19:04 +00001755 tlb_flush_entry(&env->tlb_table[0][i], addr);
1756 tlb_flush_entry(&env->tlb_table[1][i], addr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001757#if (NB_MMU_MODES >= 3)
1758 tlb_flush_entry(&env->tlb_table[2][i], addr);
1759#if (NB_MMU_MODES == 4)
1760 tlb_flush_entry(&env->tlb_table[3][i], addr);
1761#endif
1762#endif
bellard01243112004-01-04 15:48:17 +00001763
edgar_igl5c751e92008-05-06 08:44:21 +00001764 tlb_flush_jmp_cache(env, addr);
bellard9fa3e852004-01-04 18:06:42 +00001765
bellard0a962c02005-02-10 22:00:27 +00001766#ifdef USE_KQEMU
1767 if (env->kqemu_enabled) {
1768 kqemu_flush_page(env, addr);
1769 }
1770#endif
bellard9fa3e852004-01-04 18:06:42 +00001771}
1772
bellard9fa3e852004-01-04 18:06:42 +00001773/* update the TLBs so that writes to code in the virtual page 'addr'
1774 can be detected */
bellard6a00d602005-11-21 23:25:50 +00001775static void tlb_protect_code(ram_addr_t ram_addr)
bellard61382a52003-10-27 21:22:23 +00001776{
ths5fafdf22007-09-16 21:08:06 +00001777 cpu_physical_memory_reset_dirty(ram_addr,
bellard6a00d602005-11-21 23:25:50 +00001778 ram_addr + TARGET_PAGE_SIZE,
1779 CODE_DIRTY_FLAG);
bellard9fa3e852004-01-04 18:06:42 +00001780}
1781
bellard9fa3e852004-01-04 18:06:42 +00001782/* update the TLB so that writes in physical page 'phys_addr' are no longer
bellard3a7d9292005-08-21 09:26:42 +00001783 tested for self modifying code */
ths5fafdf22007-09-16 21:08:06 +00001784static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +00001785 target_ulong vaddr)
bellard9fa3e852004-01-04 18:06:42 +00001786{
bellard3a7d9292005-08-21 09:26:42 +00001787 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
bellard1ccde1c2004-02-06 19:46:14 +00001788}
1789
ths5fafdf22007-09-16 21:08:06 +00001790static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
bellard1ccde1c2004-02-06 19:46:14 +00001791 unsigned long start, unsigned long length)
1792{
1793 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00001794 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1795 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00001796 if ((addr - start) < length) {
pbrook0f459d12008-06-09 00:20:13 +00001797 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
bellard1ccde1c2004-02-06 19:46:14 +00001798 }
1799 }
1800}
1801
bellard3a7d9292005-08-21 09:26:42 +00001802void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +00001803 int dirty_flags)
bellard1ccde1c2004-02-06 19:46:14 +00001804{
1805 CPUState *env;
bellard4f2ac232004-04-26 19:44:02 +00001806 unsigned long length, start1;
bellard0a962c02005-02-10 22:00:27 +00001807 int i, mask, len;
1808 uint8_t *p;
bellard1ccde1c2004-02-06 19:46:14 +00001809
1810 start &= TARGET_PAGE_MASK;
1811 end = TARGET_PAGE_ALIGN(end);
1812
1813 length = end - start;
1814 if (length == 0)
1815 return;
bellard0a962c02005-02-10 22:00:27 +00001816 len = length >> TARGET_PAGE_BITS;
bellard3a7d9292005-08-21 09:26:42 +00001817#ifdef USE_KQEMU
bellard6a00d602005-11-21 23:25:50 +00001818 /* XXX: should not depend on cpu context */
1819 env = first_cpu;
bellard3a7d9292005-08-21 09:26:42 +00001820 if (env->kqemu_enabled) {
bellardf23db162005-08-21 19:12:28 +00001821 ram_addr_t addr;
1822 addr = start;
1823 for(i = 0; i < len; i++) {
1824 kqemu_set_notdirty(env, addr);
1825 addr += TARGET_PAGE_SIZE;
1826 }
bellard3a7d9292005-08-21 09:26:42 +00001827 }
1828#endif
bellardf23db162005-08-21 19:12:28 +00001829 mask = ~dirty_flags;
1830 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1831 for(i = 0; i < len; i++)
1832 p[i] &= mask;
1833
bellard1ccde1c2004-02-06 19:46:14 +00001834 /* we modify the TLB cache so that the dirty bit will be set again
1835 when accessing the range */
bellard59817cc2004-02-16 22:01:13 +00001836 start1 = start + (unsigned long)phys_ram_base;
bellard6a00d602005-11-21 23:25:50 +00001837 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1838 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001839 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
bellard6a00d602005-11-21 23:25:50 +00001840 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001841 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
j_mayer6fa4cea2007-04-05 06:43:27 +00001842#if (NB_MMU_MODES >= 3)
1843 for(i = 0; i < CPU_TLB_SIZE; i++)
1844 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1845#if (NB_MMU_MODES == 4)
1846 for(i = 0; i < CPU_TLB_SIZE; i++)
1847 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1848#endif
1849#endif
bellard6a00d602005-11-21 23:25:50 +00001850 }
bellard1ccde1c2004-02-06 19:46:14 +00001851}
1852
aliguori74576192008-10-06 14:02:03 +00001853int cpu_physical_memory_set_dirty_tracking(int enable)
1854{
1855 in_migration = enable;
1856 return 0;
1857}
1858
1859int cpu_physical_memory_get_dirty_tracking(void)
1860{
1861 return in_migration;
1862}
1863
bellard3a7d9292005-08-21 09:26:42 +00001864static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1865{
1866 ram_addr_t ram_addr;
1867
bellard84b7b8e2005-11-28 21:19:04 +00001868 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
ths5fafdf22007-09-16 21:08:06 +00001869 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
bellard3a7d9292005-08-21 09:26:42 +00001870 tlb_entry->addend - (unsigned long)phys_ram_base;
1871 if (!cpu_physical_memory_is_dirty(ram_addr)) {
pbrook0f459d12008-06-09 00:20:13 +00001872 tlb_entry->addr_write |= TLB_NOTDIRTY;
bellard3a7d9292005-08-21 09:26:42 +00001873 }
1874 }
1875}
1876
1877/* update the TLB according to the current state of the dirty bits */
1878void cpu_tlb_update_dirty(CPUState *env)
1879{
1880 int i;
1881 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001882 tlb_update_dirty(&env->tlb_table[0][i]);
bellard3a7d9292005-08-21 09:26:42 +00001883 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001884 tlb_update_dirty(&env->tlb_table[1][i]);
j_mayer6fa4cea2007-04-05 06:43:27 +00001885#if (NB_MMU_MODES >= 3)
1886 for(i = 0; i < CPU_TLB_SIZE; i++)
1887 tlb_update_dirty(&env->tlb_table[2][i]);
1888#if (NB_MMU_MODES == 4)
1889 for(i = 0; i < CPU_TLB_SIZE; i++)
1890 tlb_update_dirty(&env->tlb_table[3][i]);
1891#endif
1892#endif
bellard3a7d9292005-08-21 09:26:42 +00001893}
1894
pbrook0f459d12008-06-09 00:20:13 +00001895static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001896{
pbrook0f459d12008-06-09 00:20:13 +00001897 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
1898 tlb_entry->addr_write = vaddr;
bellard1ccde1c2004-02-06 19:46:14 +00001899}
1900
pbrook0f459d12008-06-09 00:20:13 +00001901/* update the TLB corresponding to virtual page vaddr
1902 so that it is no longer dirty */
1903static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001904{
bellard1ccde1c2004-02-06 19:46:14 +00001905 int i;
1906
pbrook0f459d12008-06-09 00:20:13 +00001907 vaddr &= TARGET_PAGE_MASK;
bellard1ccde1c2004-02-06 19:46:14 +00001908 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
pbrook0f459d12008-06-09 00:20:13 +00001909 tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
1910 tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001911#if (NB_MMU_MODES >= 3)
pbrook0f459d12008-06-09 00:20:13 +00001912 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001913#if (NB_MMU_MODES == 4)
pbrook0f459d12008-06-09 00:20:13 +00001914 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001915#endif
1916#endif
bellard9fa3e852004-01-04 18:06:42 +00001917}
1918
bellard59817cc2004-02-16 22:01:13 +00001919/* add a new TLB entry. At most one entry for a given virtual address
1920 is permitted. Return 0 if OK or 2 if the page could not be mapped
1921 (can only happen in non SOFTMMU mode for I/O pages or pages
1922 conflicting with the host address space). */
ths5fafdf22007-09-16 21:08:06 +00001923int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1924 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00001925 int mmu_idx, int is_softmmu)
bellard9fa3e852004-01-04 18:06:42 +00001926{
bellard92e873b2004-05-21 14:52:29 +00001927 PhysPageDesc *p;
bellard4f2ac232004-04-26 19:44:02 +00001928 unsigned long pd;
bellard9fa3e852004-01-04 18:06:42 +00001929 unsigned int index;
bellard4f2ac232004-04-26 19:44:02 +00001930 target_ulong address;
pbrook0f459d12008-06-09 00:20:13 +00001931 target_ulong code_address;
bellard108c49b2005-07-24 12:55:09 +00001932 target_phys_addr_t addend;
bellard9fa3e852004-01-04 18:06:42 +00001933 int ret;
bellard84b7b8e2005-11-28 21:19:04 +00001934 CPUTLBEntry *te;
aliguoria1d1bb32008-11-18 20:07:32 +00001935 CPUWatchpoint *wp;
pbrook0f459d12008-06-09 00:20:13 +00001936 target_phys_addr_t iotlb;
bellard9fa3e852004-01-04 18:06:42 +00001937
bellard92e873b2004-05-21 14:52:29 +00001938 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001939 if (!p) {
1940 pd = IO_MEM_UNASSIGNED;
bellard9fa3e852004-01-04 18:06:42 +00001941 } else {
1942 pd = p->phys_offset;
bellard9fa3e852004-01-04 18:06:42 +00001943 }
1944#if defined(DEBUG_TLB)
j_mayer6ebbf392007-10-14 07:07:08 +00001945 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1946 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
bellard9fa3e852004-01-04 18:06:42 +00001947#endif
1948
1949 ret = 0;
pbrook0f459d12008-06-09 00:20:13 +00001950 address = vaddr;
1951 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1952 /* IO memory case (romd handled later) */
1953 address |= TLB_MMIO;
1954 }
1955 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1956 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
1957 /* Normal RAM. */
1958 iotlb = pd & TARGET_PAGE_MASK;
1959 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
1960 iotlb |= IO_MEM_NOTDIRTY;
1961 else
1962 iotlb |= IO_MEM_ROM;
1963 } else {
1964 /* IO handlers are currently passed a phsical address.
1965 It would be nice to pass an offset from the base address
1966 of that region. This would avoid having to special case RAM,
1967 and avoid full address decoding in every device.
1968 We can't use the high bits of pd for this because
1969 IO_MEM_ROMD uses these as a ram address. */
1970 iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
1971 }
pbrook6658ffb2007-03-16 23:58:11 +00001972
pbrook0f459d12008-06-09 00:20:13 +00001973 code_address = address;
1974 /* Make accesses to pages with watchpoints go via the
1975 watchpoint trap routines. */
aliguoria1d1bb32008-11-18 20:07:32 +00001976 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
1977 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
pbrook0f459d12008-06-09 00:20:13 +00001978 iotlb = io_mem_watch + paddr;
1979 /* TODO: The memory case can be optimized by not trapping
1980 reads of pages with a write breakpoint. */
1981 address |= TLB_MMIO;
pbrook6658ffb2007-03-16 23:58:11 +00001982 }
pbrook0f459d12008-06-09 00:20:13 +00001983 }
balrogd79acba2007-06-26 20:01:13 +00001984
pbrook0f459d12008-06-09 00:20:13 +00001985 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1986 env->iotlb[mmu_idx][index] = iotlb - vaddr;
1987 te = &env->tlb_table[mmu_idx][index];
1988 te->addend = addend - vaddr;
1989 if (prot & PAGE_READ) {
1990 te->addr_read = address;
1991 } else {
1992 te->addr_read = -1;
1993 }
edgar_igl5c751e92008-05-06 08:44:21 +00001994
pbrook0f459d12008-06-09 00:20:13 +00001995 if (prot & PAGE_EXEC) {
1996 te->addr_code = code_address;
1997 } else {
1998 te->addr_code = -1;
1999 }
2000 if (prot & PAGE_WRITE) {
2001 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2002 (pd & IO_MEM_ROMD)) {
2003 /* Write access calls the I/O callback. */
2004 te->addr_write = address | TLB_MMIO;
2005 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2006 !cpu_physical_memory_is_dirty(pd)) {
2007 te->addr_write = address | TLB_NOTDIRTY;
bellard84b7b8e2005-11-28 21:19:04 +00002008 } else {
pbrook0f459d12008-06-09 00:20:13 +00002009 te->addr_write = address;
bellard9fa3e852004-01-04 18:06:42 +00002010 }
pbrook0f459d12008-06-09 00:20:13 +00002011 } else {
2012 te->addr_write = -1;
bellard9fa3e852004-01-04 18:06:42 +00002013 }
bellard9fa3e852004-01-04 18:06:42 +00002014 return ret;
2015}
2016
bellard01243112004-01-04 15:48:17 +00002017#else
2018
bellardee8b7022004-02-03 23:35:10 +00002019void tlb_flush(CPUState *env, int flush_global)
bellard01243112004-01-04 15:48:17 +00002020{
2021}
2022
bellard2e126692004-04-25 21:28:44 +00002023void tlb_flush_page(CPUState *env, target_ulong addr)
bellard01243112004-01-04 15:48:17 +00002024{
2025}
2026
ths5fafdf22007-09-16 21:08:06 +00002027int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2028 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00002029 int mmu_idx, int is_softmmu)
bellard33417e72003-08-10 21:47:01 +00002030{
bellard9fa3e852004-01-04 18:06:42 +00002031 return 0;
2032}
bellard33417e72003-08-10 21:47:01 +00002033
bellard9fa3e852004-01-04 18:06:42 +00002034/* dump memory mappings */
2035void page_dump(FILE *f)
2036{
2037 unsigned long start, end;
2038 int i, j, prot, prot1;
2039 PageDesc *p;
2040
2041 fprintf(f, "%-8s %-8s %-8s %s\n",
2042 "start", "end", "size", "prot");
2043 start = -1;
2044 end = -1;
2045 prot = 0;
2046 for(i = 0; i <= L1_SIZE; i++) {
2047 if (i < L1_SIZE)
2048 p = l1_map[i];
2049 else
2050 p = NULL;
2051 for(j = 0;j < L2_SIZE; j++) {
2052 if (!p)
2053 prot1 = 0;
2054 else
2055 prot1 = p[j].flags;
2056 if (prot1 != prot) {
2057 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2058 if (start != -1) {
2059 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
ths5fafdf22007-09-16 21:08:06 +00002060 start, end, end - start,
bellard9fa3e852004-01-04 18:06:42 +00002061 prot & PAGE_READ ? 'r' : '-',
2062 prot & PAGE_WRITE ? 'w' : '-',
2063 prot & PAGE_EXEC ? 'x' : '-');
2064 }
2065 if (prot1 != 0)
2066 start = end;
2067 else
2068 start = -1;
2069 prot = prot1;
2070 }
2071 if (!p)
2072 break;
2073 }
bellard33417e72003-08-10 21:47:01 +00002074 }
bellard33417e72003-08-10 21:47:01 +00002075}
2076
pbrook53a59602006-03-25 19:31:22 +00002077int page_get_flags(target_ulong address)
bellard33417e72003-08-10 21:47:01 +00002078{
bellard9fa3e852004-01-04 18:06:42 +00002079 PageDesc *p;
2080
2081 p = page_find(address >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002082 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00002083 return 0;
2084 return p->flags;
bellard33417e72003-08-10 21:47:01 +00002085}
2086
bellard9fa3e852004-01-04 18:06:42 +00002087/* modify the flags of a page and invalidate the code if
2088 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2089 depending on PAGE_WRITE */
pbrook53a59602006-03-25 19:31:22 +00002090void page_set_flags(target_ulong start, target_ulong end, int flags)
bellard9fa3e852004-01-04 18:06:42 +00002091{
2092 PageDesc *p;
pbrook53a59602006-03-25 19:31:22 +00002093 target_ulong addr;
bellard9fa3e852004-01-04 18:06:42 +00002094
pbrookc8a706f2008-06-02 16:16:42 +00002095 /* mmap_lock should already be held. */
bellard9fa3e852004-01-04 18:06:42 +00002096 start = start & TARGET_PAGE_MASK;
2097 end = TARGET_PAGE_ALIGN(end);
2098 if (flags & PAGE_WRITE)
2099 flags |= PAGE_WRITE_ORG;
bellard9fa3e852004-01-04 18:06:42 +00002100 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2101 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
pbrook17e23772008-06-09 13:47:45 +00002102 /* We may be called for host regions that are outside guest
2103 address space. */
2104 if (!p)
2105 return;
bellard9fa3e852004-01-04 18:06:42 +00002106 /* if the write protection is set, then we invalidate the code
2107 inside */
ths5fafdf22007-09-16 21:08:06 +00002108 if (!(p->flags & PAGE_WRITE) &&
bellard9fa3e852004-01-04 18:06:42 +00002109 (flags & PAGE_WRITE) &&
2110 p->first_tb) {
bellardd720b932004-04-25 17:57:43 +00002111 tb_invalidate_phys_page(addr, 0, NULL);
bellard9fa3e852004-01-04 18:06:42 +00002112 }
2113 p->flags = flags;
2114 }
bellard9fa3e852004-01-04 18:06:42 +00002115}
2116
ths3d97b402007-11-02 19:02:07 +00002117int page_check_range(target_ulong start, target_ulong len, int flags)
2118{
2119 PageDesc *p;
2120 target_ulong end;
2121 target_ulong addr;
2122
balrog55f280c2008-10-28 10:24:11 +00002123 if (start + len < start)
2124 /* we've wrapped around */
2125 return -1;
2126
ths3d97b402007-11-02 19:02:07 +00002127 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2128 start = start & TARGET_PAGE_MASK;
2129
ths3d97b402007-11-02 19:02:07 +00002130 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2131 p = page_find(addr >> TARGET_PAGE_BITS);
2132 if( !p )
2133 return -1;
2134 if( !(p->flags & PAGE_VALID) )
2135 return -1;
2136
bellarddae32702007-11-14 10:51:00 +00002137 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
ths3d97b402007-11-02 19:02:07 +00002138 return -1;
bellarddae32702007-11-14 10:51:00 +00002139 if (flags & PAGE_WRITE) {
2140 if (!(p->flags & PAGE_WRITE_ORG))
2141 return -1;
2142 /* unprotect the page if it was put read-only because it
2143 contains translated code */
2144 if (!(p->flags & PAGE_WRITE)) {
2145 if (!page_unprotect(addr, 0, NULL))
2146 return -1;
2147 }
2148 return 0;
2149 }
ths3d97b402007-11-02 19:02:07 +00002150 }
2151 return 0;
2152}
2153
bellard9fa3e852004-01-04 18:06:42 +00002154/* called from signal handler: invalidate the code and unprotect the
2155 page. Return TRUE if the fault was succesfully handled. */
pbrook53a59602006-03-25 19:31:22 +00002156int page_unprotect(target_ulong address, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00002157{
2158 unsigned int page_index, prot, pindex;
2159 PageDesc *p, *p1;
pbrook53a59602006-03-25 19:31:22 +00002160 target_ulong host_start, host_end, addr;
bellard9fa3e852004-01-04 18:06:42 +00002161
pbrookc8a706f2008-06-02 16:16:42 +00002162 /* Technically this isn't safe inside a signal handler. However we
2163 know this only ever happens in a synchronous SEGV handler, so in
2164 practice it seems to be ok. */
2165 mmap_lock();
2166
bellard83fb7ad2004-07-05 21:25:26 +00002167 host_start = address & qemu_host_page_mask;
bellard9fa3e852004-01-04 18:06:42 +00002168 page_index = host_start >> TARGET_PAGE_BITS;
2169 p1 = page_find(page_index);
pbrookc8a706f2008-06-02 16:16:42 +00002170 if (!p1) {
2171 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002172 return 0;
pbrookc8a706f2008-06-02 16:16:42 +00002173 }
bellard83fb7ad2004-07-05 21:25:26 +00002174 host_end = host_start + qemu_host_page_size;
bellard9fa3e852004-01-04 18:06:42 +00002175 p = p1;
2176 prot = 0;
2177 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2178 prot |= p->flags;
2179 p++;
2180 }
2181 /* if the page was really writable, then we change its
2182 protection back to writable */
2183 if (prot & PAGE_WRITE_ORG) {
2184 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2185 if (!(p1[pindex].flags & PAGE_WRITE)) {
ths5fafdf22007-09-16 21:08:06 +00002186 mprotect((void *)g2h(host_start), qemu_host_page_size,
bellard9fa3e852004-01-04 18:06:42 +00002187 (prot & PAGE_BITS) | PAGE_WRITE);
2188 p1[pindex].flags |= PAGE_WRITE;
2189 /* and since the content will be modified, we must invalidate
2190 the corresponding translated code. */
bellardd720b932004-04-25 17:57:43 +00002191 tb_invalidate_phys_page(address, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00002192#ifdef DEBUG_TB_CHECK
2193 tb_invalidate_check(address);
2194#endif
pbrookc8a706f2008-06-02 16:16:42 +00002195 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002196 return 1;
2197 }
2198 }
pbrookc8a706f2008-06-02 16:16:42 +00002199 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002200 return 0;
2201}
2202
bellard6a00d602005-11-21 23:25:50 +00002203static inline void tlb_set_dirty(CPUState *env,
2204 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002205{
2206}
bellard9fa3e852004-01-04 18:06:42 +00002207#endif /* defined(CONFIG_USER_ONLY) */
2208
pbrooke2eef172008-06-08 01:09:01 +00002209#if !defined(CONFIG_USER_ONLY)
blueswir1db7b5422007-05-26 17:36:03 +00002210static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
aurel3200f82b82008-04-27 21:12:55 +00002211 ram_addr_t memory);
2212static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2213 ram_addr_t orig_memory);
blueswir1db7b5422007-05-26 17:36:03 +00002214#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2215 need_subpage) \
2216 do { \
2217 if (addr > start_addr) \
2218 start_addr2 = 0; \
2219 else { \
2220 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2221 if (start_addr2 > 0) \
2222 need_subpage = 1; \
2223 } \
2224 \
blueswir149e9fba2007-05-30 17:25:06 +00002225 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
blueswir1db7b5422007-05-26 17:36:03 +00002226 end_addr2 = TARGET_PAGE_SIZE - 1; \
2227 else { \
2228 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2229 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2230 need_subpage = 1; \
2231 } \
2232 } while (0)
2233
bellard33417e72003-08-10 21:47:01 +00002234/* register physical memory. 'size' must be a multiple of the target
2235 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
2236 io memory page */
ths5fafdf22007-09-16 21:08:06 +00002237void cpu_register_physical_memory(target_phys_addr_t start_addr,
aurel3200f82b82008-04-27 21:12:55 +00002238 ram_addr_t size,
2239 ram_addr_t phys_offset)
bellard33417e72003-08-10 21:47:01 +00002240{
bellard108c49b2005-07-24 12:55:09 +00002241 target_phys_addr_t addr, end_addr;
bellard92e873b2004-05-21 14:52:29 +00002242 PhysPageDesc *p;
bellard9d420372006-06-25 22:25:22 +00002243 CPUState *env;
aurel3200f82b82008-04-27 21:12:55 +00002244 ram_addr_t orig_size = size;
blueswir1db7b5422007-05-26 17:36:03 +00002245 void *subpage;
bellard33417e72003-08-10 21:47:01 +00002246
bellardda260242008-05-30 20:48:25 +00002247#ifdef USE_KQEMU
2248 /* XXX: should not depend on cpu context */
2249 env = first_cpu;
2250 if (env->kqemu_enabled) {
2251 kqemu_set_phys_mem(start_addr, size, phys_offset);
2252 }
2253#endif
aliguori7ba1e612008-11-05 16:04:33 +00002254 if (kvm_enabled())
2255 kvm_set_phys_mem(start_addr, size, phys_offset);
2256
bellard5fd386f2004-05-23 21:11:22 +00002257 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
blueswir149e9fba2007-05-30 17:25:06 +00002258 end_addr = start_addr + (target_phys_addr_t)size;
2259 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
blueswir1db7b5422007-05-26 17:36:03 +00002260 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2261 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
aurel3200f82b82008-04-27 21:12:55 +00002262 ram_addr_t orig_memory = p->phys_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002263 target_phys_addr_t start_addr2, end_addr2;
2264 int need_subpage = 0;
2265
2266 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2267 need_subpage);
blueswir14254fab2008-01-01 16:57:19 +00002268 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002269 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2270 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2271 &p->phys_offset, orig_memory);
2272 } else {
2273 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2274 >> IO_MEM_SHIFT];
2275 }
2276 subpage_register(subpage, start_addr2, end_addr2, phys_offset);
2277 } else {
2278 p->phys_offset = phys_offset;
2279 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2280 (phys_offset & IO_MEM_ROMD))
2281 phys_offset += TARGET_PAGE_SIZE;
2282 }
2283 } else {
2284 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2285 p->phys_offset = phys_offset;
2286 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2287 (phys_offset & IO_MEM_ROMD))
2288 phys_offset += TARGET_PAGE_SIZE;
2289 else {
2290 target_phys_addr_t start_addr2, end_addr2;
2291 int need_subpage = 0;
2292
2293 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2294 end_addr2, need_subpage);
2295
blueswir14254fab2008-01-01 16:57:19 +00002296 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002297 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2298 &p->phys_offset, IO_MEM_UNASSIGNED);
2299 subpage_register(subpage, start_addr2, end_addr2,
2300 phys_offset);
2301 }
2302 }
2303 }
bellard33417e72003-08-10 21:47:01 +00002304 }
ths3b46e622007-09-17 08:09:54 +00002305
bellard9d420372006-06-25 22:25:22 +00002306 /* since each CPU stores ram addresses in its TLB cache, we must
2307 reset the modified entries */
2308 /* XXX: slow ! */
2309 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2310 tlb_flush(env, 1);
2311 }
bellard33417e72003-08-10 21:47:01 +00002312}
2313
bellardba863452006-09-24 18:41:10 +00002314/* XXX: temporary until new memory mapping API */
aurel3200f82b82008-04-27 21:12:55 +00002315ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
bellardba863452006-09-24 18:41:10 +00002316{
2317 PhysPageDesc *p;
2318
2319 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2320 if (!p)
2321 return IO_MEM_UNASSIGNED;
2322 return p->phys_offset;
2323}
2324
bellarde9a1ab12007-02-08 23:08:38 +00002325/* XXX: better than nothing */
aurel3200f82b82008-04-27 21:12:55 +00002326ram_addr_t qemu_ram_alloc(ram_addr_t size)
bellarde9a1ab12007-02-08 23:08:38 +00002327{
2328 ram_addr_t addr;
balrog7fb4fdc2008-04-24 17:59:27 +00002329 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
ths012a7042008-10-02 17:34:21 +00002330 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
bellarded441462008-05-23 11:56:45 +00002331 (uint64_t)size, (uint64_t)phys_ram_size);
bellarde9a1ab12007-02-08 23:08:38 +00002332 abort();
2333 }
2334 addr = phys_ram_alloc_offset;
2335 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2336 return addr;
2337}
2338
2339void qemu_ram_free(ram_addr_t addr)
2340{
2341}
2342
bellarda4193c82004-06-03 14:01:43 +00002343static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
bellard33417e72003-08-10 21:47:01 +00002344{
pbrook67d3b952006-12-18 05:03:52 +00002345#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002346 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
pbrook67d3b952006-12-18 05:03:52 +00002347#endif
blueswir1e18231a2008-10-06 18:46:28 +00002348#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2349 do_unassigned_access(addr, 0, 0, 0, 1);
2350#endif
2351 return 0;
2352}
2353
2354static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2355{
2356#ifdef DEBUG_UNASSIGNED
2357 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2358#endif
2359#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2360 do_unassigned_access(addr, 0, 0, 0, 2);
2361#endif
2362 return 0;
2363}
2364
2365static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2366{
2367#ifdef DEBUG_UNASSIGNED
2368 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2369#endif
2370#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2371 do_unassigned_access(addr, 0, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002372#endif
bellard33417e72003-08-10 21:47:01 +00002373 return 0;
2374}
2375
bellarda4193c82004-06-03 14:01:43 +00002376static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard33417e72003-08-10 21:47:01 +00002377{
pbrook67d3b952006-12-18 05:03:52 +00002378#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002379 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
pbrook67d3b952006-12-18 05:03:52 +00002380#endif
blueswir1e18231a2008-10-06 18:46:28 +00002381#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2382 do_unassigned_access(addr, 1, 0, 0, 1);
2383#endif
2384}
2385
2386static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2387{
2388#ifdef DEBUG_UNASSIGNED
2389 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2390#endif
2391#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2392 do_unassigned_access(addr, 1, 0, 0, 2);
2393#endif
2394}
2395
2396static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2397{
2398#ifdef DEBUG_UNASSIGNED
2399 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2400#endif
2401#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
2402 do_unassigned_access(addr, 1, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002403#endif
bellard33417e72003-08-10 21:47:01 +00002404}
2405
2406static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2407 unassigned_mem_readb,
blueswir1e18231a2008-10-06 18:46:28 +00002408 unassigned_mem_readw,
2409 unassigned_mem_readl,
bellard33417e72003-08-10 21:47:01 +00002410};
2411
2412static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2413 unassigned_mem_writeb,
blueswir1e18231a2008-10-06 18:46:28 +00002414 unassigned_mem_writew,
2415 unassigned_mem_writel,
bellard33417e72003-08-10 21:47:01 +00002416};
2417
pbrook0f459d12008-06-09 00:20:13 +00002418static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2419 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002420{
bellard3a7d9292005-08-21 09:26:42 +00002421 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002422 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2423 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2424#if !defined(CONFIG_USER_ONLY)
2425 tb_invalidate_phys_page_fast(ram_addr, 1);
2426 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2427#endif
2428 }
pbrook0f459d12008-06-09 00:20:13 +00002429 stb_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002430#ifdef USE_KQEMU
2431 if (cpu_single_env->kqemu_enabled &&
2432 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2433 kqemu_modify_page(cpu_single_env, ram_addr);
2434#endif
bellardf23db162005-08-21 19:12:28 +00002435 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2436 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2437 /* we remove the notdirty callback only if the code has been
2438 flushed */
2439 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002440 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002441}
2442
pbrook0f459d12008-06-09 00:20:13 +00002443static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2444 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002445{
bellard3a7d9292005-08-21 09:26:42 +00002446 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002447 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2448 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2449#if !defined(CONFIG_USER_ONLY)
2450 tb_invalidate_phys_page_fast(ram_addr, 2);
2451 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2452#endif
2453 }
pbrook0f459d12008-06-09 00:20:13 +00002454 stw_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002455#ifdef USE_KQEMU
2456 if (cpu_single_env->kqemu_enabled &&
2457 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2458 kqemu_modify_page(cpu_single_env, ram_addr);
2459#endif
bellardf23db162005-08-21 19:12:28 +00002460 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2461 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2462 /* we remove the notdirty callback only if the code has been
2463 flushed */
2464 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002465 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002466}
2467
pbrook0f459d12008-06-09 00:20:13 +00002468static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2469 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002470{
bellard3a7d9292005-08-21 09:26:42 +00002471 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002472 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2473 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2474#if !defined(CONFIG_USER_ONLY)
2475 tb_invalidate_phys_page_fast(ram_addr, 4);
2476 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2477#endif
2478 }
pbrook0f459d12008-06-09 00:20:13 +00002479 stl_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002480#ifdef USE_KQEMU
2481 if (cpu_single_env->kqemu_enabled &&
2482 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2483 kqemu_modify_page(cpu_single_env, ram_addr);
2484#endif
bellardf23db162005-08-21 19:12:28 +00002485 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2486 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2487 /* we remove the notdirty callback only if the code has been
2488 flushed */
2489 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002490 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002491}
2492
bellard3a7d9292005-08-21 09:26:42 +00002493static CPUReadMemoryFunc *error_mem_read[3] = {
2494 NULL, /* never used */
2495 NULL, /* never used */
2496 NULL, /* never used */
2497};
2498
bellard1ccde1c2004-02-06 19:46:14 +00002499static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2500 notdirty_mem_writeb,
2501 notdirty_mem_writew,
2502 notdirty_mem_writel,
2503};
2504
pbrook0f459d12008-06-09 00:20:13 +00002505/* Generate a debug exception if a watchpoint has been hit. */
aliguorib4051332008-11-18 20:14:20 +00002506static void check_watchpoint(int offset, int len_mask, int flags)
pbrook0f459d12008-06-09 00:20:13 +00002507{
2508 CPUState *env = cpu_single_env;
aliguori06d55cc2008-11-18 20:24:06 +00002509 target_ulong pc, cs_base;
2510 TranslationBlock *tb;
pbrook0f459d12008-06-09 00:20:13 +00002511 target_ulong vaddr;
aliguoria1d1bb32008-11-18 20:07:32 +00002512 CPUWatchpoint *wp;
aliguori06d55cc2008-11-18 20:24:06 +00002513 int cpu_flags;
pbrook0f459d12008-06-09 00:20:13 +00002514
aliguori06d55cc2008-11-18 20:24:06 +00002515 if (env->watchpoint_hit) {
2516 /* We re-entered the check after replacing the TB. Now raise
2517 * the debug interrupt so that is will trigger after the
2518 * current instruction. */
2519 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2520 return;
2521 }
pbrook2e70f6e2008-06-29 01:03:05 +00002522 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
aliguoria1d1bb32008-11-18 20:07:32 +00002523 for (wp = env->watchpoints; wp != NULL; wp = wp->next) {
aliguorib4051332008-11-18 20:14:20 +00002524 if ((vaddr == (wp->vaddr & len_mask) ||
2525 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
aliguoria1d1bb32008-11-18 20:07:32 +00002526 env->watchpoint_hit = wp;
aliguori06d55cc2008-11-18 20:24:06 +00002527 tb = tb_find_pc(env->mem_io_pc);
2528 if (!tb) {
2529 cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
2530 (void *)env->mem_io_pc);
2531 }
2532 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
2533 tb_phys_invalidate(tb, -1);
2534 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2535 env->exception_index = EXCP_DEBUG;
2536 } else {
2537 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2538 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
2539 }
2540 cpu_resume_from_signal(env, NULL);
pbrook0f459d12008-06-09 00:20:13 +00002541 }
2542 }
2543}
2544
pbrook6658ffb2007-03-16 23:58:11 +00002545/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2546 so these check for a hit then pass through to the normal out-of-line
2547 phys routines. */
2548static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2549{
aliguorib4051332008-11-18 20:14:20 +00002550 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002551 return ldub_phys(addr);
2552}
2553
2554static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2555{
aliguorib4051332008-11-18 20:14:20 +00002556 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002557 return lduw_phys(addr);
2558}
2559
2560static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2561{
aliguorib4051332008-11-18 20:14:20 +00002562 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002563 return ldl_phys(addr);
2564}
2565
pbrook6658ffb2007-03-16 23:58:11 +00002566static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2567 uint32_t val)
2568{
aliguorib4051332008-11-18 20:14:20 +00002569 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002570 stb_phys(addr, val);
2571}
2572
2573static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2574 uint32_t val)
2575{
aliguorib4051332008-11-18 20:14:20 +00002576 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002577 stw_phys(addr, val);
2578}
2579
2580static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2581 uint32_t val)
2582{
aliguorib4051332008-11-18 20:14:20 +00002583 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002584 stl_phys(addr, val);
2585}
2586
2587static CPUReadMemoryFunc *watch_mem_read[3] = {
2588 watch_mem_readb,
2589 watch_mem_readw,
2590 watch_mem_readl,
2591};
2592
2593static CPUWriteMemoryFunc *watch_mem_write[3] = {
2594 watch_mem_writeb,
2595 watch_mem_writew,
2596 watch_mem_writel,
2597};
pbrook6658ffb2007-03-16 23:58:11 +00002598
blueswir1db7b5422007-05-26 17:36:03 +00002599static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2600 unsigned int len)
2601{
blueswir1db7b5422007-05-26 17:36:03 +00002602 uint32_t ret;
2603 unsigned int idx;
2604
2605 idx = SUBPAGE_IDX(addr - mmio->base);
2606#if defined(DEBUG_SUBPAGE)
2607 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2608 mmio, len, addr, idx);
2609#endif
blueswir13ee89922008-01-02 19:45:26 +00002610 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
blueswir1db7b5422007-05-26 17:36:03 +00002611
2612 return ret;
2613}
2614
2615static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2616 uint32_t value, unsigned int len)
2617{
blueswir1db7b5422007-05-26 17:36:03 +00002618 unsigned int idx;
2619
2620 idx = SUBPAGE_IDX(addr - mmio->base);
2621#if defined(DEBUG_SUBPAGE)
2622 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2623 mmio, len, addr, idx, value);
2624#endif
blueswir13ee89922008-01-02 19:45:26 +00002625 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
blueswir1db7b5422007-05-26 17:36:03 +00002626}
2627
2628static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2629{
2630#if defined(DEBUG_SUBPAGE)
2631 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2632#endif
2633
2634 return subpage_readlen(opaque, addr, 0);
2635}
2636
2637static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2638 uint32_t value)
2639{
2640#if defined(DEBUG_SUBPAGE)
2641 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2642#endif
2643 subpage_writelen(opaque, addr, value, 0);
2644}
2645
2646static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2647{
2648#if defined(DEBUG_SUBPAGE)
2649 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2650#endif
2651
2652 return subpage_readlen(opaque, addr, 1);
2653}
2654
2655static void subpage_writew (void *opaque, target_phys_addr_t addr,
2656 uint32_t value)
2657{
2658#if defined(DEBUG_SUBPAGE)
2659 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2660#endif
2661 subpage_writelen(opaque, addr, value, 1);
2662}
2663
2664static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2665{
2666#if defined(DEBUG_SUBPAGE)
2667 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2668#endif
2669
2670 return subpage_readlen(opaque, addr, 2);
2671}
2672
2673static void subpage_writel (void *opaque,
2674 target_phys_addr_t addr, uint32_t value)
2675{
2676#if defined(DEBUG_SUBPAGE)
2677 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2678#endif
2679 subpage_writelen(opaque, addr, value, 2);
2680}
2681
2682static CPUReadMemoryFunc *subpage_read[] = {
2683 &subpage_readb,
2684 &subpage_readw,
2685 &subpage_readl,
2686};
2687
2688static CPUWriteMemoryFunc *subpage_write[] = {
2689 &subpage_writeb,
2690 &subpage_writew,
2691 &subpage_writel,
2692};
2693
2694static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
aurel3200f82b82008-04-27 21:12:55 +00002695 ram_addr_t memory)
blueswir1db7b5422007-05-26 17:36:03 +00002696{
2697 int idx, eidx;
blueswir14254fab2008-01-01 16:57:19 +00002698 unsigned int i;
blueswir1db7b5422007-05-26 17:36:03 +00002699
2700 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2701 return -1;
2702 idx = SUBPAGE_IDX(start);
2703 eidx = SUBPAGE_IDX(end);
2704#if defined(DEBUG_SUBPAGE)
2705 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2706 mmio, start, end, idx, eidx, memory);
2707#endif
2708 memory >>= IO_MEM_SHIFT;
2709 for (; idx <= eidx; idx++) {
blueswir14254fab2008-01-01 16:57:19 +00002710 for (i = 0; i < 4; i++) {
blueswir13ee89922008-01-02 19:45:26 +00002711 if (io_mem_read[memory][i]) {
2712 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2713 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
2714 }
2715 if (io_mem_write[memory][i]) {
2716 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2717 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
2718 }
blueswir14254fab2008-01-01 16:57:19 +00002719 }
blueswir1db7b5422007-05-26 17:36:03 +00002720 }
2721
2722 return 0;
2723}
2724
aurel3200f82b82008-04-27 21:12:55 +00002725static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2726 ram_addr_t orig_memory)
blueswir1db7b5422007-05-26 17:36:03 +00002727{
2728 subpage_t *mmio;
2729 int subpage_memory;
2730
2731 mmio = qemu_mallocz(sizeof(subpage_t));
2732 if (mmio != NULL) {
2733 mmio->base = base;
2734 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
2735#if defined(DEBUG_SUBPAGE)
2736 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2737 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
2738#endif
2739 *phys = subpage_memory | IO_MEM_SUBPAGE;
2740 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
2741 }
2742
2743 return mmio;
2744}
2745
bellard33417e72003-08-10 21:47:01 +00002746static void io_mem_init(void)
2747{
bellard3a7d9292005-08-21 09:26:42 +00002748 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
bellarda4193c82004-06-03 14:01:43 +00002749 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
bellard3a7d9292005-08-21 09:26:42 +00002750 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002751 io_mem_nb = 5;
2752
pbrook0f459d12008-06-09 00:20:13 +00002753 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
pbrook6658ffb2007-03-16 23:58:11 +00002754 watch_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002755 /* alloc dirty bits array */
bellard0a962c02005-02-10 22:00:27 +00002756 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
bellard3a7d9292005-08-21 09:26:42 +00002757 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002758}
2759
2760/* mem_read and mem_write are arrays of functions containing the
2761 function to access byte (index 0), word (index 1) and dword (index
blueswir13ee89922008-01-02 19:45:26 +00002762 2). Functions can be omitted with a NULL function pointer. The
2763 registered functions may be modified dynamically later.
2764 If io_index is non zero, the corresponding io zone is
blueswir14254fab2008-01-01 16:57:19 +00002765 modified. If it is zero, a new io zone is allocated. The return
2766 value can be used with cpu_register_physical_memory(). (-1) is
2767 returned if error. */
bellard33417e72003-08-10 21:47:01 +00002768int cpu_register_io_memory(int io_index,
2769 CPUReadMemoryFunc **mem_read,
bellarda4193c82004-06-03 14:01:43 +00002770 CPUWriteMemoryFunc **mem_write,
2771 void *opaque)
bellard33417e72003-08-10 21:47:01 +00002772{
blueswir14254fab2008-01-01 16:57:19 +00002773 int i, subwidth = 0;
bellard33417e72003-08-10 21:47:01 +00002774
2775 if (io_index <= 0) {
bellardb5ff1b32005-11-26 10:38:39 +00002776 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
bellard33417e72003-08-10 21:47:01 +00002777 return -1;
2778 io_index = io_mem_nb++;
2779 } else {
2780 if (io_index >= IO_MEM_NB_ENTRIES)
2781 return -1;
2782 }
bellardb5ff1b32005-11-26 10:38:39 +00002783
bellard33417e72003-08-10 21:47:01 +00002784 for(i = 0;i < 3; i++) {
blueswir14254fab2008-01-01 16:57:19 +00002785 if (!mem_read[i] || !mem_write[i])
2786 subwidth = IO_MEM_SUBWIDTH;
bellard33417e72003-08-10 21:47:01 +00002787 io_mem_read[io_index][i] = mem_read[i];
2788 io_mem_write[io_index][i] = mem_write[i];
2789 }
bellarda4193c82004-06-03 14:01:43 +00002790 io_mem_opaque[io_index] = opaque;
blueswir14254fab2008-01-01 16:57:19 +00002791 return (io_index << IO_MEM_SHIFT) | subwidth;
bellard33417e72003-08-10 21:47:01 +00002792}
bellard61382a52003-10-27 21:22:23 +00002793
bellard8926b512004-10-10 15:14:20 +00002794CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2795{
2796 return io_mem_write[io_index >> IO_MEM_SHIFT];
2797}
2798
2799CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2800{
2801 return io_mem_read[io_index >> IO_MEM_SHIFT];
2802}
2803
pbrooke2eef172008-06-08 01:09:01 +00002804#endif /* !defined(CONFIG_USER_ONLY) */
2805
bellard13eb76e2004-01-24 15:23:36 +00002806/* physical memory access (slow version, mainly for debug) */
2807#if defined(CONFIG_USER_ONLY)
ths5fafdf22007-09-16 21:08:06 +00002808void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002809 int len, int is_write)
2810{
2811 int l, flags;
2812 target_ulong page;
pbrook53a59602006-03-25 19:31:22 +00002813 void * p;
bellard13eb76e2004-01-24 15:23:36 +00002814
2815 while (len > 0) {
2816 page = addr & TARGET_PAGE_MASK;
2817 l = (page + TARGET_PAGE_SIZE) - addr;
2818 if (l > len)
2819 l = len;
2820 flags = page_get_flags(page);
2821 if (!(flags & PAGE_VALID))
2822 return;
2823 if (is_write) {
2824 if (!(flags & PAGE_WRITE))
2825 return;
bellard579a97f2007-11-11 14:26:47 +00002826 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002827 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
bellard579a97f2007-11-11 14:26:47 +00002828 /* FIXME - should this return an error rather than just fail? */
2829 return;
aurel3272fb7da2008-04-27 23:53:45 +00002830 memcpy(p, buf, l);
2831 unlock_user(p, addr, l);
bellard13eb76e2004-01-24 15:23:36 +00002832 } else {
2833 if (!(flags & PAGE_READ))
2834 return;
bellard579a97f2007-11-11 14:26:47 +00002835 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002836 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
bellard579a97f2007-11-11 14:26:47 +00002837 /* FIXME - should this return an error rather than just fail? */
2838 return;
aurel3272fb7da2008-04-27 23:53:45 +00002839 memcpy(buf, p, l);
aurel325b257572008-04-28 08:54:59 +00002840 unlock_user(p, addr, 0);
bellard13eb76e2004-01-24 15:23:36 +00002841 }
2842 len -= l;
2843 buf += l;
2844 addr += l;
2845 }
2846}
bellard8df1cd02005-01-28 22:37:22 +00002847
bellard13eb76e2004-01-24 15:23:36 +00002848#else
ths5fafdf22007-09-16 21:08:06 +00002849void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002850 int len, int is_write)
2851{
2852 int l, io_index;
2853 uint8_t *ptr;
2854 uint32_t val;
bellard2e126692004-04-25 21:28:44 +00002855 target_phys_addr_t page;
2856 unsigned long pd;
bellard92e873b2004-05-21 14:52:29 +00002857 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002858
bellard13eb76e2004-01-24 15:23:36 +00002859 while (len > 0) {
2860 page = addr & TARGET_PAGE_MASK;
2861 l = (page + TARGET_PAGE_SIZE) - addr;
2862 if (l > len)
2863 l = len;
bellard92e873b2004-05-21 14:52:29 +00002864 p = phys_page_find(page >> TARGET_PAGE_BITS);
bellard13eb76e2004-01-24 15:23:36 +00002865 if (!p) {
2866 pd = IO_MEM_UNASSIGNED;
2867 } else {
2868 pd = p->phys_offset;
2869 }
ths3b46e622007-09-17 08:09:54 +00002870
bellard13eb76e2004-01-24 15:23:36 +00002871 if (is_write) {
bellard3a7d9292005-08-21 09:26:42 +00002872 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard13eb76e2004-01-24 15:23:36 +00002873 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
bellard6a00d602005-11-21 23:25:50 +00002874 /* XXX: could force cpu_single_env to NULL to avoid
2875 potential bugs */
bellard13eb76e2004-01-24 15:23:36 +00002876 if (l >= 4 && ((addr & 3) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002877 /* 32 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002878 val = ldl_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002879 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002880 l = 4;
2881 } else if (l >= 2 && ((addr & 1) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002882 /* 16 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002883 val = lduw_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002884 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002885 l = 2;
2886 } else {
bellard1c213d12005-09-03 10:49:04 +00002887 /* 8 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002888 val = ldub_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002889 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002890 l = 1;
2891 }
2892 } else {
bellardb448f2f2004-02-25 23:24:04 +00002893 unsigned long addr1;
2894 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
bellard13eb76e2004-01-24 15:23:36 +00002895 /* RAM case */
bellardb448f2f2004-02-25 23:24:04 +00002896 ptr = phys_ram_base + addr1;
bellard13eb76e2004-01-24 15:23:36 +00002897 memcpy(ptr, buf, l);
bellard3a7d9292005-08-21 09:26:42 +00002898 if (!cpu_physical_memory_is_dirty(addr1)) {
2899 /* invalidate code */
2900 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
2901 /* set dirty bit */
ths5fafdf22007-09-16 21:08:06 +00002902 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
bellardf23db162005-08-21 19:12:28 +00002903 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00002904 }
bellard13eb76e2004-01-24 15:23:36 +00002905 }
2906 } else {
ths5fafdf22007-09-16 21:08:06 +00002907 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00002908 !(pd & IO_MEM_ROMD)) {
bellard13eb76e2004-01-24 15:23:36 +00002909 /* I/O case */
2910 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2911 if (l >= 4 && ((addr & 3) == 0)) {
2912 /* 32 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002913 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002914 stl_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002915 l = 4;
2916 } else if (l >= 2 && ((addr & 1) == 0)) {
2917 /* 16 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002918 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002919 stw_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002920 l = 2;
2921 } else {
bellard1c213d12005-09-03 10:49:04 +00002922 /* 8 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002923 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002924 stb_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002925 l = 1;
2926 }
2927 } else {
2928 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00002929 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard13eb76e2004-01-24 15:23:36 +00002930 (addr & ~TARGET_PAGE_MASK);
2931 memcpy(buf, ptr, l);
2932 }
2933 }
2934 len -= l;
2935 buf += l;
2936 addr += l;
2937 }
2938}
bellard8df1cd02005-01-28 22:37:22 +00002939
bellardd0ecd2a2006-04-23 17:14:48 +00002940/* used for ROM loading : can write in RAM and ROM */
ths5fafdf22007-09-16 21:08:06 +00002941void cpu_physical_memory_write_rom(target_phys_addr_t addr,
bellardd0ecd2a2006-04-23 17:14:48 +00002942 const uint8_t *buf, int len)
2943{
2944 int l;
2945 uint8_t *ptr;
2946 target_phys_addr_t page;
2947 unsigned long pd;
2948 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002949
bellardd0ecd2a2006-04-23 17:14:48 +00002950 while (len > 0) {
2951 page = addr & TARGET_PAGE_MASK;
2952 l = (page + TARGET_PAGE_SIZE) - addr;
2953 if (l > len)
2954 l = len;
2955 p = phys_page_find(page >> TARGET_PAGE_BITS);
2956 if (!p) {
2957 pd = IO_MEM_UNASSIGNED;
2958 } else {
2959 pd = p->phys_offset;
2960 }
ths3b46e622007-09-17 08:09:54 +00002961
bellardd0ecd2a2006-04-23 17:14:48 +00002962 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
bellard2a4188a2006-06-25 21:54:59 +00002963 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
2964 !(pd & IO_MEM_ROMD)) {
bellardd0ecd2a2006-04-23 17:14:48 +00002965 /* do nothing */
2966 } else {
2967 unsigned long addr1;
2968 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
2969 /* ROM/RAM case */
2970 ptr = phys_ram_base + addr1;
2971 memcpy(ptr, buf, l);
2972 }
2973 len -= l;
2974 buf += l;
2975 addr += l;
2976 }
2977}
2978
2979
bellard8df1cd02005-01-28 22:37:22 +00002980/* warning: addr must be aligned */
2981uint32_t ldl_phys(target_phys_addr_t addr)
2982{
2983 int io_index;
2984 uint8_t *ptr;
2985 uint32_t val;
2986 unsigned long pd;
2987 PhysPageDesc *p;
2988
2989 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2990 if (!p) {
2991 pd = IO_MEM_UNASSIGNED;
2992 } else {
2993 pd = p->phys_offset;
2994 }
ths3b46e622007-09-17 08:09:54 +00002995
ths5fafdf22007-09-16 21:08:06 +00002996 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00002997 !(pd & IO_MEM_ROMD)) {
bellard8df1cd02005-01-28 22:37:22 +00002998 /* I/O case */
2999 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3000 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3001 } else {
3002 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003003 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00003004 (addr & ~TARGET_PAGE_MASK);
3005 val = ldl_p(ptr);
3006 }
3007 return val;
3008}
3009
bellard84b7b8e2005-11-28 21:19:04 +00003010/* warning: addr must be aligned */
3011uint64_t ldq_phys(target_phys_addr_t addr)
3012{
3013 int io_index;
3014 uint8_t *ptr;
3015 uint64_t val;
3016 unsigned long pd;
3017 PhysPageDesc *p;
3018
3019 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3020 if (!p) {
3021 pd = IO_MEM_UNASSIGNED;
3022 } else {
3023 pd = p->phys_offset;
3024 }
ths3b46e622007-09-17 08:09:54 +00003025
bellard2a4188a2006-06-25 21:54:59 +00003026 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3027 !(pd & IO_MEM_ROMD)) {
bellard84b7b8e2005-11-28 21:19:04 +00003028 /* I/O case */
3029 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3030#ifdef TARGET_WORDS_BIGENDIAN
3031 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3032 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3033#else
3034 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3035 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3036#endif
3037 } else {
3038 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003039 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard84b7b8e2005-11-28 21:19:04 +00003040 (addr & ~TARGET_PAGE_MASK);
3041 val = ldq_p(ptr);
3042 }
3043 return val;
3044}
3045
bellardaab33092005-10-30 20:48:42 +00003046/* XXX: optimize */
3047uint32_t ldub_phys(target_phys_addr_t addr)
3048{
3049 uint8_t val;
3050 cpu_physical_memory_read(addr, &val, 1);
3051 return val;
3052}
3053
3054/* XXX: optimize */
3055uint32_t lduw_phys(target_phys_addr_t addr)
3056{
3057 uint16_t val;
3058 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3059 return tswap16(val);
3060}
3061
bellard8df1cd02005-01-28 22:37:22 +00003062/* warning: addr must be aligned. The ram page is not masked as dirty
3063 and the code inside is not invalidated. It is useful if the dirty
3064 bits are used to track modified PTEs */
3065void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3066{
3067 int io_index;
3068 uint8_t *ptr;
3069 unsigned long pd;
3070 PhysPageDesc *p;
3071
3072 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3073 if (!p) {
3074 pd = IO_MEM_UNASSIGNED;
3075 } else {
3076 pd = p->phys_offset;
3077 }
ths3b46e622007-09-17 08:09:54 +00003078
bellard3a7d9292005-08-21 09:26:42 +00003079 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003080 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3081 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3082 } else {
aliguori74576192008-10-06 14:02:03 +00003083 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3084 ptr = phys_ram_base + addr1;
bellard8df1cd02005-01-28 22:37:22 +00003085 stl_p(ptr, val);
aliguori74576192008-10-06 14:02:03 +00003086
3087 if (unlikely(in_migration)) {
3088 if (!cpu_physical_memory_is_dirty(addr1)) {
3089 /* invalidate code */
3090 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3091 /* set dirty bit */
3092 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3093 (0xff & ~CODE_DIRTY_FLAG);
3094 }
3095 }
bellard8df1cd02005-01-28 22:37:22 +00003096 }
3097}
3098
j_mayerbc98a7e2007-04-04 07:55:12 +00003099void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3100{
3101 int io_index;
3102 uint8_t *ptr;
3103 unsigned long pd;
3104 PhysPageDesc *p;
3105
3106 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3107 if (!p) {
3108 pd = IO_MEM_UNASSIGNED;
3109 } else {
3110 pd = p->phys_offset;
3111 }
ths3b46e622007-09-17 08:09:54 +00003112
j_mayerbc98a7e2007-04-04 07:55:12 +00003113 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3114 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3115#ifdef TARGET_WORDS_BIGENDIAN
3116 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3117 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3118#else
3119 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3120 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3121#endif
3122 } else {
ths5fafdf22007-09-16 21:08:06 +00003123 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
j_mayerbc98a7e2007-04-04 07:55:12 +00003124 (addr & ~TARGET_PAGE_MASK);
3125 stq_p(ptr, val);
3126 }
3127}
3128
bellard8df1cd02005-01-28 22:37:22 +00003129/* warning: addr must be aligned */
bellard8df1cd02005-01-28 22:37:22 +00003130void stl_phys(target_phys_addr_t addr, uint32_t val)
3131{
3132 int io_index;
3133 uint8_t *ptr;
3134 unsigned long pd;
3135 PhysPageDesc *p;
3136
3137 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3138 if (!p) {
3139 pd = IO_MEM_UNASSIGNED;
3140 } else {
3141 pd = p->phys_offset;
3142 }
ths3b46e622007-09-17 08:09:54 +00003143
bellard3a7d9292005-08-21 09:26:42 +00003144 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003145 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3146 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3147 } else {
3148 unsigned long addr1;
3149 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3150 /* RAM case */
3151 ptr = phys_ram_base + addr1;
3152 stl_p(ptr, val);
bellard3a7d9292005-08-21 09:26:42 +00003153 if (!cpu_physical_memory_is_dirty(addr1)) {
3154 /* invalidate code */
3155 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3156 /* set dirty bit */
bellardf23db162005-08-21 19:12:28 +00003157 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3158 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00003159 }
bellard8df1cd02005-01-28 22:37:22 +00003160 }
3161}
3162
bellardaab33092005-10-30 20:48:42 +00003163/* XXX: optimize */
3164void stb_phys(target_phys_addr_t addr, uint32_t val)
3165{
3166 uint8_t v = val;
3167 cpu_physical_memory_write(addr, &v, 1);
3168}
3169
3170/* XXX: optimize */
3171void stw_phys(target_phys_addr_t addr, uint32_t val)
3172{
3173 uint16_t v = tswap16(val);
3174 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3175}
3176
3177/* XXX: optimize */
3178void stq_phys(target_phys_addr_t addr, uint64_t val)
3179{
3180 val = tswap64(val);
3181 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3182}
3183
bellard13eb76e2004-01-24 15:23:36 +00003184#endif
3185
3186/* virtual memory access for debug */
ths5fafdf22007-09-16 21:08:06 +00003187int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
bellardb448f2f2004-02-25 23:24:04 +00003188 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00003189{
3190 int l;
j_mayer9b3c35e2007-04-07 11:21:28 +00003191 target_phys_addr_t phys_addr;
3192 target_ulong page;
bellard13eb76e2004-01-24 15:23:36 +00003193
3194 while (len > 0) {
3195 page = addr & TARGET_PAGE_MASK;
3196 phys_addr = cpu_get_phys_page_debug(env, page);
3197 /* if no physical page mapped, return an error */
3198 if (phys_addr == -1)
3199 return -1;
3200 l = (page + TARGET_PAGE_SIZE) - addr;
3201 if (l > len)
3202 l = len;
ths5fafdf22007-09-16 21:08:06 +00003203 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
bellardb448f2f2004-02-25 23:24:04 +00003204 buf, l, is_write);
bellard13eb76e2004-01-24 15:23:36 +00003205 len -= l;
3206 buf += l;
3207 addr += l;
3208 }
3209 return 0;
3210}
3211
pbrook2e70f6e2008-06-29 01:03:05 +00003212/* in deterministic execution mode, instructions doing device I/Os
3213 must be at the end of the TB */
3214void cpu_io_recompile(CPUState *env, void *retaddr)
3215{
3216 TranslationBlock *tb;
3217 uint32_t n, cflags;
3218 target_ulong pc, cs_base;
3219 uint64_t flags;
3220
3221 tb = tb_find_pc((unsigned long)retaddr);
3222 if (!tb) {
3223 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3224 retaddr);
3225 }
3226 n = env->icount_decr.u16.low + tb->icount;
3227 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3228 /* Calculate how many instructions had been executed before the fault
thsbf20dc02008-06-30 17:22:19 +00003229 occurred. */
pbrook2e70f6e2008-06-29 01:03:05 +00003230 n = n - env->icount_decr.u16.low;
3231 /* Generate a new TB ending on the I/O insn. */
3232 n++;
3233 /* On MIPS and SH, delay slot instructions can only be restarted if
3234 they were already the first instruction in the TB. If this is not
thsbf20dc02008-06-30 17:22:19 +00003235 the first instruction in a TB then re-execute the preceding
pbrook2e70f6e2008-06-29 01:03:05 +00003236 branch. */
3237#if defined(TARGET_MIPS)
3238 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3239 env->active_tc.PC -= 4;
3240 env->icount_decr.u16.low++;
3241 env->hflags &= ~MIPS_HFLAG_BMASK;
3242 }
3243#elif defined(TARGET_SH4)
3244 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3245 && n > 1) {
3246 env->pc -= 2;
3247 env->icount_decr.u16.low++;
3248 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3249 }
3250#endif
3251 /* This should never happen. */
3252 if (n > CF_COUNT_MASK)
3253 cpu_abort(env, "TB too big during recompile");
3254
3255 cflags = n | CF_LAST_IO;
3256 pc = tb->pc;
3257 cs_base = tb->cs_base;
3258 flags = tb->flags;
3259 tb_phys_invalidate(tb, -1);
3260 /* FIXME: In theory this could raise an exception. In practice
3261 we have already translated the block once so it's probably ok. */
3262 tb_gen_code(env, pc, cs_base, flags, cflags);
thsbf20dc02008-06-30 17:22:19 +00003263 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
pbrook2e70f6e2008-06-29 01:03:05 +00003264 the first in the TB) then we end up generating a whole new TB and
3265 repeating the fault, which is horribly inefficient.
3266 Better would be to execute just this insn uncached, or generate a
3267 second new TB. */
3268 cpu_resume_from_signal(env, NULL);
3269}
3270
bellarde3db7222005-01-26 22:00:47 +00003271void dump_exec_info(FILE *f,
3272 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3273{
3274 int i, target_code_size, max_target_code_size;
3275 int direct_jmp_count, direct_jmp2_count, cross_page;
3276 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +00003277
bellarde3db7222005-01-26 22:00:47 +00003278 target_code_size = 0;
3279 max_target_code_size = 0;
3280 cross_page = 0;
3281 direct_jmp_count = 0;
3282 direct_jmp2_count = 0;
3283 for(i = 0; i < nb_tbs; i++) {
3284 tb = &tbs[i];
3285 target_code_size += tb->size;
3286 if (tb->size > max_target_code_size)
3287 max_target_code_size = tb->size;
3288 if (tb->page_addr[1] != -1)
3289 cross_page++;
3290 if (tb->tb_next_offset[0] != 0xffff) {
3291 direct_jmp_count++;
3292 if (tb->tb_next_offset[1] != 0xffff) {
3293 direct_jmp2_count++;
3294 }
3295 }
3296 }
3297 /* XXX: avoid using doubles ? */
bellard57fec1f2008-02-01 10:50:11 +00003298 cpu_fprintf(f, "Translation buffer state:\n");
bellard26a5f132008-05-28 12:30:31 +00003299 cpu_fprintf(f, "gen code size %ld/%ld\n",
3300 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3301 cpu_fprintf(f, "TB count %d/%d\n",
3302 nb_tbs, code_gen_max_blocks);
ths5fafdf22007-09-16 21:08:06 +00003303 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
bellarde3db7222005-01-26 22:00:47 +00003304 nb_tbs ? target_code_size / nb_tbs : 0,
3305 max_target_code_size);
ths5fafdf22007-09-16 21:08:06 +00003306 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
bellarde3db7222005-01-26 22:00:47 +00003307 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3308 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
ths5fafdf22007-09-16 21:08:06 +00003309 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3310 cross_page,
bellarde3db7222005-01-26 22:00:47 +00003311 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3312 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
ths5fafdf22007-09-16 21:08:06 +00003313 direct_jmp_count,
bellarde3db7222005-01-26 22:00:47 +00003314 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3315 direct_jmp2_count,
3316 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
bellard57fec1f2008-02-01 10:50:11 +00003317 cpu_fprintf(f, "\nStatistics:\n");
bellarde3db7222005-01-26 22:00:47 +00003318 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3319 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3320 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
bellardb67d9a52008-05-23 09:57:34 +00003321 tcg_dump_info(f, cpu_fprintf);
bellarde3db7222005-01-26 22:00:47 +00003322}
3323
ths5fafdf22007-09-16 21:08:06 +00003324#if !defined(CONFIG_USER_ONLY)
bellard61382a52003-10-27 21:22:23 +00003325
3326#define MMUSUFFIX _cmmu
3327#define GETPC() NULL
3328#define env cpu_single_env
bellardb769d8f2004-10-03 15:07:13 +00003329#define SOFTMMU_CODE_ACCESS
bellard61382a52003-10-27 21:22:23 +00003330
3331#define SHIFT 0
3332#include "softmmu_template.h"
3333
3334#define SHIFT 1
3335#include "softmmu_template.h"
3336
3337#define SHIFT 2
3338#include "softmmu_template.h"
3339
3340#define SHIFT 3
3341#include "softmmu_template.h"
3342
3343#undef env
3344
3345#endif