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bellard54936002003-05-13 00:25:15 +00001/*
bellardfd6ce8f2003-05-14 19:00:11 +00002 * virtual page mapping and translated block handling
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard54936002003-05-13 00:25:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
aurel32fad6cb12009-01-04 22:05:52 +000018 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
bellard54936002003-05-13 00:25:15 +000019 */
bellard67b915a2004-03-31 23:37:16 +000020#include "config.h"
bellardd5a8f072004-09-29 21:15:28 +000021#ifdef _WIN32
ths4fddf622007-12-17 04:42:29 +000022#define WIN32_LEAN_AND_MEAN
bellardd5a8f072004-09-29 21:15:28 +000023#include <windows.h>
24#else
bellarda98d49b2004-11-14 16:22:05 +000025#include <sys/types.h>
bellardd5a8f072004-09-29 21:15:28 +000026#include <sys/mman.h>
27#endif
bellard54936002003-05-13 00:25:15 +000028#include <stdlib.h>
29#include <stdio.h>
30#include <stdarg.h>
31#include <string.h>
32#include <errno.h>
33#include <unistd.h>
34#include <inttypes.h>
35
bellard6180a182003-09-30 21:04:53 +000036#include "cpu.h"
37#include "exec-all.h"
aurel32ca10f862008-04-11 21:35:42 +000038#include "qemu-common.h"
bellardb67d9a52008-05-23 09:57:34 +000039#include "tcg.h"
pbrookb3c77242008-06-30 16:31:04 +000040#include "hw/hw.h"
aliguori74576192008-10-06 14:02:03 +000041#include "osdep.h"
aliguori7ba1e612008-11-05 16:04:33 +000042#include "kvm.h"
pbrook53a59602006-03-25 19:31:22 +000043#if defined(CONFIG_USER_ONLY)
44#include <qemu.h>
45#endif
bellard54936002003-05-13 00:25:15 +000046
bellardfd6ce8f2003-05-14 19:00:11 +000047//#define DEBUG_TB_INVALIDATE
bellard66e85a22003-06-24 13:28:12 +000048//#define DEBUG_FLUSH
bellard9fa3e852004-01-04 18:06:42 +000049//#define DEBUG_TLB
pbrook67d3b952006-12-18 05:03:52 +000050//#define DEBUG_UNASSIGNED
bellardfd6ce8f2003-05-14 19:00:11 +000051
52/* make various TB consistency checks */
ths5fafdf22007-09-16 21:08:06 +000053//#define DEBUG_TB_CHECK
54//#define DEBUG_TLB_CHECK
bellardfd6ce8f2003-05-14 19:00:11 +000055
ths1196be32007-03-17 15:17:58 +000056//#define DEBUG_IOPORT
blueswir1db7b5422007-05-26 17:36:03 +000057//#define DEBUG_SUBPAGE
ths1196be32007-03-17 15:17:58 +000058
pbrook99773bd2006-04-16 15:14:59 +000059#if !defined(CONFIG_USER_ONLY)
60/* TB consistency checks only implemented for usermode emulation. */
61#undef DEBUG_TB_CHECK
62#endif
63
bellard9fa3e852004-01-04 18:06:42 +000064#define SMC_BITMAP_USE_THRESHOLD 10
65
66#define MMAP_AREA_START 0x00000000
67#define MMAP_AREA_END 0xa8000000
bellardfd6ce8f2003-05-14 19:00:11 +000068
bellard108c49b2005-07-24 12:55:09 +000069#if defined(TARGET_SPARC64)
70#define TARGET_PHYS_ADDR_SPACE_BITS 41
blueswir15dcb6b92007-05-19 12:58:30 +000071#elif defined(TARGET_SPARC)
72#define TARGET_PHYS_ADDR_SPACE_BITS 36
j_mayerbedb69e2007-04-05 20:08:21 +000073#elif defined(TARGET_ALPHA)
74#define TARGET_PHYS_ADDR_SPACE_BITS 42
75#define TARGET_VIRT_ADDR_SPACE_BITS 42
bellard108c49b2005-07-24 12:55:09 +000076#elif defined(TARGET_PPC64)
77#define TARGET_PHYS_ADDR_SPACE_BITS 42
aurel3200f82b82008-04-27 21:12:55 +000078#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
79#define TARGET_PHYS_ADDR_SPACE_BITS 42
80#elif defined(TARGET_I386) && !defined(USE_KQEMU)
81#define TARGET_PHYS_ADDR_SPACE_BITS 36
bellard108c49b2005-07-24 12:55:09 +000082#else
83/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
84#define TARGET_PHYS_ADDR_SPACE_BITS 32
85#endif
86
blueswir1bdaf78e2008-10-04 07:24:27 +000087static TranslationBlock *tbs;
bellard26a5f132008-05-28 12:30:31 +000088int code_gen_max_blocks;
bellard9fa3e852004-01-04 18:06:42 +000089TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +000090static int nb_tbs;
bellardeb51d102003-05-14 21:51:13 +000091/* any access to the tbs or the page table must use this lock */
92spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
bellardfd6ce8f2003-05-14 19:00:11 +000093
blueswir1141ac462008-07-26 15:05:57 +000094#if defined(__arm__) || defined(__sparc_v9__)
95/* The prologue must be reachable with a direct jump. ARM and Sparc64
96 have limited branch ranges (possibly also PPC) so place it in a
blueswir1d03d8602008-07-10 17:21:31 +000097 section close to code segment. */
98#define code_gen_section \
99 __attribute__((__section__(".gen_code"))) \
100 __attribute__((aligned (32)))
101#else
102#define code_gen_section \
103 __attribute__((aligned (32)))
104#endif
105
106uint8_t code_gen_prologue[1024] code_gen_section;
blueswir1bdaf78e2008-10-04 07:24:27 +0000107static uint8_t *code_gen_buffer;
108static unsigned long code_gen_buffer_size;
bellard26a5f132008-05-28 12:30:31 +0000109/* threshold to flush the translated code buffer */
blueswir1bdaf78e2008-10-04 07:24:27 +0000110static unsigned long code_gen_buffer_max_size;
bellardfd6ce8f2003-05-14 19:00:11 +0000111uint8_t *code_gen_ptr;
112
pbrooke2eef172008-06-08 01:09:01 +0000113#if !defined(CONFIG_USER_ONLY)
aurel3200f82b82008-04-27 21:12:55 +0000114ram_addr_t phys_ram_size;
bellard9fa3e852004-01-04 18:06:42 +0000115int phys_ram_fd;
116uint8_t *phys_ram_base;
bellard1ccde1c2004-02-06 19:46:14 +0000117uint8_t *phys_ram_dirty;
aliguori74576192008-10-06 14:02:03 +0000118static int in_migration;
bellarde9a1ab12007-02-08 23:08:38 +0000119static ram_addr_t phys_ram_alloc_offset = 0;
pbrooke2eef172008-06-08 01:09:01 +0000120#endif
bellard9fa3e852004-01-04 18:06:42 +0000121
bellard6a00d602005-11-21 23:25:50 +0000122CPUState *first_cpu;
123/* current CPU in the current thread. It is only valid inside
124 cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000125CPUState *cpu_single_env;
pbrook2e70f6e2008-06-29 01:03:05 +0000126/* 0 = Do not count executed instructions.
thsbf20dc02008-06-30 17:22:19 +0000127 1 = Precise instruction counting.
pbrook2e70f6e2008-06-29 01:03:05 +0000128 2 = Adaptive rate instruction counting. */
129int use_icount = 0;
130/* Current instruction counter. While executing translated code this may
131 include some instructions that have not yet been executed. */
132int64_t qemu_icount;
bellard6a00d602005-11-21 23:25:50 +0000133
bellard54936002003-05-13 00:25:15 +0000134typedef struct PageDesc {
bellard92e873b2004-05-21 14:52:29 +0000135 /* list of TBs intersecting this ram page */
bellardfd6ce8f2003-05-14 19:00:11 +0000136 TranslationBlock *first_tb;
bellard9fa3e852004-01-04 18:06:42 +0000137 /* in order to optimize self modifying code, we count the number
138 of lookups we do to a given page to use a bitmap */
139 unsigned int code_write_count;
140 uint8_t *code_bitmap;
141#if defined(CONFIG_USER_ONLY)
142 unsigned long flags;
143#endif
bellard54936002003-05-13 00:25:15 +0000144} PageDesc;
145
bellard92e873b2004-05-21 14:52:29 +0000146typedef struct PhysPageDesc {
pbrook0f459d12008-06-09 00:20:13 +0000147 /* offset in host memory of the page + io_index in the low bits */
aurel3200f82b82008-04-27 21:12:55 +0000148 ram_addr_t phys_offset;
pbrook8da3ff12008-12-01 18:59:50 +0000149 ram_addr_t region_offset;
bellard92e873b2004-05-21 14:52:29 +0000150} PhysPageDesc;
151
bellard54936002003-05-13 00:25:15 +0000152#define L2_BITS 10
j_mayerbedb69e2007-04-05 20:08:21 +0000153#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
154/* XXX: this is a temporary hack for alpha target.
155 * In the future, this is to be replaced by a multi-level table
156 * to actually be able to handle the complete 64 bits address space.
157 */
158#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
159#else
aurel3203875442008-04-22 20:45:18 +0000160#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
j_mayerbedb69e2007-04-05 20:08:21 +0000161#endif
bellard54936002003-05-13 00:25:15 +0000162
163#define L1_SIZE (1 << L1_BITS)
164#define L2_SIZE (1 << L2_BITS)
165
bellard83fb7ad2004-07-05 21:25:26 +0000166unsigned long qemu_real_host_page_size;
167unsigned long qemu_host_page_bits;
168unsigned long qemu_host_page_size;
169unsigned long qemu_host_page_mask;
bellard54936002003-05-13 00:25:15 +0000170
bellard92e873b2004-05-21 14:52:29 +0000171/* XXX: for system emulation, it could just be an array */
bellard54936002003-05-13 00:25:15 +0000172static PageDesc *l1_map[L1_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +0000173static PhysPageDesc **l1_phys_map;
bellard54936002003-05-13 00:25:15 +0000174
pbrooke2eef172008-06-08 01:09:01 +0000175#if !defined(CONFIG_USER_ONLY)
176static void io_mem_init(void);
177
bellard33417e72003-08-10 21:47:01 +0000178/* io memory support */
bellard33417e72003-08-10 21:47:01 +0000179CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
180CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000181void *io_mem_opaque[IO_MEM_NB_ENTRIES];
bellard33417e72003-08-10 21:47:01 +0000182static int io_mem_nb;
pbrook6658ffb2007-03-16 23:58:11 +0000183static int io_mem_watch;
184#endif
bellard33417e72003-08-10 21:47:01 +0000185
bellard34865132003-10-05 14:28:56 +0000186/* log support */
blueswir1d9b630f2008-10-05 09:57:08 +0000187static const char *logfilename = "/tmp/qemu.log";
bellard34865132003-10-05 14:28:56 +0000188FILE *logfile;
189int loglevel;
pbrooke735b912007-06-30 13:53:24 +0000190static int log_append = 0;
bellard34865132003-10-05 14:28:56 +0000191
bellarde3db7222005-01-26 22:00:47 +0000192/* statistics */
193static int tlb_flush_count;
194static int tb_flush_count;
195static int tb_phys_invalidate_count;
196
blueswir1db7b5422007-05-26 17:36:03 +0000197#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
198typedef struct subpage_t {
199 target_phys_addr_t base;
blueswir13ee89922008-01-02 19:45:26 +0000200 CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
201 CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
202 void *opaque[TARGET_PAGE_SIZE][2][4];
pbrook8da3ff12008-12-01 18:59:50 +0000203 ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
blueswir1db7b5422007-05-26 17:36:03 +0000204} subpage_t;
205
bellard7cb69ca2008-05-10 10:55:51 +0000206#ifdef _WIN32
207static void map_exec(void *addr, long size)
208{
209 DWORD old_protect;
210 VirtualProtect(addr, size,
211 PAGE_EXECUTE_READWRITE, &old_protect);
212
213}
214#else
215static void map_exec(void *addr, long size)
216{
bellard43694152008-05-29 09:35:57 +0000217 unsigned long start, end, page_size;
bellard7cb69ca2008-05-10 10:55:51 +0000218
bellard43694152008-05-29 09:35:57 +0000219 page_size = getpagesize();
bellard7cb69ca2008-05-10 10:55:51 +0000220 start = (unsigned long)addr;
bellard43694152008-05-29 09:35:57 +0000221 start &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000222
223 end = (unsigned long)addr + size;
bellard43694152008-05-29 09:35:57 +0000224 end += page_size - 1;
225 end &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000226
227 mprotect((void *)start, end - start,
228 PROT_READ | PROT_WRITE | PROT_EXEC);
229}
230#endif
231
bellardb346ff42003-06-15 20:05:50 +0000232static void page_init(void)
bellard54936002003-05-13 00:25:15 +0000233{
bellard83fb7ad2004-07-05 21:25:26 +0000234 /* NOTE: we can always suppose that qemu_host_page_size >=
bellard54936002003-05-13 00:25:15 +0000235 TARGET_PAGE_SIZE */
aliguoric2b48b62008-11-11 22:06:42 +0000236#ifdef _WIN32
237 {
238 SYSTEM_INFO system_info;
239
240 GetSystemInfo(&system_info);
241 qemu_real_host_page_size = system_info.dwPageSize;
242 }
243#else
244 qemu_real_host_page_size = getpagesize();
245#endif
bellard83fb7ad2004-07-05 21:25:26 +0000246 if (qemu_host_page_size == 0)
247 qemu_host_page_size = qemu_real_host_page_size;
248 if (qemu_host_page_size < TARGET_PAGE_SIZE)
249 qemu_host_page_size = TARGET_PAGE_SIZE;
250 qemu_host_page_bits = 0;
251 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
252 qemu_host_page_bits++;
253 qemu_host_page_mask = ~(qemu_host_page_size - 1);
bellard108c49b2005-07-24 12:55:09 +0000254 l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
255 memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
balrog50a95692007-12-12 01:16:23 +0000256
257#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
258 {
259 long long startaddr, endaddr;
260 FILE *f;
261 int n;
262
pbrookc8a706f2008-06-02 16:16:42 +0000263 mmap_lock();
pbrook07765902008-05-31 16:33:53 +0000264 last_brk = (unsigned long)sbrk(0);
balrog50a95692007-12-12 01:16:23 +0000265 f = fopen("/proc/self/maps", "r");
266 if (f) {
267 do {
268 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
269 if (n == 2) {
blueswir1e0b8d652008-05-03 17:51:24 +0000270 startaddr = MIN(startaddr,
271 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
272 endaddr = MIN(endaddr,
273 (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
pbrookb5fc9092008-05-29 13:56:10 +0000274 page_set_flags(startaddr & TARGET_PAGE_MASK,
balrog50a95692007-12-12 01:16:23 +0000275 TARGET_PAGE_ALIGN(endaddr),
276 PAGE_RESERVED);
277 }
278 } while (!feof(f));
279 fclose(f);
280 }
pbrookc8a706f2008-06-02 16:16:42 +0000281 mmap_unlock();
balrog50a95692007-12-12 01:16:23 +0000282 }
283#endif
bellard54936002003-05-13 00:25:15 +0000284}
285
aliguori434929b2008-09-15 15:56:30 +0000286static inline PageDesc **page_l1_map(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000287{
pbrook17e23772008-06-09 13:47:45 +0000288#if TARGET_LONG_BITS > 32
289 /* Host memory outside guest VM. For 32-bit targets we have already
290 excluded high addresses. */
thsd8173e02008-08-29 13:10:00 +0000291 if (index > ((target_ulong)L2_SIZE * L1_SIZE))
pbrook17e23772008-06-09 13:47:45 +0000292 return NULL;
293#endif
aliguori434929b2008-09-15 15:56:30 +0000294 return &l1_map[index >> L2_BITS];
295}
296
297static inline PageDesc *page_find_alloc(target_ulong index)
298{
299 PageDesc **lp, *p;
300 lp = page_l1_map(index);
301 if (!lp)
302 return NULL;
303
bellard54936002003-05-13 00:25:15 +0000304 p = *lp;
305 if (!p) {
306 /* allocate if not found */
pbrook17e23772008-06-09 13:47:45 +0000307#if defined(CONFIG_USER_ONLY)
pbrook17e23772008-06-09 13:47:45 +0000308 size_t len = sizeof(PageDesc) * L2_SIZE;
309 /* Don't use qemu_malloc because it may recurse. */
310 p = mmap(0, len, PROT_READ | PROT_WRITE,
311 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
bellard54936002003-05-13 00:25:15 +0000312 *lp = p;
aurel32fb1c2cd2008-12-08 18:12:26 +0000313 if (h2g_valid(p)) {
314 unsigned long addr = h2g(p);
pbrook17e23772008-06-09 13:47:45 +0000315 page_set_flags(addr & TARGET_PAGE_MASK,
316 TARGET_PAGE_ALIGN(addr + len),
317 PAGE_RESERVED);
318 }
319#else
320 p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
321 *lp = p;
322#endif
bellard54936002003-05-13 00:25:15 +0000323 }
324 return p + (index & (L2_SIZE - 1));
325}
326
aurel3200f82b82008-04-27 21:12:55 +0000327static inline PageDesc *page_find(target_ulong index)
bellard54936002003-05-13 00:25:15 +0000328{
aliguori434929b2008-09-15 15:56:30 +0000329 PageDesc **lp, *p;
330 lp = page_l1_map(index);
331 if (!lp)
332 return NULL;
bellard54936002003-05-13 00:25:15 +0000333
aliguori434929b2008-09-15 15:56:30 +0000334 p = *lp;
bellard54936002003-05-13 00:25:15 +0000335 if (!p)
336 return 0;
bellardfd6ce8f2003-05-14 19:00:11 +0000337 return p + (index & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000338}
339
bellard108c49b2005-07-24 12:55:09 +0000340static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
bellard92e873b2004-05-21 14:52:29 +0000341{
bellard108c49b2005-07-24 12:55:09 +0000342 void **lp, **p;
pbrooke3f4e2a2006-04-08 20:02:06 +0000343 PhysPageDesc *pd;
bellard92e873b2004-05-21 14:52:29 +0000344
bellard108c49b2005-07-24 12:55:09 +0000345 p = (void **)l1_phys_map;
346#if TARGET_PHYS_ADDR_SPACE_BITS > 32
347
348#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
349#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
350#endif
351 lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000352 p = *lp;
353 if (!p) {
354 /* allocate if not found */
bellard108c49b2005-07-24 12:55:09 +0000355 if (!alloc)
356 return NULL;
357 p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
358 memset(p, 0, sizeof(void *) * L1_SIZE);
359 *lp = p;
360 }
361#endif
362 lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
pbrooke3f4e2a2006-04-08 20:02:06 +0000363 pd = *lp;
364 if (!pd) {
365 int i;
bellard108c49b2005-07-24 12:55:09 +0000366 /* allocate if not found */
367 if (!alloc)
368 return NULL;
pbrooke3f4e2a2006-04-08 20:02:06 +0000369 pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
370 *lp = pd;
371 for (i = 0; i < L2_SIZE; i++)
372 pd[i].phys_offset = IO_MEM_UNASSIGNED;
bellard92e873b2004-05-21 14:52:29 +0000373 }
pbrooke3f4e2a2006-04-08 20:02:06 +0000374 return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000375}
376
bellard108c49b2005-07-24 12:55:09 +0000377static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
bellard92e873b2004-05-21 14:52:29 +0000378{
bellard108c49b2005-07-24 12:55:09 +0000379 return phys_page_find_alloc(index, 0);
bellard92e873b2004-05-21 14:52:29 +0000380}
381
bellard9fa3e852004-01-04 18:06:42 +0000382#if !defined(CONFIG_USER_ONLY)
bellard6a00d602005-11-21 23:25:50 +0000383static void tlb_protect_code(ram_addr_t ram_addr);
ths5fafdf22007-09-16 21:08:06 +0000384static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +0000385 target_ulong vaddr);
pbrookc8a706f2008-06-02 16:16:42 +0000386#define mmap_lock() do { } while(0)
387#define mmap_unlock() do { } while(0)
bellard9fa3e852004-01-04 18:06:42 +0000388#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000389
bellard43694152008-05-29 09:35:57 +0000390#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
391
392#if defined(CONFIG_USER_ONLY)
393/* Currently it is not recommanded to allocate big chunks of data in
394 user mode. It will change when a dedicated libc will be used */
395#define USE_STATIC_CODE_GEN_BUFFER
396#endif
397
398#ifdef USE_STATIC_CODE_GEN_BUFFER
399static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
400#endif
401
blueswir18fcd3692008-08-17 20:26:25 +0000402static void code_gen_alloc(unsigned long tb_size)
bellard26a5f132008-05-28 12:30:31 +0000403{
bellard43694152008-05-29 09:35:57 +0000404#ifdef USE_STATIC_CODE_GEN_BUFFER
405 code_gen_buffer = static_code_gen_buffer;
406 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
407 map_exec(code_gen_buffer, code_gen_buffer_size);
408#else
bellard26a5f132008-05-28 12:30:31 +0000409 code_gen_buffer_size = tb_size;
410 if (code_gen_buffer_size == 0) {
bellard43694152008-05-29 09:35:57 +0000411#if defined(CONFIG_USER_ONLY)
412 /* in user mode, phys_ram_size is not meaningful */
413 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
414#else
bellard26a5f132008-05-28 12:30:31 +0000415 /* XXX: needs ajustments */
aliguori174a9a12008-09-24 14:10:36 +0000416 code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
bellard43694152008-05-29 09:35:57 +0000417#endif
bellard26a5f132008-05-28 12:30:31 +0000418 }
419 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
420 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
421 /* The code gen buffer location may have constraints depending on
422 the host cpu and OS */
423#if defined(__linux__)
424 {
425 int flags;
blueswir1141ac462008-07-26 15:05:57 +0000426 void *start = NULL;
427
bellard26a5f132008-05-28 12:30:31 +0000428 flags = MAP_PRIVATE | MAP_ANONYMOUS;
429#if defined(__x86_64__)
430 flags |= MAP_32BIT;
431 /* Cannot map more than that */
432 if (code_gen_buffer_size > (800 * 1024 * 1024))
433 code_gen_buffer_size = (800 * 1024 * 1024);
blueswir1141ac462008-07-26 15:05:57 +0000434#elif defined(__sparc_v9__)
435 // Map the buffer below 2G, so we can use direct calls and branches
436 flags |= MAP_FIXED;
437 start = (void *) 0x60000000UL;
438 if (code_gen_buffer_size > (512 * 1024 * 1024))
439 code_gen_buffer_size = (512 * 1024 * 1024);
balrog1cb06612008-12-01 02:10:17 +0000440#elif defined(__arm__)
balrog63d41242008-12-01 02:19:41 +0000441 /* Map the buffer below 32M, so we can use direct calls and branches */
balrog1cb06612008-12-01 02:10:17 +0000442 flags |= MAP_FIXED;
443 start = (void *) 0x01000000UL;
444 if (code_gen_buffer_size > 16 * 1024 * 1024)
445 code_gen_buffer_size = 16 * 1024 * 1024;
bellard26a5f132008-05-28 12:30:31 +0000446#endif
blueswir1141ac462008-07-26 15:05:57 +0000447 code_gen_buffer = mmap(start, code_gen_buffer_size,
448 PROT_WRITE | PROT_READ | PROT_EXEC,
bellard26a5f132008-05-28 12:30:31 +0000449 flags, -1, 0);
450 if (code_gen_buffer == MAP_FAILED) {
451 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
452 exit(1);
453 }
454 }
aliguori06e67a82008-09-27 15:32:41 +0000455#elif defined(__FreeBSD__)
456 {
457 int flags;
458 void *addr = NULL;
459 flags = MAP_PRIVATE | MAP_ANONYMOUS;
460#if defined(__x86_64__)
461 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
462 * 0x40000000 is free */
463 flags |= MAP_FIXED;
464 addr = (void *)0x40000000;
465 /* Cannot map more than that */
466 if (code_gen_buffer_size > (800 * 1024 * 1024))
467 code_gen_buffer_size = (800 * 1024 * 1024);
468#endif
469 code_gen_buffer = mmap(addr, code_gen_buffer_size,
470 PROT_WRITE | PROT_READ | PROT_EXEC,
471 flags, -1, 0);
472 if (code_gen_buffer == MAP_FAILED) {
473 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
474 exit(1);
475 }
476 }
bellard26a5f132008-05-28 12:30:31 +0000477#else
478 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
479 if (!code_gen_buffer) {
480 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
481 exit(1);
482 }
483 map_exec(code_gen_buffer, code_gen_buffer_size);
484#endif
bellard43694152008-05-29 09:35:57 +0000485#endif /* !USE_STATIC_CODE_GEN_BUFFER */
bellard26a5f132008-05-28 12:30:31 +0000486 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
487 code_gen_buffer_max_size = code_gen_buffer_size -
488 code_gen_max_block_size();
489 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
490 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
491}
492
493/* Must be called before using the QEMU cpus. 'tb_size' is the size
494 (in bytes) allocated to the translation buffer. Zero means default
495 size. */
496void cpu_exec_init_all(unsigned long tb_size)
497{
bellard26a5f132008-05-28 12:30:31 +0000498 cpu_gen_init();
499 code_gen_alloc(tb_size);
500 code_gen_ptr = code_gen_buffer;
bellard43694152008-05-29 09:35:57 +0000501 page_init();
pbrooke2eef172008-06-08 01:09:01 +0000502#if !defined(CONFIG_USER_ONLY)
bellard26a5f132008-05-28 12:30:31 +0000503 io_mem_init();
pbrooke2eef172008-06-08 01:09:01 +0000504#endif
bellard26a5f132008-05-28 12:30:31 +0000505}
506
pbrook9656f322008-07-01 20:01:19 +0000507#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
508
509#define CPU_COMMON_SAVE_VERSION 1
510
511static void cpu_common_save(QEMUFile *f, void *opaque)
512{
513 CPUState *env = opaque;
514
515 qemu_put_be32s(f, &env->halted);
516 qemu_put_be32s(f, &env->interrupt_request);
517}
518
519static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
520{
521 CPUState *env = opaque;
522
523 if (version_id != CPU_COMMON_SAVE_VERSION)
524 return -EINVAL;
525
526 qemu_get_be32s(f, &env->halted);
pbrook75f482a2008-07-01 21:53:33 +0000527 qemu_get_be32s(f, &env->interrupt_request);
pbrook9656f322008-07-01 20:01:19 +0000528 tlb_flush(env, 1);
529
530 return 0;
531}
532#endif
533
bellard6a00d602005-11-21 23:25:50 +0000534void cpu_exec_init(CPUState *env)
bellardfd6ce8f2003-05-14 19:00:11 +0000535{
bellard6a00d602005-11-21 23:25:50 +0000536 CPUState **penv;
537 int cpu_index;
538
bellard6a00d602005-11-21 23:25:50 +0000539 env->next_cpu = NULL;
540 penv = &first_cpu;
541 cpu_index = 0;
542 while (*penv != NULL) {
543 penv = (CPUState **)&(*penv)->next_cpu;
544 cpu_index++;
545 }
546 env->cpu_index = cpu_index;
aliguoric0ce9982008-11-25 22:13:57 +0000547 TAILQ_INIT(&env->breakpoints);
548 TAILQ_INIT(&env->watchpoints);
bellard6a00d602005-11-21 23:25:50 +0000549 *penv = env;
pbrookb3c77242008-06-30 16:31:04 +0000550#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
pbrook9656f322008-07-01 20:01:19 +0000551 register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
552 cpu_common_save, cpu_common_load, env);
pbrookb3c77242008-06-30 16:31:04 +0000553 register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
554 cpu_save, cpu_load, env);
555#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000556}
557
bellard9fa3e852004-01-04 18:06:42 +0000558static inline void invalidate_page_bitmap(PageDesc *p)
559{
560 if (p->code_bitmap) {
bellard59817cc2004-02-16 22:01:13 +0000561 qemu_free(p->code_bitmap);
bellard9fa3e852004-01-04 18:06:42 +0000562 p->code_bitmap = NULL;
563 }
564 p->code_write_count = 0;
565}
566
bellardfd6ce8f2003-05-14 19:00:11 +0000567/* set to NULL all the 'first_tb' fields in all PageDescs */
568static void page_flush_tb(void)
569{
570 int i, j;
571 PageDesc *p;
572
573 for(i = 0; i < L1_SIZE; i++) {
574 p = l1_map[i];
575 if (p) {
bellard9fa3e852004-01-04 18:06:42 +0000576 for(j = 0; j < L2_SIZE; j++) {
577 p->first_tb = NULL;
578 invalidate_page_bitmap(p);
579 p++;
580 }
bellardfd6ce8f2003-05-14 19:00:11 +0000581 }
582 }
583}
584
585/* flush all the translation blocks */
bellardd4e81642003-05-25 16:46:15 +0000586/* XXX: tb_flush is currently not thread safe */
bellard6a00d602005-11-21 23:25:50 +0000587void tb_flush(CPUState *env1)
bellardfd6ce8f2003-05-14 19:00:11 +0000588{
bellard6a00d602005-11-21 23:25:50 +0000589 CPUState *env;
bellard01243112004-01-04 15:48:17 +0000590#if defined(DEBUG_FLUSH)
blueswir1ab3d1722007-11-04 07:31:40 +0000591 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
592 (unsigned long)(code_gen_ptr - code_gen_buffer),
593 nb_tbs, nb_tbs > 0 ?
594 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
bellardfd6ce8f2003-05-14 19:00:11 +0000595#endif
bellard26a5f132008-05-28 12:30:31 +0000596 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
pbrooka208e542008-03-31 17:07:36 +0000597 cpu_abort(env1, "Internal error: code buffer overflow\n");
598
bellardfd6ce8f2003-05-14 19:00:11 +0000599 nb_tbs = 0;
ths3b46e622007-09-17 08:09:54 +0000600
bellard6a00d602005-11-21 23:25:50 +0000601 for(env = first_cpu; env != NULL; env = env->next_cpu) {
602 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
603 }
bellard9fa3e852004-01-04 18:06:42 +0000604
bellard8a8a6082004-10-03 13:36:49 +0000605 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
bellardfd6ce8f2003-05-14 19:00:11 +0000606 page_flush_tb();
bellard9fa3e852004-01-04 18:06:42 +0000607
bellardfd6ce8f2003-05-14 19:00:11 +0000608 code_gen_ptr = code_gen_buffer;
bellardd4e81642003-05-25 16:46:15 +0000609 /* XXX: flush processor icache at this point if cache flush is
610 expensive */
bellarde3db7222005-01-26 22:00:47 +0000611 tb_flush_count++;
bellardfd6ce8f2003-05-14 19:00:11 +0000612}
613
614#ifdef DEBUG_TB_CHECK
615
j_mayerbc98a7e2007-04-04 07:55:12 +0000616static void tb_invalidate_check(target_ulong address)
bellardfd6ce8f2003-05-14 19:00:11 +0000617{
618 TranslationBlock *tb;
619 int i;
620 address &= TARGET_PAGE_MASK;
pbrook99773bd2006-04-16 15:14:59 +0000621 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
622 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000623 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
624 address >= tb->pc + tb->size)) {
625 printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
pbrook99773bd2006-04-16 15:14:59 +0000626 address, (long)tb->pc, tb->size);
bellardfd6ce8f2003-05-14 19:00:11 +0000627 }
628 }
629 }
630}
631
632/* verify that all the pages have correct rights for code */
633static void tb_page_check(void)
634{
635 TranslationBlock *tb;
636 int i, flags1, flags2;
ths3b46e622007-09-17 08:09:54 +0000637
pbrook99773bd2006-04-16 15:14:59 +0000638 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
639 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000640 flags1 = page_get_flags(tb->pc);
641 flags2 = page_get_flags(tb->pc + tb->size - 1);
642 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
643 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
pbrook99773bd2006-04-16 15:14:59 +0000644 (long)tb->pc, tb->size, flags1, flags2);
bellardfd6ce8f2003-05-14 19:00:11 +0000645 }
646 }
647 }
648}
649
blueswir1bdaf78e2008-10-04 07:24:27 +0000650static void tb_jmp_check(TranslationBlock *tb)
bellardd4e81642003-05-25 16:46:15 +0000651{
652 TranslationBlock *tb1;
653 unsigned int n1;
654
655 /* suppress any remaining jumps to this TB */
656 tb1 = tb->jmp_first;
657 for(;;) {
658 n1 = (long)tb1 & 3;
659 tb1 = (TranslationBlock *)((long)tb1 & ~3);
660 if (n1 == 2)
661 break;
662 tb1 = tb1->jmp_next[n1];
663 }
664 /* check end of list */
665 if (tb1 != tb) {
666 printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
667 }
668}
669
bellardfd6ce8f2003-05-14 19:00:11 +0000670#endif
671
672/* invalidate one TB */
673static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
674 int next_offset)
675{
676 TranslationBlock *tb1;
677 for(;;) {
678 tb1 = *ptb;
679 if (tb1 == tb) {
680 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
681 break;
682 }
683 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
684 }
685}
686
bellard9fa3e852004-01-04 18:06:42 +0000687static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
688{
689 TranslationBlock *tb1;
690 unsigned int n1;
691
692 for(;;) {
693 tb1 = *ptb;
694 n1 = (long)tb1 & 3;
695 tb1 = (TranslationBlock *)((long)tb1 & ~3);
696 if (tb1 == tb) {
697 *ptb = tb1->page_next[n1];
698 break;
699 }
700 ptb = &tb1->page_next[n1];
701 }
702}
703
bellardd4e81642003-05-25 16:46:15 +0000704static inline void tb_jmp_remove(TranslationBlock *tb, int n)
705{
706 TranslationBlock *tb1, **ptb;
707 unsigned int n1;
708
709 ptb = &tb->jmp_next[n];
710 tb1 = *ptb;
711 if (tb1) {
712 /* find tb(n) in circular list */
713 for(;;) {
714 tb1 = *ptb;
715 n1 = (long)tb1 & 3;
716 tb1 = (TranslationBlock *)((long)tb1 & ~3);
717 if (n1 == n && tb1 == tb)
718 break;
719 if (n1 == 2) {
720 ptb = &tb1->jmp_first;
721 } else {
722 ptb = &tb1->jmp_next[n1];
723 }
724 }
725 /* now we can suppress tb(n) from the list */
726 *ptb = tb->jmp_next[n];
727
728 tb->jmp_next[n] = NULL;
729 }
730}
731
732/* reset the jump entry 'n' of a TB so that it is not chained to
733 another TB */
734static inline void tb_reset_jump(TranslationBlock *tb, int n)
735{
736 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
737}
738
pbrook2e70f6e2008-06-29 01:03:05 +0000739void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000740{
bellard6a00d602005-11-21 23:25:50 +0000741 CPUState *env;
bellardfd6ce8f2003-05-14 19:00:11 +0000742 PageDesc *p;
bellard8a40a182005-11-20 10:35:40 +0000743 unsigned int h, n1;
aurel3200f82b82008-04-27 21:12:55 +0000744 target_phys_addr_t phys_pc;
bellard8a40a182005-11-20 10:35:40 +0000745 TranslationBlock *tb1, *tb2;
ths3b46e622007-09-17 08:09:54 +0000746
bellard9fa3e852004-01-04 18:06:42 +0000747 /* remove the TB from the hash list */
748 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
749 h = tb_phys_hash_func(phys_pc);
ths5fafdf22007-09-16 21:08:06 +0000750 tb_remove(&tb_phys_hash[h], tb,
bellard9fa3e852004-01-04 18:06:42 +0000751 offsetof(TranslationBlock, phys_hash_next));
bellardfd6ce8f2003-05-14 19:00:11 +0000752
bellard9fa3e852004-01-04 18:06:42 +0000753 /* remove the TB from the page list */
754 if (tb->page_addr[0] != page_addr) {
755 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
756 tb_page_remove(&p->first_tb, tb);
757 invalidate_page_bitmap(p);
758 }
759 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
760 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
761 tb_page_remove(&p->first_tb, tb);
762 invalidate_page_bitmap(p);
763 }
764
bellard8a40a182005-11-20 10:35:40 +0000765 tb_invalidated_flag = 1;
766
767 /* remove the TB from the hash list */
768 h = tb_jmp_cache_hash_func(tb->pc);
bellard6a00d602005-11-21 23:25:50 +0000769 for(env = first_cpu; env != NULL; env = env->next_cpu) {
770 if (env->tb_jmp_cache[h] == tb)
771 env->tb_jmp_cache[h] = NULL;
772 }
bellard8a40a182005-11-20 10:35:40 +0000773
774 /* suppress this TB from the two jump lists */
775 tb_jmp_remove(tb, 0);
776 tb_jmp_remove(tb, 1);
777
778 /* suppress any remaining jumps to this TB */
779 tb1 = tb->jmp_first;
780 for(;;) {
781 n1 = (long)tb1 & 3;
782 if (n1 == 2)
783 break;
784 tb1 = (TranslationBlock *)((long)tb1 & ~3);
785 tb2 = tb1->jmp_next[n1];
786 tb_reset_jump(tb1, n1);
787 tb1->jmp_next[n1] = NULL;
788 tb1 = tb2;
789 }
790 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
791
bellarde3db7222005-01-26 22:00:47 +0000792 tb_phys_invalidate_count++;
bellard9fa3e852004-01-04 18:06:42 +0000793}
794
795static inline void set_bits(uint8_t *tab, int start, int len)
796{
797 int end, mask, end1;
798
799 end = start + len;
800 tab += start >> 3;
801 mask = 0xff << (start & 7);
802 if ((start & ~7) == (end & ~7)) {
803 if (start < end) {
804 mask &= ~(0xff << (end & 7));
805 *tab |= mask;
806 }
807 } else {
808 *tab++ |= mask;
809 start = (start + 8) & ~7;
810 end1 = end & ~7;
811 while (start < end1) {
812 *tab++ = 0xff;
813 start += 8;
814 }
815 if (start < end) {
816 mask = ~(0xff << (end & 7));
817 *tab |= mask;
818 }
819 }
820}
821
822static void build_page_bitmap(PageDesc *p)
823{
824 int n, tb_start, tb_end;
825 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +0000826
pbrookb2a70812008-06-09 13:57:23 +0000827 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
bellard9fa3e852004-01-04 18:06:42 +0000828 if (!p->code_bitmap)
829 return;
bellard9fa3e852004-01-04 18:06:42 +0000830
831 tb = p->first_tb;
832 while (tb != NULL) {
833 n = (long)tb & 3;
834 tb = (TranslationBlock *)((long)tb & ~3);
835 /* NOTE: this is subtle as a TB may span two physical pages */
836 if (n == 0) {
837 /* NOTE: tb_end may be after the end of the page, but
838 it is not a problem */
839 tb_start = tb->pc & ~TARGET_PAGE_MASK;
840 tb_end = tb_start + tb->size;
841 if (tb_end > TARGET_PAGE_SIZE)
842 tb_end = TARGET_PAGE_SIZE;
843 } else {
844 tb_start = 0;
845 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
846 }
847 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
848 tb = tb->page_next[n];
849 }
850}
851
pbrook2e70f6e2008-06-29 01:03:05 +0000852TranslationBlock *tb_gen_code(CPUState *env,
853 target_ulong pc, target_ulong cs_base,
854 int flags, int cflags)
bellardd720b932004-04-25 17:57:43 +0000855{
856 TranslationBlock *tb;
857 uint8_t *tc_ptr;
858 target_ulong phys_pc, phys_page2, virt_page2;
859 int code_gen_size;
860
bellardc27004e2005-01-03 23:35:10 +0000861 phys_pc = get_phys_addr_code(env, pc);
862 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000863 if (!tb) {
864 /* flush must be done */
865 tb_flush(env);
866 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000867 tb = tb_alloc(pc);
pbrook2e70f6e2008-06-29 01:03:05 +0000868 /* Don't forget to invalidate previous TB info. */
869 tb_invalidated_flag = 1;
bellardd720b932004-04-25 17:57:43 +0000870 }
871 tc_ptr = code_gen_ptr;
872 tb->tc_ptr = tc_ptr;
873 tb->cs_base = cs_base;
874 tb->flags = flags;
875 tb->cflags = cflags;
blueswir1d07bde82007-12-11 19:35:45 +0000876 cpu_gen_code(env, tb, &code_gen_size);
bellardd720b932004-04-25 17:57:43 +0000877 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000878
bellardd720b932004-04-25 17:57:43 +0000879 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000880 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellardd720b932004-04-25 17:57:43 +0000881 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000882 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
bellardd720b932004-04-25 17:57:43 +0000883 phys_page2 = get_phys_addr_code(env, virt_page2);
884 }
885 tb_link_phys(tb, phys_pc, phys_page2);
pbrook2e70f6e2008-06-29 01:03:05 +0000886 return tb;
bellardd720b932004-04-25 17:57:43 +0000887}
ths3b46e622007-09-17 08:09:54 +0000888
bellard9fa3e852004-01-04 18:06:42 +0000889/* invalidate all TBs which intersect with the target physical page
890 starting in range [start;end[. NOTE: start and end must refer to
bellardd720b932004-04-25 17:57:43 +0000891 the same physical page. 'is_cpu_write_access' should be true if called
892 from a real cpu write access: the virtual CPU will exit the current
893 TB if code is modified inside this TB. */
aurel3200f82b82008-04-27 21:12:55 +0000894void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
bellardd720b932004-04-25 17:57:43 +0000895 int is_cpu_write_access)
bellard9fa3e852004-01-04 18:06:42 +0000896{
aliguori6b917542008-11-18 19:46:41 +0000897 TranslationBlock *tb, *tb_next, *saved_tb;
bellardd720b932004-04-25 17:57:43 +0000898 CPUState *env = cpu_single_env;
bellard9fa3e852004-01-04 18:06:42 +0000899 target_ulong tb_start, tb_end;
aliguori6b917542008-11-18 19:46:41 +0000900 PageDesc *p;
901 int n;
902#ifdef TARGET_HAS_PRECISE_SMC
903 int current_tb_not_found = is_cpu_write_access;
904 TranslationBlock *current_tb = NULL;
905 int current_tb_modified = 0;
906 target_ulong current_pc = 0;
907 target_ulong current_cs_base = 0;
908 int current_flags = 0;
909#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +0000910
911 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000912 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000913 return;
ths5fafdf22007-09-16 21:08:06 +0000914 if (!p->code_bitmap &&
bellardd720b932004-04-25 17:57:43 +0000915 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
916 is_cpu_write_access) {
bellard9fa3e852004-01-04 18:06:42 +0000917 /* build code bitmap */
918 build_page_bitmap(p);
919 }
920
921 /* we remove all the TBs in the range [start, end[ */
922 /* XXX: see if in some cases it could be faster to invalidate all the code */
923 tb = p->first_tb;
924 while (tb != NULL) {
925 n = (long)tb & 3;
926 tb = (TranslationBlock *)((long)tb & ~3);
927 tb_next = tb->page_next[n];
928 /* NOTE: this is subtle as a TB may span two physical pages */
929 if (n == 0) {
930 /* NOTE: tb_end may be after the end of the page, but
931 it is not a problem */
932 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
933 tb_end = tb_start + tb->size;
934 } else {
935 tb_start = tb->page_addr[1];
936 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
937 }
938 if (!(tb_end <= start || tb_start >= end)) {
bellardd720b932004-04-25 17:57:43 +0000939#ifdef TARGET_HAS_PRECISE_SMC
940 if (current_tb_not_found) {
941 current_tb_not_found = 0;
942 current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000943 if (env->mem_io_pc) {
bellardd720b932004-04-25 17:57:43 +0000944 /* now we have a real cpu fault */
pbrook2e70f6e2008-06-29 01:03:05 +0000945 current_tb = tb_find_pc(env->mem_io_pc);
bellardd720b932004-04-25 17:57:43 +0000946 }
947 }
948 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +0000949 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +0000950 /* If we are modifying the current TB, we must stop
951 its execution. We could be more precise by checking
952 that the modification is after the current PC, but it
953 would require a specialized function to partially
954 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +0000955
bellardd720b932004-04-25 17:57:43 +0000956 current_tb_modified = 1;
ths5fafdf22007-09-16 21:08:06 +0000957 cpu_restore_state(current_tb, env,
pbrook2e70f6e2008-06-29 01:03:05 +0000958 env->mem_io_pc, NULL);
aliguori6b917542008-11-18 19:46:41 +0000959 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
960 &current_flags);
bellardd720b932004-04-25 17:57:43 +0000961 }
962#endif /* TARGET_HAS_PRECISE_SMC */
bellard6f5a9f72005-11-26 20:12:28 +0000963 /* we need to do that to handle the case where a signal
964 occurs while doing tb_phys_invalidate() */
965 saved_tb = NULL;
966 if (env) {
967 saved_tb = env->current_tb;
968 env->current_tb = NULL;
969 }
bellard9fa3e852004-01-04 18:06:42 +0000970 tb_phys_invalidate(tb, -1);
bellard6f5a9f72005-11-26 20:12:28 +0000971 if (env) {
972 env->current_tb = saved_tb;
973 if (env->interrupt_request && env->current_tb)
974 cpu_interrupt(env, env->interrupt_request);
975 }
bellard9fa3e852004-01-04 18:06:42 +0000976 }
977 tb = tb_next;
978 }
979#if !defined(CONFIG_USER_ONLY)
980 /* if no code remaining, no need to continue to use slow writes */
981 if (!p->first_tb) {
982 invalidate_page_bitmap(p);
bellardd720b932004-04-25 17:57:43 +0000983 if (is_cpu_write_access) {
pbrook2e70f6e2008-06-29 01:03:05 +0000984 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
bellardd720b932004-04-25 17:57:43 +0000985 }
986 }
987#endif
988#ifdef TARGET_HAS_PRECISE_SMC
989 if (current_tb_modified) {
990 /* we generate a block containing just the instruction
991 modifying the memory. It will ensure that it cannot modify
992 itself */
bellardea1c1802004-06-14 18:56:36 +0000993 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +0000994 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +0000995 cpu_resume_from_signal(env, NULL);
bellard9fa3e852004-01-04 18:06:42 +0000996 }
997#endif
998}
999
1000/* len must be <= 8 and start must be a multiple of len */
aurel3200f82b82008-04-27 21:12:55 +00001001static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
bellard9fa3e852004-01-04 18:06:42 +00001002{
1003 PageDesc *p;
1004 int offset, b;
bellard59817cc2004-02-16 22:01:13 +00001005#if 0
bellarda4193c82004-06-03 14:01:43 +00001006 if (1) {
aliguori93fcfe32009-01-15 22:34:14 +00001007 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1008 cpu_single_env->mem_io_vaddr, len,
1009 cpu_single_env->eip,
1010 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
bellard59817cc2004-02-16 22:01:13 +00001011 }
1012#endif
bellard9fa3e852004-01-04 18:06:42 +00001013 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001014 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00001015 return;
1016 if (p->code_bitmap) {
1017 offset = start & ~TARGET_PAGE_MASK;
1018 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1019 if (b & ((1 << len) - 1))
1020 goto do_invalidate;
1021 } else {
1022 do_invalidate:
bellardd720b932004-04-25 17:57:43 +00001023 tb_invalidate_phys_page_range(start, start + len, 1);
bellard9fa3e852004-01-04 18:06:42 +00001024 }
1025}
1026
bellard9fa3e852004-01-04 18:06:42 +00001027#if !defined(CONFIG_SOFTMMU)
aurel3200f82b82008-04-27 21:12:55 +00001028static void tb_invalidate_phys_page(target_phys_addr_t addr,
bellardd720b932004-04-25 17:57:43 +00001029 unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001030{
aliguori6b917542008-11-18 19:46:41 +00001031 TranslationBlock *tb;
bellard9fa3e852004-01-04 18:06:42 +00001032 PageDesc *p;
aliguori6b917542008-11-18 19:46:41 +00001033 int n;
bellardd720b932004-04-25 17:57:43 +00001034#ifdef TARGET_HAS_PRECISE_SMC
aliguori6b917542008-11-18 19:46:41 +00001035 TranslationBlock *current_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001036 CPUState *env = cpu_single_env;
aliguori6b917542008-11-18 19:46:41 +00001037 int current_tb_modified = 0;
1038 target_ulong current_pc = 0;
1039 target_ulong current_cs_base = 0;
1040 int current_flags = 0;
bellardd720b932004-04-25 17:57:43 +00001041#endif
bellard9fa3e852004-01-04 18:06:42 +00001042
1043 addr &= TARGET_PAGE_MASK;
1044 p = page_find(addr >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001045 if (!p)
bellardfd6ce8f2003-05-14 19:00:11 +00001046 return;
1047 tb = p->first_tb;
bellardd720b932004-04-25 17:57:43 +00001048#ifdef TARGET_HAS_PRECISE_SMC
1049 if (tb && pc != 0) {
1050 current_tb = tb_find_pc(pc);
1051 }
1052#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001053 while (tb != NULL) {
bellard9fa3e852004-01-04 18:06:42 +00001054 n = (long)tb & 3;
1055 tb = (TranslationBlock *)((long)tb & ~3);
bellardd720b932004-04-25 17:57:43 +00001056#ifdef TARGET_HAS_PRECISE_SMC
1057 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +00001058 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +00001059 /* If we are modifying the current TB, we must stop
1060 its execution. We could be more precise by checking
1061 that the modification is after the current PC, but it
1062 would require a specialized function to partially
1063 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +00001064
bellardd720b932004-04-25 17:57:43 +00001065 current_tb_modified = 1;
1066 cpu_restore_state(current_tb, env, pc, puc);
aliguori6b917542008-11-18 19:46:41 +00001067 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1068 &current_flags);
bellardd720b932004-04-25 17:57:43 +00001069 }
1070#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +00001071 tb_phys_invalidate(tb, addr);
1072 tb = tb->page_next[n];
bellardfd6ce8f2003-05-14 19:00:11 +00001073 }
1074 p->first_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001075#ifdef TARGET_HAS_PRECISE_SMC
1076 if (current_tb_modified) {
1077 /* we generate a block containing just the instruction
1078 modifying the memory. It will ensure that it cannot modify
1079 itself */
bellardea1c1802004-06-14 18:56:36 +00001080 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001081 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001082 cpu_resume_from_signal(env, puc);
1083 }
1084#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001085}
bellard9fa3e852004-01-04 18:06:42 +00001086#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001087
1088/* add the tb in the target page and protect it if necessary */
ths5fafdf22007-09-16 21:08:06 +00001089static inline void tb_alloc_page(TranslationBlock *tb,
pbrook53a59602006-03-25 19:31:22 +00001090 unsigned int n, target_ulong page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +00001091{
1092 PageDesc *p;
bellard9fa3e852004-01-04 18:06:42 +00001093 TranslationBlock *last_first_tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001094
bellard9fa3e852004-01-04 18:06:42 +00001095 tb->page_addr[n] = page_addr;
bellard3a7d9292005-08-21 09:26:42 +00001096 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001097 tb->page_next[n] = p->first_tb;
1098 last_first_tb = p->first_tb;
1099 p->first_tb = (TranslationBlock *)((long)tb | n);
1100 invalidate_page_bitmap(p);
1101
bellard107db442004-06-22 18:48:46 +00001102#if defined(TARGET_HAS_SMC) || 1
bellardd720b932004-04-25 17:57:43 +00001103
bellard9fa3e852004-01-04 18:06:42 +00001104#if defined(CONFIG_USER_ONLY)
bellardfd6ce8f2003-05-14 19:00:11 +00001105 if (p->flags & PAGE_WRITE) {
pbrook53a59602006-03-25 19:31:22 +00001106 target_ulong addr;
1107 PageDesc *p2;
bellard9fa3e852004-01-04 18:06:42 +00001108 int prot;
1109
bellardfd6ce8f2003-05-14 19:00:11 +00001110 /* force the host page as non writable (writes will have a
1111 page fault + mprotect overhead) */
pbrook53a59602006-03-25 19:31:22 +00001112 page_addr &= qemu_host_page_mask;
bellardfd6ce8f2003-05-14 19:00:11 +00001113 prot = 0;
pbrook53a59602006-03-25 19:31:22 +00001114 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1115 addr += TARGET_PAGE_SIZE) {
1116
1117 p2 = page_find (addr >> TARGET_PAGE_BITS);
1118 if (!p2)
1119 continue;
1120 prot |= p2->flags;
1121 p2->flags &= ~PAGE_WRITE;
1122 page_get_flags(addr);
1123 }
ths5fafdf22007-09-16 21:08:06 +00001124 mprotect(g2h(page_addr), qemu_host_page_size,
bellardfd6ce8f2003-05-14 19:00:11 +00001125 (prot & PAGE_BITS) & ~PAGE_WRITE);
1126#ifdef DEBUG_TB_INVALIDATE
blueswir1ab3d1722007-11-04 07:31:40 +00001127 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
pbrook53a59602006-03-25 19:31:22 +00001128 page_addr);
bellardfd6ce8f2003-05-14 19:00:11 +00001129#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001130 }
bellard9fa3e852004-01-04 18:06:42 +00001131#else
1132 /* if some code is already present, then the pages are already
1133 protected. So we handle the case where only the first TB is
1134 allocated in a physical page */
1135 if (!last_first_tb) {
bellard6a00d602005-11-21 23:25:50 +00001136 tlb_protect_code(page_addr);
bellard9fa3e852004-01-04 18:06:42 +00001137 }
1138#endif
bellardd720b932004-04-25 17:57:43 +00001139
1140#endif /* TARGET_HAS_SMC */
bellardfd6ce8f2003-05-14 19:00:11 +00001141}
1142
1143/* Allocate a new translation block. Flush the translation buffer if
1144 too many translation blocks or too much generated code. */
bellardc27004e2005-01-03 23:35:10 +00001145TranslationBlock *tb_alloc(target_ulong pc)
bellardfd6ce8f2003-05-14 19:00:11 +00001146{
1147 TranslationBlock *tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001148
bellard26a5f132008-05-28 12:30:31 +00001149 if (nb_tbs >= code_gen_max_blocks ||
1150 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
bellardd4e81642003-05-25 16:46:15 +00001151 return NULL;
bellardfd6ce8f2003-05-14 19:00:11 +00001152 tb = &tbs[nb_tbs++];
1153 tb->pc = pc;
bellardb448f2f2004-02-25 23:24:04 +00001154 tb->cflags = 0;
bellardd4e81642003-05-25 16:46:15 +00001155 return tb;
1156}
1157
pbrook2e70f6e2008-06-29 01:03:05 +00001158void tb_free(TranslationBlock *tb)
1159{
thsbf20dc02008-06-30 17:22:19 +00001160 /* In practice this is mostly used for single use temporary TB
pbrook2e70f6e2008-06-29 01:03:05 +00001161 Ignore the hard cases and just back up if this TB happens to
1162 be the last one generated. */
1163 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1164 code_gen_ptr = tb->tc_ptr;
1165 nb_tbs--;
1166 }
1167}
1168
bellard9fa3e852004-01-04 18:06:42 +00001169/* add a new TB and link it to the physical page tables. phys_page2 is
1170 (-1) to indicate that only one page contains the TB. */
ths5fafdf22007-09-16 21:08:06 +00001171void tb_link_phys(TranslationBlock *tb,
bellard9fa3e852004-01-04 18:06:42 +00001172 target_ulong phys_pc, target_ulong phys_page2)
bellardd4e81642003-05-25 16:46:15 +00001173{
bellard9fa3e852004-01-04 18:06:42 +00001174 unsigned int h;
1175 TranslationBlock **ptb;
1176
pbrookc8a706f2008-06-02 16:16:42 +00001177 /* Grab the mmap lock to stop another thread invalidating this TB
1178 before we are done. */
1179 mmap_lock();
bellard9fa3e852004-01-04 18:06:42 +00001180 /* add in the physical hash table */
1181 h = tb_phys_hash_func(phys_pc);
1182 ptb = &tb_phys_hash[h];
1183 tb->phys_hash_next = *ptb;
1184 *ptb = tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001185
1186 /* add in the page list */
bellard9fa3e852004-01-04 18:06:42 +00001187 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1188 if (phys_page2 != -1)
1189 tb_alloc_page(tb, 1, phys_page2);
1190 else
1191 tb->page_addr[1] = -1;
bellard9fa3e852004-01-04 18:06:42 +00001192
bellardd4e81642003-05-25 16:46:15 +00001193 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1194 tb->jmp_next[0] = NULL;
1195 tb->jmp_next[1] = NULL;
1196
1197 /* init original jump addresses */
1198 if (tb->tb_next_offset[0] != 0xffff)
1199 tb_reset_jump(tb, 0);
1200 if (tb->tb_next_offset[1] != 0xffff)
1201 tb_reset_jump(tb, 1);
bellard8a40a182005-11-20 10:35:40 +00001202
1203#ifdef DEBUG_TB_CHECK
1204 tb_page_check();
1205#endif
pbrookc8a706f2008-06-02 16:16:42 +00001206 mmap_unlock();
bellardfd6ce8f2003-05-14 19:00:11 +00001207}
1208
bellarda513fe12003-05-27 23:29:48 +00001209/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1210 tb[1].tc_ptr. Return NULL if not found */
1211TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1212{
1213 int m_min, m_max, m;
1214 unsigned long v;
1215 TranslationBlock *tb;
1216
1217 if (nb_tbs <= 0)
1218 return NULL;
1219 if (tc_ptr < (unsigned long)code_gen_buffer ||
1220 tc_ptr >= (unsigned long)code_gen_ptr)
1221 return NULL;
1222 /* binary search (cf Knuth) */
1223 m_min = 0;
1224 m_max = nb_tbs - 1;
1225 while (m_min <= m_max) {
1226 m = (m_min + m_max) >> 1;
1227 tb = &tbs[m];
1228 v = (unsigned long)tb->tc_ptr;
1229 if (v == tc_ptr)
1230 return tb;
1231 else if (tc_ptr < v) {
1232 m_max = m - 1;
1233 } else {
1234 m_min = m + 1;
1235 }
ths5fafdf22007-09-16 21:08:06 +00001236 }
bellarda513fe12003-05-27 23:29:48 +00001237 return &tbs[m_max];
1238}
bellard75012672003-06-21 13:11:07 +00001239
bellardea041c02003-06-25 16:16:50 +00001240static void tb_reset_jump_recursive(TranslationBlock *tb);
1241
1242static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1243{
1244 TranslationBlock *tb1, *tb_next, **ptb;
1245 unsigned int n1;
1246
1247 tb1 = tb->jmp_next[n];
1248 if (tb1 != NULL) {
1249 /* find head of list */
1250 for(;;) {
1251 n1 = (long)tb1 & 3;
1252 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1253 if (n1 == 2)
1254 break;
1255 tb1 = tb1->jmp_next[n1];
1256 }
1257 /* we are now sure now that tb jumps to tb1 */
1258 tb_next = tb1;
1259
1260 /* remove tb from the jmp_first list */
1261 ptb = &tb_next->jmp_first;
1262 for(;;) {
1263 tb1 = *ptb;
1264 n1 = (long)tb1 & 3;
1265 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1266 if (n1 == n && tb1 == tb)
1267 break;
1268 ptb = &tb1->jmp_next[n1];
1269 }
1270 *ptb = tb->jmp_next[n];
1271 tb->jmp_next[n] = NULL;
ths3b46e622007-09-17 08:09:54 +00001272
bellardea041c02003-06-25 16:16:50 +00001273 /* suppress the jump to next tb in generated code */
1274 tb_reset_jump(tb, n);
1275
bellard01243112004-01-04 15:48:17 +00001276 /* suppress jumps in the tb on which we could have jumped */
bellardea041c02003-06-25 16:16:50 +00001277 tb_reset_jump_recursive(tb_next);
1278 }
1279}
1280
1281static void tb_reset_jump_recursive(TranslationBlock *tb)
1282{
1283 tb_reset_jump_recursive2(tb, 0);
1284 tb_reset_jump_recursive2(tb, 1);
1285}
1286
bellard1fddef42005-04-17 19:16:13 +00001287#if defined(TARGET_HAS_ICE)
bellardd720b932004-04-25 17:57:43 +00001288static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1289{
j_mayer9b3c35e2007-04-07 11:21:28 +00001290 target_phys_addr_t addr;
1291 target_ulong pd;
pbrookc2f07f82006-04-08 17:14:56 +00001292 ram_addr_t ram_addr;
1293 PhysPageDesc *p;
bellardd720b932004-04-25 17:57:43 +00001294
pbrookc2f07f82006-04-08 17:14:56 +00001295 addr = cpu_get_phys_page_debug(env, pc);
1296 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1297 if (!p) {
1298 pd = IO_MEM_UNASSIGNED;
1299 } else {
1300 pd = p->phys_offset;
1301 }
1302 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
pbrook706cd4b2006-04-08 17:36:21 +00001303 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
bellardd720b932004-04-25 17:57:43 +00001304}
bellardc27004e2005-01-03 23:35:10 +00001305#endif
bellardd720b932004-04-25 17:57:43 +00001306
pbrook6658ffb2007-03-16 23:58:11 +00001307/* Add a watchpoint. */
aliguoria1d1bb32008-11-18 20:07:32 +00001308int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1309 int flags, CPUWatchpoint **watchpoint)
pbrook6658ffb2007-03-16 23:58:11 +00001310{
aliguorib4051332008-11-18 20:14:20 +00001311 target_ulong len_mask = ~(len - 1);
aliguoric0ce9982008-11-25 22:13:57 +00001312 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001313
aliguorib4051332008-11-18 20:14:20 +00001314 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1315 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1316 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1317 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1318 return -EINVAL;
1319 }
aliguoria1d1bb32008-11-18 20:07:32 +00001320 wp = qemu_malloc(sizeof(*wp));
1321 if (!wp)
aliguori426cd5d2008-11-18 21:52:54 +00001322 return -ENOMEM;
pbrook6658ffb2007-03-16 23:58:11 +00001323
aliguoria1d1bb32008-11-18 20:07:32 +00001324 wp->vaddr = addr;
aliguorib4051332008-11-18 20:14:20 +00001325 wp->len_mask = len_mask;
aliguoria1d1bb32008-11-18 20:07:32 +00001326 wp->flags = flags;
1327
aliguori2dc9f412008-11-18 20:56:59 +00001328 /* keep all GDB-injected watchpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001329 if (flags & BP_GDB)
1330 TAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
1331 else
1332 TAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001333
pbrook6658ffb2007-03-16 23:58:11 +00001334 tlb_flush_page(env, addr);
aliguoria1d1bb32008-11-18 20:07:32 +00001335
1336 if (watchpoint)
1337 *watchpoint = wp;
1338 return 0;
pbrook6658ffb2007-03-16 23:58:11 +00001339}
1340
aliguoria1d1bb32008-11-18 20:07:32 +00001341/* Remove a specific watchpoint. */
1342int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1343 int flags)
pbrook6658ffb2007-03-16 23:58:11 +00001344{
aliguorib4051332008-11-18 20:14:20 +00001345 target_ulong len_mask = ~(len - 1);
aliguoria1d1bb32008-11-18 20:07:32 +00001346 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001347
aliguoric0ce9982008-11-25 22:13:57 +00001348 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00001349 if (addr == wp->vaddr && len_mask == wp->len_mask
aliguori6e140f22008-11-18 20:37:55 +00001350 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
aliguoria1d1bb32008-11-18 20:07:32 +00001351 cpu_watchpoint_remove_by_ref(env, wp);
pbrook6658ffb2007-03-16 23:58:11 +00001352 return 0;
1353 }
1354 }
aliguoria1d1bb32008-11-18 20:07:32 +00001355 return -ENOENT;
pbrook6658ffb2007-03-16 23:58:11 +00001356}
1357
aliguoria1d1bb32008-11-18 20:07:32 +00001358/* Remove a specific watchpoint by reference. */
1359void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1360{
aliguoric0ce9982008-11-25 22:13:57 +00001361 TAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
edgar_igl7d03f822008-05-17 18:58:29 +00001362
aliguoria1d1bb32008-11-18 20:07:32 +00001363 tlb_flush_page(env, watchpoint->vaddr);
1364
1365 qemu_free(watchpoint);
edgar_igl7d03f822008-05-17 18:58:29 +00001366}
1367
aliguoria1d1bb32008-11-18 20:07:32 +00001368/* Remove all matching watchpoints. */
1369void cpu_watchpoint_remove_all(CPUState *env, int mask)
1370{
aliguoric0ce9982008-11-25 22:13:57 +00001371 CPUWatchpoint *wp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001372
aliguoric0ce9982008-11-25 22:13:57 +00001373 TAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001374 if (wp->flags & mask)
1375 cpu_watchpoint_remove_by_ref(env, wp);
aliguoric0ce9982008-11-25 22:13:57 +00001376 }
aliguoria1d1bb32008-11-18 20:07:32 +00001377}
1378
1379/* Add a breakpoint. */
1380int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1381 CPUBreakpoint **breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001382{
bellard1fddef42005-04-17 19:16:13 +00001383#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001384 CPUBreakpoint *bp;
ths3b46e622007-09-17 08:09:54 +00001385
aliguoria1d1bb32008-11-18 20:07:32 +00001386 bp = qemu_malloc(sizeof(*bp));
1387 if (!bp)
aliguori426cd5d2008-11-18 21:52:54 +00001388 return -ENOMEM;
aliguoria1d1bb32008-11-18 20:07:32 +00001389
1390 bp->pc = pc;
1391 bp->flags = flags;
1392
aliguori2dc9f412008-11-18 20:56:59 +00001393 /* keep all GDB-injected breakpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001394 if (flags & BP_GDB)
1395 TAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
1396 else
1397 TAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001398
1399 breakpoint_invalidate(env, pc);
1400
1401 if (breakpoint)
1402 *breakpoint = bp;
1403 return 0;
1404#else
1405 return -ENOSYS;
1406#endif
1407}
1408
1409/* Remove a specific breakpoint. */
1410int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1411{
1412#if defined(TARGET_HAS_ICE)
1413 CPUBreakpoint *bp;
1414
aliguoric0ce9982008-11-25 22:13:57 +00001415 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00001416 if (bp->pc == pc && bp->flags == flags) {
1417 cpu_breakpoint_remove_by_ref(env, bp);
bellard4c3a88a2003-07-26 12:06:08 +00001418 return 0;
aliguoria1d1bb32008-11-18 20:07:32 +00001419 }
bellard4c3a88a2003-07-26 12:06:08 +00001420 }
aliguoria1d1bb32008-11-18 20:07:32 +00001421 return -ENOENT;
bellard4c3a88a2003-07-26 12:06:08 +00001422#else
aliguoria1d1bb32008-11-18 20:07:32 +00001423 return -ENOSYS;
bellard4c3a88a2003-07-26 12:06:08 +00001424#endif
1425}
1426
aliguoria1d1bb32008-11-18 20:07:32 +00001427/* Remove a specific breakpoint by reference. */
1428void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001429{
bellard1fddef42005-04-17 19:16:13 +00001430#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001431 TAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
bellardd720b932004-04-25 17:57:43 +00001432
aliguoria1d1bb32008-11-18 20:07:32 +00001433 breakpoint_invalidate(env, breakpoint->pc);
1434
1435 qemu_free(breakpoint);
1436#endif
1437}
1438
1439/* Remove all matching breakpoints. */
1440void cpu_breakpoint_remove_all(CPUState *env, int mask)
1441{
1442#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001443 CPUBreakpoint *bp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001444
aliguoric0ce9982008-11-25 22:13:57 +00001445 TAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001446 if (bp->flags & mask)
1447 cpu_breakpoint_remove_by_ref(env, bp);
aliguoric0ce9982008-11-25 22:13:57 +00001448 }
bellard4c3a88a2003-07-26 12:06:08 +00001449#endif
1450}
1451
bellardc33a3462003-07-29 20:50:33 +00001452/* enable or disable single step mode. EXCP_DEBUG is returned by the
1453 CPU loop after each instruction */
1454void cpu_single_step(CPUState *env, int enabled)
1455{
bellard1fddef42005-04-17 19:16:13 +00001456#if defined(TARGET_HAS_ICE)
bellardc33a3462003-07-29 20:50:33 +00001457 if (env->singlestep_enabled != enabled) {
1458 env->singlestep_enabled = enabled;
1459 /* must flush all the translated code to avoid inconsistancies */
bellard9fa3e852004-01-04 18:06:42 +00001460 /* XXX: only flush what is necessary */
bellard01243112004-01-04 15:48:17 +00001461 tb_flush(env);
bellardc33a3462003-07-29 20:50:33 +00001462 }
1463#endif
1464}
1465
bellard34865132003-10-05 14:28:56 +00001466/* enable or disable low levels log */
1467void cpu_set_log(int log_flags)
1468{
1469 loglevel = log_flags;
1470 if (loglevel && !logfile) {
pbrook11fcfab2007-07-01 18:21:11 +00001471 logfile = fopen(logfilename, log_append ? "a" : "w");
bellard34865132003-10-05 14:28:56 +00001472 if (!logfile) {
1473 perror(logfilename);
1474 _exit(1);
1475 }
bellard9fa3e852004-01-04 18:06:42 +00001476#if !defined(CONFIG_SOFTMMU)
1477 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1478 {
blueswir1b55266b2008-09-20 08:07:15 +00001479 static char logfile_buf[4096];
bellard9fa3e852004-01-04 18:06:42 +00001480 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1481 }
1482#else
bellard34865132003-10-05 14:28:56 +00001483 setvbuf(logfile, NULL, _IOLBF, 0);
bellard9fa3e852004-01-04 18:06:42 +00001484#endif
pbrooke735b912007-06-30 13:53:24 +00001485 log_append = 1;
1486 }
1487 if (!loglevel && logfile) {
1488 fclose(logfile);
1489 logfile = NULL;
bellard34865132003-10-05 14:28:56 +00001490 }
1491}
1492
1493void cpu_set_log_filename(const char *filename)
1494{
1495 logfilename = strdup(filename);
pbrooke735b912007-06-30 13:53:24 +00001496 if (logfile) {
1497 fclose(logfile);
1498 logfile = NULL;
1499 }
1500 cpu_set_log(loglevel);
bellard34865132003-10-05 14:28:56 +00001501}
bellardc33a3462003-07-29 20:50:33 +00001502
bellard01243112004-01-04 15:48:17 +00001503/* mask must never be zero, except for A20 change call */
bellard68a79312003-06-30 13:12:32 +00001504void cpu_interrupt(CPUState *env, int mask)
bellardea041c02003-06-25 16:16:50 +00001505{
pbrookd5975362008-06-07 20:50:51 +00001506#if !defined(USE_NPTL)
bellardea041c02003-06-25 16:16:50 +00001507 TranslationBlock *tb;
aurel3215a51152008-03-28 22:29:15 +00001508 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
pbrookd5975362008-06-07 20:50:51 +00001509#endif
pbrook2e70f6e2008-06-29 01:03:05 +00001510 int old_mask;
bellard59817cc2004-02-16 22:01:13 +00001511
pbrook2e70f6e2008-06-29 01:03:05 +00001512 old_mask = env->interrupt_request;
pbrookd5975362008-06-07 20:50:51 +00001513 /* FIXME: This is probably not threadsafe. A different thread could
thsbf20dc02008-06-30 17:22:19 +00001514 be in the middle of a read-modify-write operation. */
bellard68a79312003-06-30 13:12:32 +00001515 env->interrupt_request |= mask;
pbrookd5975362008-06-07 20:50:51 +00001516#if defined(USE_NPTL)
1517 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1518 problem and hope the cpu will stop of its own accord. For userspace
1519 emulation this often isn't actually as bad as it sounds. Often
1520 signals are used primarily to interrupt blocking syscalls. */
1521#else
pbrook2e70f6e2008-06-29 01:03:05 +00001522 if (use_icount) {
pbrook266910c2008-07-09 15:31:50 +00001523 env->icount_decr.u16.high = 0xffff;
pbrook2e70f6e2008-06-29 01:03:05 +00001524#ifndef CONFIG_USER_ONLY
1525 /* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
1526 an async event happened and we need to process it. */
1527 if (!can_do_io(env)
1528 && (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
1529 cpu_abort(env, "Raised interrupt while not in I/O function");
1530 }
1531#endif
1532 } else {
1533 tb = env->current_tb;
1534 /* if the cpu is currently executing code, we must unlink it and
1535 all the potentially executing TB */
1536 if (tb && !testandset(&interrupt_lock)) {
1537 env->current_tb = NULL;
1538 tb_reset_jump_recursive(tb);
1539 resetlock(&interrupt_lock);
1540 }
bellardea041c02003-06-25 16:16:50 +00001541 }
pbrookd5975362008-06-07 20:50:51 +00001542#endif
bellardea041c02003-06-25 16:16:50 +00001543}
1544
bellardb54ad042004-05-20 13:42:52 +00001545void cpu_reset_interrupt(CPUState *env, int mask)
1546{
1547 env->interrupt_request &= ~mask;
1548}
1549
blueswir1c7cd6a32008-10-02 18:27:46 +00001550const CPULogItem cpu_log_items[] = {
ths5fafdf22007-09-16 21:08:06 +00001551 { CPU_LOG_TB_OUT_ASM, "out_asm",
bellardf193c792004-03-21 17:06:25 +00001552 "show generated host assembly code for each compiled TB" },
1553 { CPU_LOG_TB_IN_ASM, "in_asm",
1554 "show target assembly code for each compiled TB" },
ths5fafdf22007-09-16 21:08:06 +00001555 { CPU_LOG_TB_OP, "op",
bellard57fec1f2008-02-01 10:50:11 +00001556 "show micro ops for each compiled TB" },
bellardf193c792004-03-21 17:06:25 +00001557 { CPU_LOG_TB_OP_OPT, "op_opt",
blueswir1e01a1152008-03-14 17:37:11 +00001558 "show micro ops "
1559#ifdef TARGET_I386
1560 "before eflags optimization and "
bellardf193c792004-03-21 17:06:25 +00001561#endif
blueswir1e01a1152008-03-14 17:37:11 +00001562 "after liveness analysis" },
bellardf193c792004-03-21 17:06:25 +00001563 { CPU_LOG_INT, "int",
1564 "show interrupts/exceptions in short format" },
1565 { CPU_LOG_EXEC, "exec",
1566 "show trace before each executed TB (lots of logs)" },
bellard9fddaa02004-05-21 12:59:32 +00001567 { CPU_LOG_TB_CPU, "cpu",
thse91c8a72007-06-03 13:35:16 +00001568 "show CPU state before block translation" },
bellardf193c792004-03-21 17:06:25 +00001569#ifdef TARGET_I386
1570 { CPU_LOG_PCALL, "pcall",
1571 "show protected mode far calls/returns/exceptions" },
1572#endif
bellard8e3a9fd2004-10-09 17:32:58 +00001573#ifdef DEBUG_IOPORT
bellardfd872592004-05-12 19:11:15 +00001574 { CPU_LOG_IOPORT, "ioport",
1575 "show all i/o ports accesses" },
bellard8e3a9fd2004-10-09 17:32:58 +00001576#endif
bellardf193c792004-03-21 17:06:25 +00001577 { 0, NULL, NULL },
1578};
1579
1580static int cmp1(const char *s1, int n, const char *s2)
1581{
1582 if (strlen(s2) != n)
1583 return 0;
1584 return memcmp(s1, s2, n) == 0;
1585}
ths3b46e622007-09-17 08:09:54 +00001586
bellardf193c792004-03-21 17:06:25 +00001587/* takes a comma separated list of log masks. Return 0 if error. */
1588int cpu_str_to_log_mask(const char *str)
1589{
blueswir1c7cd6a32008-10-02 18:27:46 +00001590 const CPULogItem *item;
bellardf193c792004-03-21 17:06:25 +00001591 int mask;
1592 const char *p, *p1;
1593
1594 p = str;
1595 mask = 0;
1596 for(;;) {
1597 p1 = strchr(p, ',');
1598 if (!p1)
1599 p1 = p + strlen(p);
bellard8e3a9fd2004-10-09 17:32:58 +00001600 if(cmp1(p,p1-p,"all")) {
1601 for(item = cpu_log_items; item->mask != 0; item++) {
1602 mask |= item->mask;
1603 }
1604 } else {
bellardf193c792004-03-21 17:06:25 +00001605 for(item = cpu_log_items; item->mask != 0; item++) {
1606 if (cmp1(p, p1 - p, item->name))
1607 goto found;
1608 }
1609 return 0;
bellard8e3a9fd2004-10-09 17:32:58 +00001610 }
bellardf193c792004-03-21 17:06:25 +00001611 found:
1612 mask |= item->mask;
1613 if (*p1 != ',')
1614 break;
1615 p = p1 + 1;
1616 }
1617 return mask;
1618}
bellardea041c02003-06-25 16:16:50 +00001619
bellard75012672003-06-21 13:11:07 +00001620void cpu_abort(CPUState *env, const char *fmt, ...)
1621{
1622 va_list ap;
pbrook493ae1f2007-11-23 16:53:59 +00001623 va_list ap2;
bellard75012672003-06-21 13:11:07 +00001624
1625 va_start(ap, fmt);
pbrook493ae1f2007-11-23 16:53:59 +00001626 va_copy(ap2, ap);
bellard75012672003-06-21 13:11:07 +00001627 fprintf(stderr, "qemu: fatal: ");
1628 vfprintf(stderr, fmt, ap);
1629 fprintf(stderr, "\n");
1630#ifdef TARGET_I386
bellard7fe48482004-10-09 18:08:01 +00001631 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1632#else
1633 cpu_dump_state(env, stderr, fprintf, 0);
bellard75012672003-06-21 13:11:07 +00001634#endif
aliguori93fcfe32009-01-15 22:34:14 +00001635 if (qemu_log_enabled()) {
1636 qemu_log("qemu: fatal: ");
1637 qemu_log_vprintf(fmt, ap2);
1638 qemu_log("\n");
j_mayerf9373292007-09-29 12:18:20 +00001639#ifdef TARGET_I386
aliguori93fcfe32009-01-15 22:34:14 +00001640 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
j_mayerf9373292007-09-29 12:18:20 +00001641#else
aliguori93fcfe32009-01-15 22:34:14 +00001642 log_cpu_state(env, 0);
j_mayerf9373292007-09-29 12:18:20 +00001643#endif
aliguori31b1a7b2009-01-15 22:35:09 +00001644 qemu_log_flush();
aliguori93fcfe32009-01-15 22:34:14 +00001645 qemu_log_close();
balrog924edca2007-06-10 14:07:13 +00001646 }
pbrook493ae1f2007-11-23 16:53:59 +00001647 va_end(ap2);
j_mayerf9373292007-09-29 12:18:20 +00001648 va_end(ap);
bellard75012672003-06-21 13:11:07 +00001649 abort();
1650}
1651
thsc5be9f02007-02-28 20:20:53 +00001652CPUState *cpu_copy(CPUState *env)
1653{
ths01ba9812007-12-09 02:22:57 +00001654 CPUState *new_env = cpu_init(env->cpu_model_str);
thsc5be9f02007-02-28 20:20:53 +00001655 CPUState *next_cpu = new_env->next_cpu;
1656 int cpu_index = new_env->cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001657#if defined(TARGET_HAS_ICE)
1658 CPUBreakpoint *bp;
1659 CPUWatchpoint *wp;
1660#endif
1661
thsc5be9f02007-02-28 20:20:53 +00001662 memcpy(new_env, env, sizeof(CPUState));
aliguori5a38f082009-01-15 20:16:51 +00001663
1664 /* Preserve chaining and index. */
thsc5be9f02007-02-28 20:20:53 +00001665 new_env->next_cpu = next_cpu;
1666 new_env->cpu_index = cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001667
1668 /* Clone all break/watchpoints.
1669 Note: Once we support ptrace with hw-debug register access, make sure
1670 BP_CPU break/watchpoints are handled correctly on clone. */
1671 TAILQ_INIT(&env->breakpoints);
1672 TAILQ_INIT(&env->watchpoints);
1673#if defined(TARGET_HAS_ICE)
1674 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1675 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
1676 }
1677 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
1678 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
1679 wp->flags, NULL);
1680 }
1681#endif
1682
thsc5be9f02007-02-28 20:20:53 +00001683 return new_env;
1684}
1685
bellard01243112004-01-04 15:48:17 +00001686#if !defined(CONFIG_USER_ONLY)
1687
edgar_igl5c751e92008-05-06 08:44:21 +00001688static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1689{
1690 unsigned int i;
1691
1692 /* Discard jump cache entries for any tb which might potentially
1693 overlap the flushed page. */
1694 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1695 memset (&env->tb_jmp_cache[i], 0,
1696 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1697
1698 i = tb_jmp_cache_hash_page(addr);
1699 memset (&env->tb_jmp_cache[i], 0,
1700 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
1701}
1702
bellardee8b7022004-02-03 23:35:10 +00001703/* NOTE: if flush_global is true, also flush global entries (not
1704 implemented yet) */
1705void tlb_flush(CPUState *env, int flush_global)
bellard33417e72003-08-10 21:47:01 +00001706{
bellard33417e72003-08-10 21:47:01 +00001707 int i;
bellard01243112004-01-04 15:48:17 +00001708
bellard9fa3e852004-01-04 18:06:42 +00001709#if defined(DEBUG_TLB)
1710 printf("tlb_flush:\n");
1711#endif
bellard01243112004-01-04 15:48:17 +00001712 /* must reset current TB so that interrupts cannot modify the
1713 links while we are modifying them */
1714 env->current_tb = NULL;
1715
bellard33417e72003-08-10 21:47:01 +00001716 for(i = 0; i < CPU_TLB_SIZE; i++) {
bellard84b7b8e2005-11-28 21:19:04 +00001717 env->tlb_table[0][i].addr_read = -1;
1718 env->tlb_table[0][i].addr_write = -1;
1719 env->tlb_table[0][i].addr_code = -1;
1720 env->tlb_table[1][i].addr_read = -1;
1721 env->tlb_table[1][i].addr_write = -1;
1722 env->tlb_table[1][i].addr_code = -1;
j_mayer6fa4cea2007-04-05 06:43:27 +00001723#if (NB_MMU_MODES >= 3)
1724 env->tlb_table[2][i].addr_read = -1;
1725 env->tlb_table[2][i].addr_write = -1;
1726 env->tlb_table[2][i].addr_code = -1;
1727#if (NB_MMU_MODES == 4)
1728 env->tlb_table[3][i].addr_read = -1;
1729 env->tlb_table[3][i].addr_write = -1;
1730 env->tlb_table[3][i].addr_code = -1;
1731#endif
1732#endif
bellard33417e72003-08-10 21:47:01 +00001733 }
bellard9fa3e852004-01-04 18:06:42 +00001734
bellard8a40a182005-11-20 10:35:40 +00001735 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
bellard9fa3e852004-01-04 18:06:42 +00001736
bellard0a962c02005-02-10 22:00:27 +00001737#ifdef USE_KQEMU
1738 if (env->kqemu_enabled) {
1739 kqemu_flush(env, flush_global);
1740 }
1741#endif
bellarde3db7222005-01-26 22:00:47 +00001742 tlb_flush_count++;
bellard33417e72003-08-10 21:47:01 +00001743}
1744
bellard274da6b2004-05-20 21:56:27 +00001745static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
bellard61382a52003-10-27 21:22:23 +00001746{
ths5fafdf22007-09-16 21:08:06 +00001747 if (addr == (tlb_entry->addr_read &
bellard84b7b8e2005-11-28 21:19:04 +00001748 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001749 addr == (tlb_entry->addr_write &
bellard84b7b8e2005-11-28 21:19:04 +00001750 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001751 addr == (tlb_entry->addr_code &
bellard84b7b8e2005-11-28 21:19:04 +00001752 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1753 tlb_entry->addr_read = -1;
1754 tlb_entry->addr_write = -1;
1755 tlb_entry->addr_code = -1;
1756 }
bellard61382a52003-10-27 21:22:23 +00001757}
1758
bellard2e126692004-04-25 21:28:44 +00001759void tlb_flush_page(CPUState *env, target_ulong addr)
bellard33417e72003-08-10 21:47:01 +00001760{
bellard8a40a182005-11-20 10:35:40 +00001761 int i;
bellard01243112004-01-04 15:48:17 +00001762
bellard9fa3e852004-01-04 18:06:42 +00001763#if defined(DEBUG_TLB)
bellard108c49b2005-07-24 12:55:09 +00001764 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
bellard9fa3e852004-01-04 18:06:42 +00001765#endif
bellard01243112004-01-04 15:48:17 +00001766 /* must reset current TB so that interrupts cannot modify the
1767 links while we are modifying them */
1768 env->current_tb = NULL;
bellard33417e72003-08-10 21:47:01 +00001769
bellard61382a52003-10-27 21:22:23 +00001770 addr &= TARGET_PAGE_MASK;
bellard33417e72003-08-10 21:47:01 +00001771 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
bellard84b7b8e2005-11-28 21:19:04 +00001772 tlb_flush_entry(&env->tlb_table[0][i], addr);
1773 tlb_flush_entry(&env->tlb_table[1][i], addr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001774#if (NB_MMU_MODES >= 3)
1775 tlb_flush_entry(&env->tlb_table[2][i], addr);
1776#if (NB_MMU_MODES == 4)
1777 tlb_flush_entry(&env->tlb_table[3][i], addr);
1778#endif
1779#endif
bellard01243112004-01-04 15:48:17 +00001780
edgar_igl5c751e92008-05-06 08:44:21 +00001781 tlb_flush_jmp_cache(env, addr);
bellard9fa3e852004-01-04 18:06:42 +00001782
bellard0a962c02005-02-10 22:00:27 +00001783#ifdef USE_KQEMU
1784 if (env->kqemu_enabled) {
1785 kqemu_flush_page(env, addr);
1786 }
1787#endif
bellard9fa3e852004-01-04 18:06:42 +00001788}
1789
bellard9fa3e852004-01-04 18:06:42 +00001790/* update the TLBs so that writes to code in the virtual page 'addr'
1791 can be detected */
bellard6a00d602005-11-21 23:25:50 +00001792static void tlb_protect_code(ram_addr_t ram_addr)
bellard61382a52003-10-27 21:22:23 +00001793{
ths5fafdf22007-09-16 21:08:06 +00001794 cpu_physical_memory_reset_dirty(ram_addr,
bellard6a00d602005-11-21 23:25:50 +00001795 ram_addr + TARGET_PAGE_SIZE,
1796 CODE_DIRTY_FLAG);
bellard9fa3e852004-01-04 18:06:42 +00001797}
1798
bellard9fa3e852004-01-04 18:06:42 +00001799/* update the TLB so that writes in physical page 'phys_addr' are no longer
bellard3a7d9292005-08-21 09:26:42 +00001800 tested for self modifying code */
ths5fafdf22007-09-16 21:08:06 +00001801static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +00001802 target_ulong vaddr)
bellard9fa3e852004-01-04 18:06:42 +00001803{
bellard3a7d9292005-08-21 09:26:42 +00001804 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
bellard1ccde1c2004-02-06 19:46:14 +00001805}
1806
ths5fafdf22007-09-16 21:08:06 +00001807static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
bellard1ccde1c2004-02-06 19:46:14 +00001808 unsigned long start, unsigned long length)
1809{
1810 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00001811 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1812 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00001813 if ((addr - start) < length) {
pbrook0f459d12008-06-09 00:20:13 +00001814 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
bellard1ccde1c2004-02-06 19:46:14 +00001815 }
1816 }
1817}
1818
bellard3a7d9292005-08-21 09:26:42 +00001819void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +00001820 int dirty_flags)
bellard1ccde1c2004-02-06 19:46:14 +00001821{
1822 CPUState *env;
bellard4f2ac232004-04-26 19:44:02 +00001823 unsigned long length, start1;
bellard0a962c02005-02-10 22:00:27 +00001824 int i, mask, len;
1825 uint8_t *p;
bellard1ccde1c2004-02-06 19:46:14 +00001826
1827 start &= TARGET_PAGE_MASK;
1828 end = TARGET_PAGE_ALIGN(end);
1829
1830 length = end - start;
1831 if (length == 0)
1832 return;
bellard0a962c02005-02-10 22:00:27 +00001833 len = length >> TARGET_PAGE_BITS;
bellard3a7d9292005-08-21 09:26:42 +00001834#ifdef USE_KQEMU
bellard6a00d602005-11-21 23:25:50 +00001835 /* XXX: should not depend on cpu context */
1836 env = first_cpu;
bellard3a7d9292005-08-21 09:26:42 +00001837 if (env->kqemu_enabled) {
bellardf23db162005-08-21 19:12:28 +00001838 ram_addr_t addr;
1839 addr = start;
1840 for(i = 0; i < len; i++) {
1841 kqemu_set_notdirty(env, addr);
1842 addr += TARGET_PAGE_SIZE;
1843 }
bellard3a7d9292005-08-21 09:26:42 +00001844 }
1845#endif
bellardf23db162005-08-21 19:12:28 +00001846 mask = ~dirty_flags;
1847 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
1848 for(i = 0; i < len; i++)
1849 p[i] &= mask;
1850
bellard1ccde1c2004-02-06 19:46:14 +00001851 /* we modify the TLB cache so that the dirty bit will be set again
1852 when accessing the range */
bellard59817cc2004-02-16 22:01:13 +00001853 start1 = start + (unsigned long)phys_ram_base;
bellard6a00d602005-11-21 23:25:50 +00001854 for(env = first_cpu; env != NULL; env = env->next_cpu) {
1855 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001856 tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
bellard6a00d602005-11-21 23:25:50 +00001857 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001858 tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
j_mayer6fa4cea2007-04-05 06:43:27 +00001859#if (NB_MMU_MODES >= 3)
1860 for(i = 0; i < CPU_TLB_SIZE; i++)
1861 tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
1862#if (NB_MMU_MODES == 4)
1863 for(i = 0; i < CPU_TLB_SIZE; i++)
1864 tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
1865#endif
1866#endif
bellard6a00d602005-11-21 23:25:50 +00001867 }
bellard1ccde1c2004-02-06 19:46:14 +00001868}
1869
aliguori74576192008-10-06 14:02:03 +00001870int cpu_physical_memory_set_dirty_tracking(int enable)
1871{
1872 in_migration = enable;
1873 return 0;
1874}
1875
1876int cpu_physical_memory_get_dirty_tracking(void)
1877{
1878 return in_migration;
1879}
1880
aliguori2bec46d2008-11-24 20:21:41 +00001881void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr)
1882{
1883 if (kvm_enabled())
1884 kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
1885}
1886
bellard3a7d9292005-08-21 09:26:42 +00001887static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
1888{
1889 ram_addr_t ram_addr;
1890
bellard84b7b8e2005-11-28 21:19:04 +00001891 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
ths5fafdf22007-09-16 21:08:06 +00001892 ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
bellard3a7d9292005-08-21 09:26:42 +00001893 tlb_entry->addend - (unsigned long)phys_ram_base;
1894 if (!cpu_physical_memory_is_dirty(ram_addr)) {
pbrook0f459d12008-06-09 00:20:13 +00001895 tlb_entry->addr_write |= TLB_NOTDIRTY;
bellard3a7d9292005-08-21 09:26:42 +00001896 }
1897 }
1898}
1899
1900/* update the TLB according to the current state of the dirty bits */
1901void cpu_tlb_update_dirty(CPUState *env)
1902{
1903 int i;
1904 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001905 tlb_update_dirty(&env->tlb_table[0][i]);
bellard3a7d9292005-08-21 09:26:42 +00001906 for(i = 0; i < CPU_TLB_SIZE; i++)
bellard84b7b8e2005-11-28 21:19:04 +00001907 tlb_update_dirty(&env->tlb_table[1][i]);
j_mayer6fa4cea2007-04-05 06:43:27 +00001908#if (NB_MMU_MODES >= 3)
1909 for(i = 0; i < CPU_TLB_SIZE; i++)
1910 tlb_update_dirty(&env->tlb_table[2][i]);
1911#if (NB_MMU_MODES == 4)
1912 for(i = 0; i < CPU_TLB_SIZE; i++)
1913 tlb_update_dirty(&env->tlb_table[3][i]);
1914#endif
1915#endif
bellard3a7d9292005-08-21 09:26:42 +00001916}
1917
pbrook0f459d12008-06-09 00:20:13 +00001918static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001919{
pbrook0f459d12008-06-09 00:20:13 +00001920 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
1921 tlb_entry->addr_write = vaddr;
bellard1ccde1c2004-02-06 19:46:14 +00001922}
1923
pbrook0f459d12008-06-09 00:20:13 +00001924/* update the TLB corresponding to virtual page vaddr
1925 so that it is no longer dirty */
1926static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00001927{
bellard1ccde1c2004-02-06 19:46:14 +00001928 int i;
1929
pbrook0f459d12008-06-09 00:20:13 +00001930 vaddr &= TARGET_PAGE_MASK;
bellard1ccde1c2004-02-06 19:46:14 +00001931 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
pbrook0f459d12008-06-09 00:20:13 +00001932 tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
1933 tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001934#if (NB_MMU_MODES >= 3)
pbrook0f459d12008-06-09 00:20:13 +00001935 tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001936#if (NB_MMU_MODES == 4)
pbrook0f459d12008-06-09 00:20:13 +00001937 tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
j_mayer6fa4cea2007-04-05 06:43:27 +00001938#endif
1939#endif
bellard9fa3e852004-01-04 18:06:42 +00001940}
1941
bellard59817cc2004-02-16 22:01:13 +00001942/* add a new TLB entry. At most one entry for a given virtual address
1943 is permitted. Return 0 if OK or 2 if the page could not be mapped
1944 (can only happen in non SOFTMMU mode for I/O pages or pages
1945 conflicting with the host address space). */
ths5fafdf22007-09-16 21:08:06 +00001946int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
1947 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00001948 int mmu_idx, int is_softmmu)
bellard9fa3e852004-01-04 18:06:42 +00001949{
bellard92e873b2004-05-21 14:52:29 +00001950 PhysPageDesc *p;
bellard4f2ac232004-04-26 19:44:02 +00001951 unsigned long pd;
bellard9fa3e852004-01-04 18:06:42 +00001952 unsigned int index;
bellard4f2ac232004-04-26 19:44:02 +00001953 target_ulong address;
pbrook0f459d12008-06-09 00:20:13 +00001954 target_ulong code_address;
bellard108c49b2005-07-24 12:55:09 +00001955 target_phys_addr_t addend;
bellard9fa3e852004-01-04 18:06:42 +00001956 int ret;
bellard84b7b8e2005-11-28 21:19:04 +00001957 CPUTLBEntry *te;
aliguoria1d1bb32008-11-18 20:07:32 +00001958 CPUWatchpoint *wp;
pbrook0f459d12008-06-09 00:20:13 +00001959 target_phys_addr_t iotlb;
bellard9fa3e852004-01-04 18:06:42 +00001960
bellard92e873b2004-05-21 14:52:29 +00001961 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00001962 if (!p) {
1963 pd = IO_MEM_UNASSIGNED;
bellard9fa3e852004-01-04 18:06:42 +00001964 } else {
1965 pd = p->phys_offset;
bellard9fa3e852004-01-04 18:06:42 +00001966 }
1967#if defined(DEBUG_TLB)
j_mayer6ebbf392007-10-14 07:07:08 +00001968 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
1969 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
bellard9fa3e852004-01-04 18:06:42 +00001970#endif
1971
1972 ret = 0;
pbrook0f459d12008-06-09 00:20:13 +00001973 address = vaddr;
1974 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
1975 /* IO memory case (romd handled later) */
1976 address |= TLB_MMIO;
1977 }
1978 addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
1979 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
1980 /* Normal RAM. */
1981 iotlb = pd & TARGET_PAGE_MASK;
1982 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
1983 iotlb |= IO_MEM_NOTDIRTY;
1984 else
1985 iotlb |= IO_MEM_ROM;
1986 } else {
1987 /* IO handlers are currently passed a phsical address.
1988 It would be nice to pass an offset from the base address
1989 of that region. This would avoid having to special case RAM,
1990 and avoid full address decoding in every device.
1991 We can't use the high bits of pd for this because
1992 IO_MEM_ROMD uses these as a ram address. */
pbrook8da3ff12008-12-01 18:59:50 +00001993 iotlb = (pd & ~TARGET_PAGE_MASK);
1994 if (p) {
pbrook8da3ff12008-12-01 18:59:50 +00001995 iotlb += p->region_offset;
1996 } else {
1997 iotlb += paddr;
1998 }
pbrook0f459d12008-06-09 00:20:13 +00001999 }
pbrook6658ffb2007-03-16 23:58:11 +00002000
pbrook0f459d12008-06-09 00:20:13 +00002001 code_address = address;
2002 /* Make accesses to pages with watchpoints go via the
2003 watchpoint trap routines. */
aliguoric0ce9982008-11-25 22:13:57 +00002004 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00002005 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
pbrook0f459d12008-06-09 00:20:13 +00002006 iotlb = io_mem_watch + paddr;
2007 /* TODO: The memory case can be optimized by not trapping
2008 reads of pages with a write breakpoint. */
2009 address |= TLB_MMIO;
pbrook6658ffb2007-03-16 23:58:11 +00002010 }
pbrook0f459d12008-06-09 00:20:13 +00002011 }
balrogd79acba2007-06-26 20:01:13 +00002012
pbrook0f459d12008-06-09 00:20:13 +00002013 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2014 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2015 te = &env->tlb_table[mmu_idx][index];
2016 te->addend = addend - vaddr;
2017 if (prot & PAGE_READ) {
2018 te->addr_read = address;
2019 } else {
2020 te->addr_read = -1;
2021 }
edgar_igl5c751e92008-05-06 08:44:21 +00002022
pbrook0f459d12008-06-09 00:20:13 +00002023 if (prot & PAGE_EXEC) {
2024 te->addr_code = code_address;
2025 } else {
2026 te->addr_code = -1;
2027 }
2028 if (prot & PAGE_WRITE) {
2029 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2030 (pd & IO_MEM_ROMD)) {
2031 /* Write access calls the I/O callback. */
2032 te->addr_write = address | TLB_MMIO;
2033 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2034 !cpu_physical_memory_is_dirty(pd)) {
2035 te->addr_write = address | TLB_NOTDIRTY;
bellard84b7b8e2005-11-28 21:19:04 +00002036 } else {
pbrook0f459d12008-06-09 00:20:13 +00002037 te->addr_write = address;
bellard9fa3e852004-01-04 18:06:42 +00002038 }
pbrook0f459d12008-06-09 00:20:13 +00002039 } else {
2040 te->addr_write = -1;
bellard9fa3e852004-01-04 18:06:42 +00002041 }
bellard9fa3e852004-01-04 18:06:42 +00002042 return ret;
2043}
2044
bellard01243112004-01-04 15:48:17 +00002045#else
2046
bellardee8b7022004-02-03 23:35:10 +00002047void tlb_flush(CPUState *env, int flush_global)
bellard01243112004-01-04 15:48:17 +00002048{
2049}
2050
bellard2e126692004-04-25 21:28:44 +00002051void tlb_flush_page(CPUState *env, target_ulong addr)
bellard01243112004-01-04 15:48:17 +00002052{
2053}
2054
ths5fafdf22007-09-16 21:08:06 +00002055int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
2056 target_phys_addr_t paddr, int prot,
j_mayer6ebbf392007-10-14 07:07:08 +00002057 int mmu_idx, int is_softmmu)
bellard33417e72003-08-10 21:47:01 +00002058{
bellard9fa3e852004-01-04 18:06:42 +00002059 return 0;
2060}
bellard33417e72003-08-10 21:47:01 +00002061
bellard9fa3e852004-01-04 18:06:42 +00002062/* dump memory mappings */
2063void page_dump(FILE *f)
2064{
2065 unsigned long start, end;
2066 int i, j, prot, prot1;
2067 PageDesc *p;
2068
2069 fprintf(f, "%-8s %-8s %-8s %s\n",
2070 "start", "end", "size", "prot");
2071 start = -1;
2072 end = -1;
2073 prot = 0;
2074 for(i = 0; i <= L1_SIZE; i++) {
2075 if (i < L1_SIZE)
2076 p = l1_map[i];
2077 else
2078 p = NULL;
2079 for(j = 0;j < L2_SIZE; j++) {
2080 if (!p)
2081 prot1 = 0;
2082 else
2083 prot1 = p[j].flags;
2084 if (prot1 != prot) {
2085 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
2086 if (start != -1) {
2087 fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
ths5fafdf22007-09-16 21:08:06 +00002088 start, end, end - start,
bellard9fa3e852004-01-04 18:06:42 +00002089 prot & PAGE_READ ? 'r' : '-',
2090 prot & PAGE_WRITE ? 'w' : '-',
2091 prot & PAGE_EXEC ? 'x' : '-');
2092 }
2093 if (prot1 != 0)
2094 start = end;
2095 else
2096 start = -1;
2097 prot = prot1;
2098 }
2099 if (!p)
2100 break;
2101 }
bellard33417e72003-08-10 21:47:01 +00002102 }
bellard33417e72003-08-10 21:47:01 +00002103}
2104
pbrook53a59602006-03-25 19:31:22 +00002105int page_get_flags(target_ulong address)
bellard33417e72003-08-10 21:47:01 +00002106{
bellard9fa3e852004-01-04 18:06:42 +00002107 PageDesc *p;
2108
2109 p = page_find(address >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002110 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00002111 return 0;
2112 return p->flags;
bellard33417e72003-08-10 21:47:01 +00002113}
2114
bellard9fa3e852004-01-04 18:06:42 +00002115/* modify the flags of a page and invalidate the code if
2116 necessary. The flag PAGE_WRITE_ORG is positionned automatically
2117 depending on PAGE_WRITE */
pbrook53a59602006-03-25 19:31:22 +00002118void page_set_flags(target_ulong start, target_ulong end, int flags)
bellard9fa3e852004-01-04 18:06:42 +00002119{
2120 PageDesc *p;
pbrook53a59602006-03-25 19:31:22 +00002121 target_ulong addr;
bellard9fa3e852004-01-04 18:06:42 +00002122
pbrookc8a706f2008-06-02 16:16:42 +00002123 /* mmap_lock should already be held. */
bellard9fa3e852004-01-04 18:06:42 +00002124 start = start & TARGET_PAGE_MASK;
2125 end = TARGET_PAGE_ALIGN(end);
2126 if (flags & PAGE_WRITE)
2127 flags |= PAGE_WRITE_ORG;
bellard9fa3e852004-01-04 18:06:42 +00002128 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2129 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
pbrook17e23772008-06-09 13:47:45 +00002130 /* We may be called for host regions that are outside guest
2131 address space. */
2132 if (!p)
2133 return;
bellard9fa3e852004-01-04 18:06:42 +00002134 /* if the write protection is set, then we invalidate the code
2135 inside */
ths5fafdf22007-09-16 21:08:06 +00002136 if (!(p->flags & PAGE_WRITE) &&
bellard9fa3e852004-01-04 18:06:42 +00002137 (flags & PAGE_WRITE) &&
2138 p->first_tb) {
bellardd720b932004-04-25 17:57:43 +00002139 tb_invalidate_phys_page(addr, 0, NULL);
bellard9fa3e852004-01-04 18:06:42 +00002140 }
2141 p->flags = flags;
2142 }
bellard9fa3e852004-01-04 18:06:42 +00002143}
2144
ths3d97b402007-11-02 19:02:07 +00002145int page_check_range(target_ulong start, target_ulong len, int flags)
2146{
2147 PageDesc *p;
2148 target_ulong end;
2149 target_ulong addr;
2150
balrog55f280c2008-10-28 10:24:11 +00002151 if (start + len < start)
2152 /* we've wrapped around */
2153 return -1;
2154
ths3d97b402007-11-02 19:02:07 +00002155 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2156 start = start & TARGET_PAGE_MASK;
2157
ths3d97b402007-11-02 19:02:07 +00002158 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2159 p = page_find(addr >> TARGET_PAGE_BITS);
2160 if( !p )
2161 return -1;
2162 if( !(p->flags & PAGE_VALID) )
2163 return -1;
2164
bellarddae32702007-11-14 10:51:00 +00002165 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
ths3d97b402007-11-02 19:02:07 +00002166 return -1;
bellarddae32702007-11-14 10:51:00 +00002167 if (flags & PAGE_WRITE) {
2168 if (!(p->flags & PAGE_WRITE_ORG))
2169 return -1;
2170 /* unprotect the page if it was put read-only because it
2171 contains translated code */
2172 if (!(p->flags & PAGE_WRITE)) {
2173 if (!page_unprotect(addr, 0, NULL))
2174 return -1;
2175 }
2176 return 0;
2177 }
ths3d97b402007-11-02 19:02:07 +00002178 }
2179 return 0;
2180}
2181
bellard9fa3e852004-01-04 18:06:42 +00002182/* called from signal handler: invalidate the code and unprotect the
2183 page. Return TRUE if the fault was succesfully handled. */
pbrook53a59602006-03-25 19:31:22 +00002184int page_unprotect(target_ulong address, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00002185{
2186 unsigned int page_index, prot, pindex;
2187 PageDesc *p, *p1;
pbrook53a59602006-03-25 19:31:22 +00002188 target_ulong host_start, host_end, addr;
bellard9fa3e852004-01-04 18:06:42 +00002189
pbrookc8a706f2008-06-02 16:16:42 +00002190 /* Technically this isn't safe inside a signal handler. However we
2191 know this only ever happens in a synchronous SEGV handler, so in
2192 practice it seems to be ok. */
2193 mmap_lock();
2194
bellard83fb7ad2004-07-05 21:25:26 +00002195 host_start = address & qemu_host_page_mask;
bellard9fa3e852004-01-04 18:06:42 +00002196 page_index = host_start >> TARGET_PAGE_BITS;
2197 p1 = page_find(page_index);
pbrookc8a706f2008-06-02 16:16:42 +00002198 if (!p1) {
2199 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002200 return 0;
pbrookc8a706f2008-06-02 16:16:42 +00002201 }
bellard83fb7ad2004-07-05 21:25:26 +00002202 host_end = host_start + qemu_host_page_size;
bellard9fa3e852004-01-04 18:06:42 +00002203 p = p1;
2204 prot = 0;
2205 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2206 prot |= p->flags;
2207 p++;
2208 }
2209 /* if the page was really writable, then we change its
2210 protection back to writable */
2211 if (prot & PAGE_WRITE_ORG) {
2212 pindex = (address - host_start) >> TARGET_PAGE_BITS;
2213 if (!(p1[pindex].flags & PAGE_WRITE)) {
ths5fafdf22007-09-16 21:08:06 +00002214 mprotect((void *)g2h(host_start), qemu_host_page_size,
bellard9fa3e852004-01-04 18:06:42 +00002215 (prot & PAGE_BITS) | PAGE_WRITE);
2216 p1[pindex].flags |= PAGE_WRITE;
2217 /* and since the content will be modified, we must invalidate
2218 the corresponding translated code. */
bellardd720b932004-04-25 17:57:43 +00002219 tb_invalidate_phys_page(address, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00002220#ifdef DEBUG_TB_CHECK
2221 tb_invalidate_check(address);
2222#endif
pbrookc8a706f2008-06-02 16:16:42 +00002223 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002224 return 1;
2225 }
2226 }
pbrookc8a706f2008-06-02 16:16:42 +00002227 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002228 return 0;
2229}
2230
bellard6a00d602005-11-21 23:25:50 +00002231static inline void tlb_set_dirty(CPUState *env,
2232 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002233{
2234}
bellard9fa3e852004-01-04 18:06:42 +00002235#endif /* defined(CONFIG_USER_ONLY) */
2236
pbrooke2eef172008-06-08 01:09:01 +00002237#if !defined(CONFIG_USER_ONLY)
pbrook8da3ff12008-12-01 18:59:50 +00002238
blueswir1db7b5422007-05-26 17:36:03 +00002239static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
pbrook8da3ff12008-12-01 18:59:50 +00002240 ram_addr_t memory, ram_addr_t region_offset);
aurel3200f82b82008-04-27 21:12:55 +00002241static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
pbrook8da3ff12008-12-01 18:59:50 +00002242 ram_addr_t orig_memory, ram_addr_t region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002243#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2244 need_subpage) \
2245 do { \
2246 if (addr > start_addr) \
2247 start_addr2 = 0; \
2248 else { \
2249 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2250 if (start_addr2 > 0) \
2251 need_subpage = 1; \
2252 } \
2253 \
blueswir149e9fba2007-05-30 17:25:06 +00002254 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
blueswir1db7b5422007-05-26 17:36:03 +00002255 end_addr2 = TARGET_PAGE_SIZE - 1; \
2256 else { \
2257 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2258 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2259 need_subpage = 1; \
2260 } \
2261 } while (0)
2262
bellard33417e72003-08-10 21:47:01 +00002263/* register physical memory. 'size' must be a multiple of the target
2264 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
pbrook8da3ff12008-12-01 18:59:50 +00002265 io memory page. The address used when calling the IO function is
2266 the offset from the start of the region, plus region_offset. Both
2267 start_region and regon_offset are rounded down to a page boundary
2268 before calculating this offset. This should not be a problem unless
2269 the low bits of start_addr and region_offset differ. */
2270void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
2271 ram_addr_t size,
2272 ram_addr_t phys_offset,
2273 ram_addr_t region_offset)
bellard33417e72003-08-10 21:47:01 +00002274{
bellard108c49b2005-07-24 12:55:09 +00002275 target_phys_addr_t addr, end_addr;
bellard92e873b2004-05-21 14:52:29 +00002276 PhysPageDesc *p;
bellard9d420372006-06-25 22:25:22 +00002277 CPUState *env;
aurel3200f82b82008-04-27 21:12:55 +00002278 ram_addr_t orig_size = size;
blueswir1db7b5422007-05-26 17:36:03 +00002279 void *subpage;
bellard33417e72003-08-10 21:47:01 +00002280
bellardda260242008-05-30 20:48:25 +00002281#ifdef USE_KQEMU
2282 /* XXX: should not depend on cpu context */
2283 env = first_cpu;
2284 if (env->kqemu_enabled) {
2285 kqemu_set_phys_mem(start_addr, size, phys_offset);
2286 }
2287#endif
aliguori7ba1e612008-11-05 16:04:33 +00002288 if (kvm_enabled())
2289 kvm_set_phys_mem(start_addr, size, phys_offset);
2290
pbrook8da3ff12008-12-01 18:59:50 +00002291 region_offset &= TARGET_PAGE_MASK;
bellard5fd386f2004-05-23 21:11:22 +00002292 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
blueswir149e9fba2007-05-30 17:25:06 +00002293 end_addr = start_addr + (target_phys_addr_t)size;
2294 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
blueswir1db7b5422007-05-26 17:36:03 +00002295 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2296 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
aurel3200f82b82008-04-27 21:12:55 +00002297 ram_addr_t orig_memory = p->phys_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002298 target_phys_addr_t start_addr2, end_addr2;
2299 int need_subpage = 0;
2300
2301 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2302 need_subpage);
blueswir14254fab2008-01-01 16:57:19 +00002303 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002304 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2305 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002306 &p->phys_offset, orig_memory,
2307 p->region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002308 } else {
2309 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2310 >> IO_MEM_SHIFT];
2311 }
pbrook8da3ff12008-12-01 18:59:50 +00002312 subpage_register(subpage, start_addr2, end_addr2, phys_offset,
2313 region_offset);
2314 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002315 } else {
2316 p->phys_offset = phys_offset;
2317 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2318 (phys_offset & IO_MEM_ROMD))
2319 phys_offset += TARGET_PAGE_SIZE;
2320 }
2321 } else {
2322 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2323 p->phys_offset = phys_offset;
pbrook8da3ff12008-12-01 18:59:50 +00002324 p->region_offset = region_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002325 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
pbrook8da3ff12008-12-01 18:59:50 +00002326 (phys_offset & IO_MEM_ROMD)) {
blueswir1db7b5422007-05-26 17:36:03 +00002327 phys_offset += TARGET_PAGE_SIZE;
pbrook0e8f0962008-12-02 09:02:15 +00002328 } else {
blueswir1db7b5422007-05-26 17:36:03 +00002329 target_phys_addr_t start_addr2, end_addr2;
2330 int need_subpage = 0;
2331
2332 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2333 end_addr2, need_subpage);
2334
blueswir14254fab2008-01-01 16:57:19 +00002335 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
blueswir1db7b5422007-05-26 17:36:03 +00002336 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002337 &p->phys_offset, IO_MEM_UNASSIGNED,
2338 0);
blueswir1db7b5422007-05-26 17:36:03 +00002339 subpage_register(subpage, start_addr2, end_addr2,
pbrook8da3ff12008-12-01 18:59:50 +00002340 phys_offset, region_offset);
2341 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002342 }
2343 }
2344 }
pbrook8da3ff12008-12-01 18:59:50 +00002345 region_offset += TARGET_PAGE_SIZE;
bellard33417e72003-08-10 21:47:01 +00002346 }
ths3b46e622007-09-17 08:09:54 +00002347
bellard9d420372006-06-25 22:25:22 +00002348 /* since each CPU stores ram addresses in its TLB cache, we must
2349 reset the modified entries */
2350 /* XXX: slow ! */
2351 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2352 tlb_flush(env, 1);
2353 }
bellard33417e72003-08-10 21:47:01 +00002354}
2355
bellardba863452006-09-24 18:41:10 +00002356/* XXX: temporary until new memory mapping API */
aurel3200f82b82008-04-27 21:12:55 +00002357ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
bellardba863452006-09-24 18:41:10 +00002358{
2359 PhysPageDesc *p;
2360
2361 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2362 if (!p)
2363 return IO_MEM_UNASSIGNED;
2364 return p->phys_offset;
2365}
2366
aliguorif65ed4c2008-12-09 20:09:57 +00002367void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2368{
2369 if (kvm_enabled())
2370 kvm_coalesce_mmio_region(addr, size);
2371}
2372
2373void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2374{
2375 if (kvm_enabled())
2376 kvm_uncoalesce_mmio_region(addr, size);
2377}
2378
bellarde9a1ab12007-02-08 23:08:38 +00002379/* XXX: better than nothing */
aurel3200f82b82008-04-27 21:12:55 +00002380ram_addr_t qemu_ram_alloc(ram_addr_t size)
bellarde9a1ab12007-02-08 23:08:38 +00002381{
2382 ram_addr_t addr;
balrog7fb4fdc2008-04-24 17:59:27 +00002383 if ((phys_ram_alloc_offset + size) > phys_ram_size) {
ths012a7042008-10-02 17:34:21 +00002384 fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
bellarded441462008-05-23 11:56:45 +00002385 (uint64_t)size, (uint64_t)phys_ram_size);
bellarde9a1ab12007-02-08 23:08:38 +00002386 abort();
2387 }
2388 addr = phys_ram_alloc_offset;
2389 phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
2390 return addr;
2391}
2392
2393void qemu_ram_free(ram_addr_t addr)
2394{
2395}
2396
bellarda4193c82004-06-03 14:01:43 +00002397static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
bellard33417e72003-08-10 21:47:01 +00002398{
pbrook67d3b952006-12-18 05:03:52 +00002399#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002400 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
pbrook67d3b952006-12-18 05:03:52 +00002401#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002402#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002403 do_unassigned_access(addr, 0, 0, 0, 1);
2404#endif
2405 return 0;
2406}
2407
2408static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2409{
2410#ifdef DEBUG_UNASSIGNED
2411 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2412#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002413#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002414 do_unassigned_access(addr, 0, 0, 0, 2);
2415#endif
2416 return 0;
2417}
2418
2419static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2420{
2421#ifdef DEBUG_UNASSIGNED
2422 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2423#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002424#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002425 do_unassigned_access(addr, 0, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002426#endif
bellard33417e72003-08-10 21:47:01 +00002427 return 0;
2428}
2429
bellarda4193c82004-06-03 14:01:43 +00002430static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard33417e72003-08-10 21:47:01 +00002431{
pbrook67d3b952006-12-18 05:03:52 +00002432#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002433 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
pbrook67d3b952006-12-18 05:03:52 +00002434#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002435#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002436 do_unassigned_access(addr, 1, 0, 0, 1);
2437#endif
2438}
2439
2440static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2441{
2442#ifdef DEBUG_UNASSIGNED
2443 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2444#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002445#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002446 do_unassigned_access(addr, 1, 0, 0, 2);
2447#endif
2448}
2449
2450static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2451{
2452#ifdef DEBUG_UNASSIGNED
2453 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2454#endif
edgar_igl0a6f8a62008-12-29 14:39:57 +00002455#if defined(TARGET_SPARC)
blueswir1e18231a2008-10-06 18:46:28 +00002456 do_unassigned_access(addr, 1, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002457#endif
bellard33417e72003-08-10 21:47:01 +00002458}
2459
2460static CPUReadMemoryFunc *unassigned_mem_read[3] = {
2461 unassigned_mem_readb,
blueswir1e18231a2008-10-06 18:46:28 +00002462 unassigned_mem_readw,
2463 unassigned_mem_readl,
bellard33417e72003-08-10 21:47:01 +00002464};
2465
2466static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
2467 unassigned_mem_writeb,
blueswir1e18231a2008-10-06 18:46:28 +00002468 unassigned_mem_writew,
2469 unassigned_mem_writel,
bellard33417e72003-08-10 21:47:01 +00002470};
2471
pbrook0f459d12008-06-09 00:20:13 +00002472static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
2473 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002474{
bellard3a7d9292005-08-21 09:26:42 +00002475 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002476 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2477 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2478#if !defined(CONFIG_USER_ONLY)
2479 tb_invalidate_phys_page_fast(ram_addr, 1);
2480 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2481#endif
2482 }
pbrook0f459d12008-06-09 00:20:13 +00002483 stb_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002484#ifdef USE_KQEMU
2485 if (cpu_single_env->kqemu_enabled &&
2486 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2487 kqemu_modify_page(cpu_single_env, ram_addr);
2488#endif
bellardf23db162005-08-21 19:12:28 +00002489 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2490 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2491 /* we remove the notdirty callback only if the code has been
2492 flushed */
2493 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002494 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002495}
2496
pbrook0f459d12008-06-09 00:20:13 +00002497static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
2498 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002499{
bellard3a7d9292005-08-21 09:26:42 +00002500 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002501 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2502 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2503#if !defined(CONFIG_USER_ONLY)
2504 tb_invalidate_phys_page_fast(ram_addr, 2);
2505 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2506#endif
2507 }
pbrook0f459d12008-06-09 00:20:13 +00002508 stw_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002509#ifdef USE_KQEMU
2510 if (cpu_single_env->kqemu_enabled &&
2511 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2512 kqemu_modify_page(cpu_single_env, ram_addr);
2513#endif
bellardf23db162005-08-21 19:12:28 +00002514 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2515 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2516 /* we remove the notdirty callback only if the code has been
2517 flushed */
2518 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002519 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002520}
2521
pbrook0f459d12008-06-09 00:20:13 +00002522static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
2523 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00002524{
bellard3a7d9292005-08-21 09:26:42 +00002525 int dirty_flags;
bellard3a7d9292005-08-21 09:26:42 +00002526 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2527 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
2528#if !defined(CONFIG_USER_ONLY)
2529 tb_invalidate_phys_page_fast(ram_addr, 4);
2530 dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
2531#endif
2532 }
pbrook0f459d12008-06-09 00:20:13 +00002533 stl_p(phys_ram_base + ram_addr, val);
bellardf32fc642006-02-08 22:43:39 +00002534#ifdef USE_KQEMU
2535 if (cpu_single_env->kqemu_enabled &&
2536 (dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
2537 kqemu_modify_page(cpu_single_env, ram_addr);
2538#endif
bellardf23db162005-08-21 19:12:28 +00002539 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
2540 phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
2541 /* we remove the notdirty callback only if the code has been
2542 flushed */
2543 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00002544 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00002545}
2546
bellard3a7d9292005-08-21 09:26:42 +00002547static CPUReadMemoryFunc *error_mem_read[3] = {
2548 NULL, /* never used */
2549 NULL, /* never used */
2550 NULL, /* never used */
2551};
2552
bellard1ccde1c2004-02-06 19:46:14 +00002553static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
2554 notdirty_mem_writeb,
2555 notdirty_mem_writew,
2556 notdirty_mem_writel,
2557};
2558
pbrook0f459d12008-06-09 00:20:13 +00002559/* Generate a debug exception if a watchpoint has been hit. */
aliguorib4051332008-11-18 20:14:20 +00002560static void check_watchpoint(int offset, int len_mask, int flags)
pbrook0f459d12008-06-09 00:20:13 +00002561{
2562 CPUState *env = cpu_single_env;
aliguori06d55cc2008-11-18 20:24:06 +00002563 target_ulong pc, cs_base;
2564 TranslationBlock *tb;
pbrook0f459d12008-06-09 00:20:13 +00002565 target_ulong vaddr;
aliguoria1d1bb32008-11-18 20:07:32 +00002566 CPUWatchpoint *wp;
aliguori06d55cc2008-11-18 20:24:06 +00002567 int cpu_flags;
pbrook0f459d12008-06-09 00:20:13 +00002568
aliguori06d55cc2008-11-18 20:24:06 +00002569 if (env->watchpoint_hit) {
2570 /* We re-entered the check after replacing the TB. Now raise
2571 * the debug interrupt so that is will trigger after the
2572 * current instruction. */
2573 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
2574 return;
2575 }
pbrook2e70f6e2008-06-29 01:03:05 +00002576 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
aliguoric0ce9982008-11-25 22:13:57 +00002577 TAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00002578 if ((vaddr == (wp->vaddr & len_mask) ||
2579 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
aliguori6e140f22008-11-18 20:37:55 +00002580 wp->flags |= BP_WATCHPOINT_HIT;
2581 if (!env->watchpoint_hit) {
2582 env->watchpoint_hit = wp;
2583 tb = tb_find_pc(env->mem_io_pc);
2584 if (!tb) {
2585 cpu_abort(env, "check_watchpoint: could not find TB for "
2586 "pc=%p", (void *)env->mem_io_pc);
2587 }
2588 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
2589 tb_phys_invalidate(tb, -1);
2590 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2591 env->exception_index = EXCP_DEBUG;
2592 } else {
2593 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
2594 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
2595 }
2596 cpu_resume_from_signal(env, NULL);
aliguori06d55cc2008-11-18 20:24:06 +00002597 }
aliguori6e140f22008-11-18 20:37:55 +00002598 } else {
2599 wp->flags &= ~BP_WATCHPOINT_HIT;
pbrook0f459d12008-06-09 00:20:13 +00002600 }
2601 }
2602}
2603
pbrook6658ffb2007-03-16 23:58:11 +00002604/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2605 so these check for a hit then pass through to the normal out-of-line
2606 phys routines. */
2607static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2608{
aliguorib4051332008-11-18 20:14:20 +00002609 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002610 return ldub_phys(addr);
2611}
2612
2613static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2614{
aliguorib4051332008-11-18 20:14:20 +00002615 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002616 return lduw_phys(addr);
2617}
2618
2619static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2620{
aliguorib4051332008-11-18 20:14:20 +00002621 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00002622 return ldl_phys(addr);
2623}
2624
pbrook6658ffb2007-03-16 23:58:11 +00002625static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2626 uint32_t val)
2627{
aliguorib4051332008-11-18 20:14:20 +00002628 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002629 stb_phys(addr, val);
2630}
2631
2632static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2633 uint32_t val)
2634{
aliguorib4051332008-11-18 20:14:20 +00002635 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002636 stw_phys(addr, val);
2637}
2638
2639static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2640 uint32_t val)
2641{
aliguorib4051332008-11-18 20:14:20 +00002642 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00002643 stl_phys(addr, val);
2644}
2645
2646static CPUReadMemoryFunc *watch_mem_read[3] = {
2647 watch_mem_readb,
2648 watch_mem_readw,
2649 watch_mem_readl,
2650};
2651
2652static CPUWriteMemoryFunc *watch_mem_write[3] = {
2653 watch_mem_writeb,
2654 watch_mem_writew,
2655 watch_mem_writel,
2656};
pbrook6658ffb2007-03-16 23:58:11 +00002657
blueswir1db7b5422007-05-26 17:36:03 +00002658static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2659 unsigned int len)
2660{
blueswir1db7b5422007-05-26 17:36:03 +00002661 uint32_t ret;
2662 unsigned int idx;
2663
pbrook8da3ff12008-12-01 18:59:50 +00002664 idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00002665#if defined(DEBUG_SUBPAGE)
2666 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2667 mmio, len, addr, idx);
2668#endif
pbrook8da3ff12008-12-01 18:59:50 +00002669 ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
2670 addr + mmio->region_offset[idx][0][len]);
blueswir1db7b5422007-05-26 17:36:03 +00002671
2672 return ret;
2673}
2674
2675static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2676 uint32_t value, unsigned int len)
2677{
blueswir1db7b5422007-05-26 17:36:03 +00002678 unsigned int idx;
2679
pbrook8da3ff12008-12-01 18:59:50 +00002680 idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00002681#if defined(DEBUG_SUBPAGE)
2682 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2683 mmio, len, addr, idx, value);
2684#endif
pbrook8da3ff12008-12-01 18:59:50 +00002685 (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
2686 addr + mmio->region_offset[idx][1][len],
2687 value);
blueswir1db7b5422007-05-26 17:36:03 +00002688}
2689
2690static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2691{
2692#if defined(DEBUG_SUBPAGE)
2693 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2694#endif
2695
2696 return subpage_readlen(opaque, addr, 0);
2697}
2698
2699static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2700 uint32_t value)
2701{
2702#if defined(DEBUG_SUBPAGE)
2703 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2704#endif
2705 subpage_writelen(opaque, addr, value, 0);
2706}
2707
2708static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2709{
2710#if defined(DEBUG_SUBPAGE)
2711 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2712#endif
2713
2714 return subpage_readlen(opaque, addr, 1);
2715}
2716
2717static void subpage_writew (void *opaque, target_phys_addr_t addr,
2718 uint32_t value)
2719{
2720#if defined(DEBUG_SUBPAGE)
2721 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2722#endif
2723 subpage_writelen(opaque, addr, value, 1);
2724}
2725
2726static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2727{
2728#if defined(DEBUG_SUBPAGE)
2729 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2730#endif
2731
2732 return subpage_readlen(opaque, addr, 2);
2733}
2734
2735static void subpage_writel (void *opaque,
2736 target_phys_addr_t addr, uint32_t value)
2737{
2738#if defined(DEBUG_SUBPAGE)
2739 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2740#endif
2741 subpage_writelen(opaque, addr, value, 2);
2742}
2743
2744static CPUReadMemoryFunc *subpage_read[] = {
2745 &subpage_readb,
2746 &subpage_readw,
2747 &subpage_readl,
2748};
2749
2750static CPUWriteMemoryFunc *subpage_write[] = {
2751 &subpage_writeb,
2752 &subpage_writew,
2753 &subpage_writel,
2754};
2755
2756static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
pbrook8da3ff12008-12-01 18:59:50 +00002757 ram_addr_t memory, ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00002758{
2759 int idx, eidx;
blueswir14254fab2008-01-01 16:57:19 +00002760 unsigned int i;
blueswir1db7b5422007-05-26 17:36:03 +00002761
2762 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2763 return -1;
2764 idx = SUBPAGE_IDX(start);
2765 eidx = SUBPAGE_IDX(end);
2766#if defined(DEBUG_SUBPAGE)
2767 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
2768 mmio, start, end, idx, eidx, memory);
2769#endif
2770 memory >>= IO_MEM_SHIFT;
2771 for (; idx <= eidx; idx++) {
blueswir14254fab2008-01-01 16:57:19 +00002772 for (i = 0; i < 4; i++) {
blueswir13ee89922008-01-02 19:45:26 +00002773 if (io_mem_read[memory][i]) {
2774 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
2775 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
pbrook8da3ff12008-12-01 18:59:50 +00002776 mmio->region_offset[idx][0][i] = region_offset;
blueswir13ee89922008-01-02 19:45:26 +00002777 }
2778 if (io_mem_write[memory][i]) {
2779 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
2780 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
pbrook8da3ff12008-12-01 18:59:50 +00002781 mmio->region_offset[idx][1][i] = region_offset;
blueswir13ee89922008-01-02 19:45:26 +00002782 }
blueswir14254fab2008-01-01 16:57:19 +00002783 }
blueswir1db7b5422007-05-26 17:36:03 +00002784 }
2785
2786 return 0;
2787}
2788
aurel3200f82b82008-04-27 21:12:55 +00002789static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
pbrook8da3ff12008-12-01 18:59:50 +00002790 ram_addr_t orig_memory, ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00002791{
2792 subpage_t *mmio;
2793 int subpage_memory;
2794
2795 mmio = qemu_mallocz(sizeof(subpage_t));
2796 if (mmio != NULL) {
2797 mmio->base = base;
2798 subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
2799#if defined(DEBUG_SUBPAGE)
2800 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
2801 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
2802#endif
2803 *phys = subpage_memory | IO_MEM_SUBPAGE;
pbrook8da3ff12008-12-01 18:59:50 +00002804 subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
2805 region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002806 }
2807
2808 return mmio;
2809}
2810
bellard33417e72003-08-10 21:47:01 +00002811static void io_mem_init(void)
2812{
bellard3a7d9292005-08-21 09:26:42 +00002813 cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
bellarda4193c82004-06-03 14:01:43 +00002814 cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
bellard3a7d9292005-08-21 09:26:42 +00002815 cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002816 io_mem_nb = 5;
2817
pbrook0f459d12008-06-09 00:20:13 +00002818 io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
pbrook6658ffb2007-03-16 23:58:11 +00002819 watch_mem_write, NULL);
bellard1ccde1c2004-02-06 19:46:14 +00002820 /* alloc dirty bits array */
bellard0a962c02005-02-10 22:00:27 +00002821 phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
bellard3a7d9292005-08-21 09:26:42 +00002822 memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002823}
2824
2825/* mem_read and mem_write are arrays of functions containing the
2826 function to access byte (index 0), word (index 1) and dword (index
blueswir13ee89922008-01-02 19:45:26 +00002827 2). Functions can be omitted with a NULL function pointer. The
2828 registered functions may be modified dynamically later.
2829 If io_index is non zero, the corresponding io zone is
blueswir14254fab2008-01-01 16:57:19 +00002830 modified. If it is zero, a new io zone is allocated. The return
2831 value can be used with cpu_register_physical_memory(). (-1) is
2832 returned if error. */
bellard33417e72003-08-10 21:47:01 +00002833int cpu_register_io_memory(int io_index,
2834 CPUReadMemoryFunc **mem_read,
bellarda4193c82004-06-03 14:01:43 +00002835 CPUWriteMemoryFunc **mem_write,
2836 void *opaque)
bellard33417e72003-08-10 21:47:01 +00002837{
blueswir14254fab2008-01-01 16:57:19 +00002838 int i, subwidth = 0;
bellard33417e72003-08-10 21:47:01 +00002839
2840 if (io_index <= 0) {
bellardb5ff1b32005-11-26 10:38:39 +00002841 if (io_mem_nb >= IO_MEM_NB_ENTRIES)
bellard33417e72003-08-10 21:47:01 +00002842 return -1;
2843 io_index = io_mem_nb++;
2844 } else {
2845 if (io_index >= IO_MEM_NB_ENTRIES)
2846 return -1;
2847 }
bellardb5ff1b32005-11-26 10:38:39 +00002848
bellard33417e72003-08-10 21:47:01 +00002849 for(i = 0;i < 3; i++) {
blueswir14254fab2008-01-01 16:57:19 +00002850 if (!mem_read[i] || !mem_write[i])
2851 subwidth = IO_MEM_SUBWIDTH;
bellard33417e72003-08-10 21:47:01 +00002852 io_mem_read[io_index][i] = mem_read[i];
2853 io_mem_write[io_index][i] = mem_write[i];
2854 }
bellarda4193c82004-06-03 14:01:43 +00002855 io_mem_opaque[io_index] = opaque;
blueswir14254fab2008-01-01 16:57:19 +00002856 return (io_index << IO_MEM_SHIFT) | subwidth;
bellard33417e72003-08-10 21:47:01 +00002857}
bellard61382a52003-10-27 21:22:23 +00002858
bellard8926b512004-10-10 15:14:20 +00002859CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
2860{
2861 return io_mem_write[io_index >> IO_MEM_SHIFT];
2862}
2863
2864CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
2865{
2866 return io_mem_read[io_index >> IO_MEM_SHIFT];
2867}
2868
pbrooke2eef172008-06-08 01:09:01 +00002869#endif /* !defined(CONFIG_USER_ONLY) */
2870
bellard13eb76e2004-01-24 15:23:36 +00002871/* physical memory access (slow version, mainly for debug) */
2872#if defined(CONFIG_USER_ONLY)
ths5fafdf22007-09-16 21:08:06 +00002873void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002874 int len, int is_write)
2875{
2876 int l, flags;
2877 target_ulong page;
pbrook53a59602006-03-25 19:31:22 +00002878 void * p;
bellard13eb76e2004-01-24 15:23:36 +00002879
2880 while (len > 0) {
2881 page = addr & TARGET_PAGE_MASK;
2882 l = (page + TARGET_PAGE_SIZE) - addr;
2883 if (l > len)
2884 l = len;
2885 flags = page_get_flags(page);
2886 if (!(flags & PAGE_VALID))
2887 return;
2888 if (is_write) {
2889 if (!(flags & PAGE_WRITE))
2890 return;
bellard579a97f2007-11-11 14:26:47 +00002891 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002892 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
bellard579a97f2007-11-11 14:26:47 +00002893 /* FIXME - should this return an error rather than just fail? */
2894 return;
aurel3272fb7da2008-04-27 23:53:45 +00002895 memcpy(p, buf, l);
2896 unlock_user(p, addr, l);
bellard13eb76e2004-01-24 15:23:36 +00002897 } else {
2898 if (!(flags & PAGE_READ))
2899 return;
bellard579a97f2007-11-11 14:26:47 +00002900 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00002901 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
bellard579a97f2007-11-11 14:26:47 +00002902 /* FIXME - should this return an error rather than just fail? */
2903 return;
aurel3272fb7da2008-04-27 23:53:45 +00002904 memcpy(buf, p, l);
aurel325b257572008-04-28 08:54:59 +00002905 unlock_user(p, addr, 0);
bellard13eb76e2004-01-24 15:23:36 +00002906 }
2907 len -= l;
2908 buf += l;
2909 addr += l;
2910 }
2911}
bellard8df1cd02005-01-28 22:37:22 +00002912
bellard13eb76e2004-01-24 15:23:36 +00002913#else
ths5fafdf22007-09-16 21:08:06 +00002914void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00002915 int len, int is_write)
2916{
2917 int l, io_index;
2918 uint8_t *ptr;
2919 uint32_t val;
bellard2e126692004-04-25 21:28:44 +00002920 target_phys_addr_t page;
2921 unsigned long pd;
bellard92e873b2004-05-21 14:52:29 +00002922 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00002923
bellard13eb76e2004-01-24 15:23:36 +00002924 while (len > 0) {
2925 page = addr & TARGET_PAGE_MASK;
2926 l = (page + TARGET_PAGE_SIZE) - addr;
2927 if (l > len)
2928 l = len;
bellard92e873b2004-05-21 14:52:29 +00002929 p = phys_page_find(page >> TARGET_PAGE_BITS);
bellard13eb76e2004-01-24 15:23:36 +00002930 if (!p) {
2931 pd = IO_MEM_UNASSIGNED;
2932 } else {
2933 pd = p->phys_offset;
2934 }
ths3b46e622007-09-17 08:09:54 +00002935
bellard13eb76e2004-01-24 15:23:36 +00002936 if (is_write) {
bellard3a7d9292005-08-21 09:26:42 +00002937 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard13eb76e2004-01-24 15:23:36 +00002938 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00002939 if (p)
2940 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard6a00d602005-11-21 23:25:50 +00002941 /* XXX: could force cpu_single_env to NULL to avoid
2942 potential bugs */
bellard13eb76e2004-01-24 15:23:36 +00002943 if (l >= 4 && ((addr & 3) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002944 /* 32 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002945 val = ldl_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002946 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002947 l = 4;
2948 } else if (l >= 2 && ((addr & 1) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00002949 /* 16 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002950 val = lduw_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002951 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002952 l = 2;
2953 } else {
bellard1c213d12005-09-03 10:49:04 +00002954 /* 8 bit write access */
bellardc27004e2005-01-03 23:35:10 +00002955 val = ldub_p(buf);
bellarda4193c82004-06-03 14:01:43 +00002956 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
bellard13eb76e2004-01-24 15:23:36 +00002957 l = 1;
2958 }
2959 } else {
bellardb448f2f2004-02-25 23:24:04 +00002960 unsigned long addr1;
2961 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
bellard13eb76e2004-01-24 15:23:36 +00002962 /* RAM case */
bellardb448f2f2004-02-25 23:24:04 +00002963 ptr = phys_ram_base + addr1;
bellard13eb76e2004-01-24 15:23:36 +00002964 memcpy(ptr, buf, l);
bellard3a7d9292005-08-21 09:26:42 +00002965 if (!cpu_physical_memory_is_dirty(addr1)) {
2966 /* invalidate code */
2967 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
2968 /* set dirty bit */
ths5fafdf22007-09-16 21:08:06 +00002969 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
bellardf23db162005-08-21 19:12:28 +00002970 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00002971 }
bellard13eb76e2004-01-24 15:23:36 +00002972 }
2973 } else {
ths5fafdf22007-09-16 21:08:06 +00002974 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00002975 !(pd & IO_MEM_ROMD)) {
bellard13eb76e2004-01-24 15:23:36 +00002976 /* I/O case */
2977 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00002978 if (p)
2979 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard13eb76e2004-01-24 15:23:36 +00002980 if (l >= 4 && ((addr & 3) == 0)) {
2981 /* 32 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002982 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002983 stl_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002984 l = 4;
2985 } else if (l >= 2 && ((addr & 1) == 0)) {
2986 /* 16 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002987 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002988 stw_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002989 l = 2;
2990 } else {
bellard1c213d12005-09-03 10:49:04 +00002991 /* 8 bit read access */
bellarda4193c82004-06-03 14:01:43 +00002992 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
bellardc27004e2005-01-03 23:35:10 +00002993 stb_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00002994 l = 1;
2995 }
2996 } else {
2997 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00002998 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard13eb76e2004-01-24 15:23:36 +00002999 (addr & ~TARGET_PAGE_MASK);
3000 memcpy(buf, ptr, l);
3001 }
3002 }
3003 len -= l;
3004 buf += l;
3005 addr += l;
3006 }
3007}
bellard8df1cd02005-01-28 22:37:22 +00003008
bellardd0ecd2a2006-04-23 17:14:48 +00003009/* used for ROM loading : can write in RAM and ROM */
ths5fafdf22007-09-16 21:08:06 +00003010void cpu_physical_memory_write_rom(target_phys_addr_t addr,
bellardd0ecd2a2006-04-23 17:14:48 +00003011 const uint8_t *buf, int len)
3012{
3013 int l;
3014 uint8_t *ptr;
3015 target_phys_addr_t page;
3016 unsigned long pd;
3017 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00003018
bellardd0ecd2a2006-04-23 17:14:48 +00003019 while (len > 0) {
3020 page = addr & TARGET_PAGE_MASK;
3021 l = (page + TARGET_PAGE_SIZE) - addr;
3022 if (l > len)
3023 l = len;
3024 p = phys_page_find(page >> TARGET_PAGE_BITS);
3025 if (!p) {
3026 pd = IO_MEM_UNASSIGNED;
3027 } else {
3028 pd = p->phys_offset;
3029 }
ths3b46e622007-09-17 08:09:54 +00003030
bellardd0ecd2a2006-04-23 17:14:48 +00003031 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
bellard2a4188a2006-06-25 21:54:59 +00003032 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3033 !(pd & IO_MEM_ROMD)) {
bellardd0ecd2a2006-04-23 17:14:48 +00003034 /* do nothing */
3035 } else {
3036 unsigned long addr1;
3037 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3038 /* ROM/RAM case */
3039 ptr = phys_ram_base + addr1;
3040 memcpy(ptr, buf, l);
3041 }
3042 len -= l;
3043 buf += l;
3044 addr += l;
3045 }
3046}
3047
aliguori6d16c2f2009-01-22 16:59:11 +00003048typedef struct {
3049 void *buffer;
3050 target_phys_addr_t addr;
3051 target_phys_addr_t len;
3052} BounceBuffer;
3053
3054static BounceBuffer bounce;
3055
aliguoriba223c22009-01-22 16:59:16 +00003056typedef struct MapClient {
3057 void *opaque;
3058 void (*callback)(void *opaque);
3059 LIST_ENTRY(MapClient) link;
3060} MapClient;
3061
3062static LIST_HEAD(map_client_list, MapClient) map_client_list
3063 = LIST_HEAD_INITIALIZER(map_client_list);
3064
3065void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
3066{
3067 MapClient *client = qemu_malloc(sizeof(*client));
3068
3069 client->opaque = opaque;
3070 client->callback = callback;
3071 LIST_INSERT_HEAD(&map_client_list, client, link);
3072 return client;
3073}
3074
3075void cpu_unregister_map_client(void *_client)
3076{
3077 MapClient *client = (MapClient *)_client;
3078
3079 LIST_REMOVE(client, link);
3080}
3081
3082static void cpu_notify_map_clients(void)
3083{
3084 MapClient *client;
3085
3086 while (!LIST_EMPTY(&map_client_list)) {
3087 client = LIST_FIRST(&map_client_list);
3088 client->callback(client->opaque);
3089 LIST_REMOVE(client, link);
3090 }
3091}
3092
aliguori6d16c2f2009-01-22 16:59:11 +00003093/* Map a physical memory region into a host virtual address.
3094 * May map a subset of the requested range, given by and returned in *plen.
3095 * May return NULL if resources needed to perform the mapping are exhausted.
3096 * Use only for reads OR writes - not for read-modify-write operations.
aliguoriba223c22009-01-22 16:59:16 +00003097 * Use cpu_register_map_client() to know when retrying the map operation is
3098 * likely to succeed.
aliguori6d16c2f2009-01-22 16:59:11 +00003099 */
3100void *cpu_physical_memory_map(target_phys_addr_t addr,
3101 target_phys_addr_t *plen,
3102 int is_write)
3103{
3104 target_phys_addr_t len = *plen;
3105 target_phys_addr_t done = 0;
3106 int l;
3107 uint8_t *ret = NULL;
3108 uint8_t *ptr;
3109 target_phys_addr_t page;
3110 unsigned long pd;
3111 PhysPageDesc *p;
3112 unsigned long addr1;
3113
3114 while (len > 0) {
3115 page = addr & TARGET_PAGE_MASK;
3116 l = (page + TARGET_PAGE_SIZE) - addr;
3117 if (l > len)
3118 l = len;
3119 p = phys_page_find(page >> TARGET_PAGE_BITS);
3120 if (!p) {
3121 pd = IO_MEM_UNASSIGNED;
3122 } else {
3123 pd = p->phys_offset;
3124 }
3125
3126 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3127 if (done || bounce.buffer) {
3128 break;
3129 }
3130 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
3131 bounce.addr = addr;
3132 bounce.len = l;
3133 if (!is_write) {
3134 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3135 }
3136 ptr = bounce.buffer;
3137 } else {
3138 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3139 ptr = phys_ram_base + addr1;
3140 }
3141 if (!done) {
3142 ret = ptr;
3143 } else if (ret + done != ptr) {
3144 break;
3145 }
3146
3147 len -= l;
3148 addr += l;
3149 done += l;
3150 }
3151 *plen = done;
3152 return ret;
3153}
3154
3155/* Unmaps a memory region previously mapped by cpu_physical_memory_map().
3156 * Will also mark the memory as dirty if is_write == 1. access_len gives
3157 * the amount of memory that was actually read or written by the caller.
3158 */
3159void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
3160 int is_write, target_phys_addr_t access_len)
3161{
3162 if (buffer != bounce.buffer) {
3163 if (is_write) {
3164 unsigned long addr1 = (uint8_t *)buffer - phys_ram_base;
3165 while (access_len) {
3166 unsigned l;
3167 l = TARGET_PAGE_SIZE;
3168 if (l > access_len)
3169 l = access_len;
3170 if (!cpu_physical_memory_is_dirty(addr1)) {
3171 /* invalidate code */
3172 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3173 /* set dirty bit */
3174 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3175 (0xff & ~CODE_DIRTY_FLAG);
3176 }
3177 addr1 += l;
3178 access_len -= l;
3179 }
3180 }
3181 return;
3182 }
3183 if (is_write) {
3184 cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3185 }
3186 qemu_free(bounce.buffer);
3187 bounce.buffer = NULL;
aliguoriba223c22009-01-22 16:59:16 +00003188 cpu_notify_map_clients();
aliguori6d16c2f2009-01-22 16:59:11 +00003189}
bellardd0ecd2a2006-04-23 17:14:48 +00003190
bellard8df1cd02005-01-28 22:37:22 +00003191/* warning: addr must be aligned */
3192uint32_t ldl_phys(target_phys_addr_t addr)
3193{
3194 int io_index;
3195 uint8_t *ptr;
3196 uint32_t val;
3197 unsigned long pd;
3198 PhysPageDesc *p;
3199
3200 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3201 if (!p) {
3202 pd = IO_MEM_UNASSIGNED;
3203 } else {
3204 pd = p->phys_offset;
3205 }
ths3b46e622007-09-17 08:09:54 +00003206
ths5fafdf22007-09-16 21:08:06 +00003207 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00003208 !(pd & IO_MEM_ROMD)) {
bellard8df1cd02005-01-28 22:37:22 +00003209 /* I/O case */
3210 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003211 if (p)
3212 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003213 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3214 } else {
3215 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003216 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00003217 (addr & ~TARGET_PAGE_MASK);
3218 val = ldl_p(ptr);
3219 }
3220 return val;
3221}
3222
bellard84b7b8e2005-11-28 21:19:04 +00003223/* warning: addr must be aligned */
3224uint64_t ldq_phys(target_phys_addr_t addr)
3225{
3226 int io_index;
3227 uint8_t *ptr;
3228 uint64_t val;
3229 unsigned long pd;
3230 PhysPageDesc *p;
3231
3232 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3233 if (!p) {
3234 pd = IO_MEM_UNASSIGNED;
3235 } else {
3236 pd = p->phys_offset;
3237 }
ths3b46e622007-09-17 08:09:54 +00003238
bellard2a4188a2006-06-25 21:54:59 +00003239 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3240 !(pd & IO_MEM_ROMD)) {
bellard84b7b8e2005-11-28 21:19:04 +00003241 /* I/O case */
3242 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003243 if (p)
3244 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard84b7b8e2005-11-28 21:19:04 +00003245#ifdef TARGET_WORDS_BIGENDIAN
3246 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3247 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3248#else
3249 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3250 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3251#endif
3252 } else {
3253 /* RAM case */
ths5fafdf22007-09-16 21:08:06 +00003254 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
bellard84b7b8e2005-11-28 21:19:04 +00003255 (addr & ~TARGET_PAGE_MASK);
3256 val = ldq_p(ptr);
3257 }
3258 return val;
3259}
3260
bellardaab33092005-10-30 20:48:42 +00003261/* XXX: optimize */
3262uint32_t ldub_phys(target_phys_addr_t addr)
3263{
3264 uint8_t val;
3265 cpu_physical_memory_read(addr, &val, 1);
3266 return val;
3267}
3268
3269/* XXX: optimize */
3270uint32_t lduw_phys(target_phys_addr_t addr)
3271{
3272 uint16_t val;
3273 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3274 return tswap16(val);
3275}
3276
bellard8df1cd02005-01-28 22:37:22 +00003277/* warning: addr must be aligned. The ram page is not masked as dirty
3278 and the code inside is not invalidated. It is useful if the dirty
3279 bits are used to track modified PTEs */
3280void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3281{
3282 int io_index;
3283 uint8_t *ptr;
3284 unsigned long pd;
3285 PhysPageDesc *p;
3286
3287 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3288 if (!p) {
3289 pd = IO_MEM_UNASSIGNED;
3290 } else {
3291 pd = p->phys_offset;
3292 }
ths3b46e622007-09-17 08:09:54 +00003293
bellard3a7d9292005-08-21 09:26:42 +00003294 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003295 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003296 if (p)
3297 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003298 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3299 } else {
aliguori74576192008-10-06 14:02:03 +00003300 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3301 ptr = phys_ram_base + addr1;
bellard8df1cd02005-01-28 22:37:22 +00003302 stl_p(ptr, val);
aliguori74576192008-10-06 14:02:03 +00003303
3304 if (unlikely(in_migration)) {
3305 if (!cpu_physical_memory_is_dirty(addr1)) {
3306 /* invalidate code */
3307 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3308 /* set dirty bit */
3309 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3310 (0xff & ~CODE_DIRTY_FLAG);
3311 }
3312 }
bellard8df1cd02005-01-28 22:37:22 +00003313 }
3314}
3315
j_mayerbc98a7e2007-04-04 07:55:12 +00003316void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3317{
3318 int io_index;
3319 uint8_t *ptr;
3320 unsigned long pd;
3321 PhysPageDesc *p;
3322
3323 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3324 if (!p) {
3325 pd = IO_MEM_UNASSIGNED;
3326 } else {
3327 pd = p->phys_offset;
3328 }
ths3b46e622007-09-17 08:09:54 +00003329
j_mayerbc98a7e2007-04-04 07:55:12 +00003330 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3331 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003332 if (p)
3333 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
j_mayerbc98a7e2007-04-04 07:55:12 +00003334#ifdef TARGET_WORDS_BIGENDIAN
3335 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3336 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3337#else
3338 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3339 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3340#endif
3341 } else {
ths5fafdf22007-09-16 21:08:06 +00003342 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
j_mayerbc98a7e2007-04-04 07:55:12 +00003343 (addr & ~TARGET_PAGE_MASK);
3344 stq_p(ptr, val);
3345 }
3346}
3347
bellard8df1cd02005-01-28 22:37:22 +00003348/* warning: addr must be aligned */
bellard8df1cd02005-01-28 22:37:22 +00003349void stl_phys(target_phys_addr_t addr, uint32_t val)
3350{
3351 int io_index;
3352 uint8_t *ptr;
3353 unsigned long pd;
3354 PhysPageDesc *p;
3355
3356 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3357 if (!p) {
3358 pd = IO_MEM_UNASSIGNED;
3359 } else {
3360 pd = p->phys_offset;
3361 }
ths3b46e622007-09-17 08:09:54 +00003362
bellard3a7d9292005-08-21 09:26:42 +00003363 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003364 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003365 if (p)
3366 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003367 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3368 } else {
3369 unsigned long addr1;
3370 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3371 /* RAM case */
3372 ptr = phys_ram_base + addr1;
3373 stl_p(ptr, val);
bellard3a7d9292005-08-21 09:26:42 +00003374 if (!cpu_physical_memory_is_dirty(addr1)) {
3375 /* invalidate code */
3376 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3377 /* set dirty bit */
bellardf23db162005-08-21 19:12:28 +00003378 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
3379 (0xff & ~CODE_DIRTY_FLAG);
bellard3a7d9292005-08-21 09:26:42 +00003380 }
bellard8df1cd02005-01-28 22:37:22 +00003381 }
3382}
3383
bellardaab33092005-10-30 20:48:42 +00003384/* XXX: optimize */
3385void stb_phys(target_phys_addr_t addr, uint32_t val)
3386{
3387 uint8_t v = val;
3388 cpu_physical_memory_write(addr, &v, 1);
3389}
3390
3391/* XXX: optimize */
3392void stw_phys(target_phys_addr_t addr, uint32_t val)
3393{
3394 uint16_t v = tswap16(val);
3395 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3396}
3397
3398/* XXX: optimize */
3399void stq_phys(target_phys_addr_t addr, uint64_t val)
3400{
3401 val = tswap64(val);
3402 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3403}
3404
bellard13eb76e2004-01-24 15:23:36 +00003405#endif
3406
3407/* virtual memory access for debug */
ths5fafdf22007-09-16 21:08:06 +00003408int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
bellardb448f2f2004-02-25 23:24:04 +00003409 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00003410{
3411 int l;
j_mayer9b3c35e2007-04-07 11:21:28 +00003412 target_phys_addr_t phys_addr;
3413 target_ulong page;
bellard13eb76e2004-01-24 15:23:36 +00003414
3415 while (len > 0) {
3416 page = addr & TARGET_PAGE_MASK;
3417 phys_addr = cpu_get_phys_page_debug(env, page);
3418 /* if no physical page mapped, return an error */
3419 if (phys_addr == -1)
3420 return -1;
3421 l = (page + TARGET_PAGE_SIZE) - addr;
3422 if (l > len)
3423 l = len;
ths5fafdf22007-09-16 21:08:06 +00003424 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
bellardb448f2f2004-02-25 23:24:04 +00003425 buf, l, is_write);
bellard13eb76e2004-01-24 15:23:36 +00003426 len -= l;
3427 buf += l;
3428 addr += l;
3429 }
3430 return 0;
3431}
3432
pbrook2e70f6e2008-06-29 01:03:05 +00003433/* in deterministic execution mode, instructions doing device I/Os
3434 must be at the end of the TB */
3435void cpu_io_recompile(CPUState *env, void *retaddr)
3436{
3437 TranslationBlock *tb;
3438 uint32_t n, cflags;
3439 target_ulong pc, cs_base;
3440 uint64_t flags;
3441
3442 tb = tb_find_pc((unsigned long)retaddr);
3443 if (!tb) {
3444 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
3445 retaddr);
3446 }
3447 n = env->icount_decr.u16.low + tb->icount;
3448 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
3449 /* Calculate how many instructions had been executed before the fault
thsbf20dc02008-06-30 17:22:19 +00003450 occurred. */
pbrook2e70f6e2008-06-29 01:03:05 +00003451 n = n - env->icount_decr.u16.low;
3452 /* Generate a new TB ending on the I/O insn. */
3453 n++;
3454 /* On MIPS and SH, delay slot instructions can only be restarted if
3455 they were already the first instruction in the TB. If this is not
thsbf20dc02008-06-30 17:22:19 +00003456 the first instruction in a TB then re-execute the preceding
pbrook2e70f6e2008-06-29 01:03:05 +00003457 branch. */
3458#if defined(TARGET_MIPS)
3459 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
3460 env->active_tc.PC -= 4;
3461 env->icount_decr.u16.low++;
3462 env->hflags &= ~MIPS_HFLAG_BMASK;
3463 }
3464#elif defined(TARGET_SH4)
3465 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
3466 && n > 1) {
3467 env->pc -= 2;
3468 env->icount_decr.u16.low++;
3469 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
3470 }
3471#endif
3472 /* This should never happen. */
3473 if (n > CF_COUNT_MASK)
3474 cpu_abort(env, "TB too big during recompile");
3475
3476 cflags = n | CF_LAST_IO;
3477 pc = tb->pc;
3478 cs_base = tb->cs_base;
3479 flags = tb->flags;
3480 tb_phys_invalidate(tb, -1);
3481 /* FIXME: In theory this could raise an exception. In practice
3482 we have already translated the block once so it's probably ok. */
3483 tb_gen_code(env, pc, cs_base, flags, cflags);
thsbf20dc02008-06-30 17:22:19 +00003484 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
pbrook2e70f6e2008-06-29 01:03:05 +00003485 the first in the TB) then we end up generating a whole new TB and
3486 repeating the fault, which is horribly inefficient.
3487 Better would be to execute just this insn uncached, or generate a
3488 second new TB. */
3489 cpu_resume_from_signal(env, NULL);
3490}
3491
bellarde3db7222005-01-26 22:00:47 +00003492void dump_exec_info(FILE *f,
3493 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3494{
3495 int i, target_code_size, max_target_code_size;
3496 int direct_jmp_count, direct_jmp2_count, cross_page;
3497 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +00003498
bellarde3db7222005-01-26 22:00:47 +00003499 target_code_size = 0;
3500 max_target_code_size = 0;
3501 cross_page = 0;
3502 direct_jmp_count = 0;
3503 direct_jmp2_count = 0;
3504 for(i = 0; i < nb_tbs; i++) {
3505 tb = &tbs[i];
3506 target_code_size += tb->size;
3507 if (tb->size > max_target_code_size)
3508 max_target_code_size = tb->size;
3509 if (tb->page_addr[1] != -1)
3510 cross_page++;
3511 if (tb->tb_next_offset[0] != 0xffff) {
3512 direct_jmp_count++;
3513 if (tb->tb_next_offset[1] != 0xffff) {
3514 direct_jmp2_count++;
3515 }
3516 }
3517 }
3518 /* XXX: avoid using doubles ? */
bellard57fec1f2008-02-01 10:50:11 +00003519 cpu_fprintf(f, "Translation buffer state:\n");
bellard26a5f132008-05-28 12:30:31 +00003520 cpu_fprintf(f, "gen code size %ld/%ld\n",
3521 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
3522 cpu_fprintf(f, "TB count %d/%d\n",
3523 nb_tbs, code_gen_max_blocks);
ths5fafdf22007-09-16 21:08:06 +00003524 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
bellarde3db7222005-01-26 22:00:47 +00003525 nb_tbs ? target_code_size / nb_tbs : 0,
3526 max_target_code_size);
ths5fafdf22007-09-16 21:08:06 +00003527 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
bellarde3db7222005-01-26 22:00:47 +00003528 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
3529 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
ths5fafdf22007-09-16 21:08:06 +00003530 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
3531 cross_page,
bellarde3db7222005-01-26 22:00:47 +00003532 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
3533 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
ths5fafdf22007-09-16 21:08:06 +00003534 direct_jmp_count,
bellarde3db7222005-01-26 22:00:47 +00003535 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
3536 direct_jmp2_count,
3537 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
bellard57fec1f2008-02-01 10:50:11 +00003538 cpu_fprintf(f, "\nStatistics:\n");
bellarde3db7222005-01-26 22:00:47 +00003539 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
3540 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
3541 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
bellardb67d9a52008-05-23 09:57:34 +00003542 tcg_dump_info(f, cpu_fprintf);
bellarde3db7222005-01-26 22:00:47 +00003543}
3544
ths5fafdf22007-09-16 21:08:06 +00003545#if !defined(CONFIG_USER_ONLY)
bellard61382a52003-10-27 21:22:23 +00003546
3547#define MMUSUFFIX _cmmu
3548#define GETPC() NULL
3549#define env cpu_single_env
bellardb769d8f2004-10-03 15:07:13 +00003550#define SOFTMMU_CODE_ACCESS
bellard61382a52003-10-27 21:22:23 +00003551
3552#define SHIFT 0
3553#include "softmmu_template.h"
3554
3555#define SHIFT 1
3556#include "softmmu_template.h"
3557
3558#define SHIFT 2
3559#include "softmmu_template.h"
3560
3561#define SHIFT 3
3562#include "softmmu_template.h"
3563
3564#undef env
3565
3566#endif