bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 2 | * virtual page mapping and translated block handling |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 18 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 20 | #ifdef _WIN32 |
| 21 | #include <windows.h> |
| 22 | #else |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 23 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 24 | #include <sys/mman.h> |
| 25 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 26 | #include <stdlib.h> |
| 27 | #include <stdio.h> |
| 28 | #include <stdarg.h> |
| 29 | #include <string.h> |
| 30 | #include <errno.h> |
| 31 | #include <unistd.h> |
| 32 | #include <inttypes.h> |
| 33 | |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 34 | #include "cpu.h" |
| 35 | #include "exec-all.h" |
aurel32 | ca10f86 | 2008-04-11 21:35:42 +0000 | [diff] [blame] | 36 | #include "qemu-common.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 37 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 38 | #include "hw/hw.h" |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 39 | #include "hw/qdev.h" |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 40 | #include "osdep.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 41 | #include "kvm.h" |
Blue Swirl | 29e922b | 2010-03-29 19:24:00 +0000 | [diff] [blame] | 42 | #include "qemu-timer.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 43 | #if defined(CONFIG_USER_ONLY) |
| 44 | #include <qemu.h> |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 45 | #include <signal.h> |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 46 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 47 | #include <sys/param.h> |
| 48 | #if __FreeBSD_version >= 700104 |
| 49 | #define HAVE_KINFO_GETVMMAP |
| 50 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ |
| 51 | #include <sys/time.h> |
| 52 | #include <sys/proc.h> |
| 53 | #include <machine/profile.h> |
| 54 | #define _KERNEL |
| 55 | #include <sys/user.h> |
| 56 | #undef _KERNEL |
| 57 | #undef sigqueue |
| 58 | #include <libutil.h> |
| 59 | #endif |
| 60 | #endif |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 61 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 62 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 63 | //#define DEBUG_TB_INVALIDATE |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 64 | //#define DEBUG_FLUSH |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 65 | //#define DEBUG_TLB |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 66 | //#define DEBUG_UNASSIGNED |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 67 | |
| 68 | /* make various TB consistency checks */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 69 | //#define DEBUG_TB_CHECK |
| 70 | //#define DEBUG_TLB_CHECK |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 71 | |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 72 | //#define DEBUG_IOPORT |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 73 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 74 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 75 | #if !defined(CONFIG_USER_ONLY) |
| 76 | /* TB consistency checks only implemented for usermode emulation. */ |
| 77 | #undef DEBUG_TB_CHECK |
| 78 | #endif |
| 79 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 80 | #define SMC_BITMAP_USE_THRESHOLD 10 |
| 81 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 82 | static TranslationBlock *tbs; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 83 | static int code_gen_max_blocks; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 84 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 85 | static int nb_tbs; |
bellard | eb51d10 | 2003-05-14 21:51:13 +0000 | [diff] [blame] | 86 | /* any access to the tbs or the page table must use this lock */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 87 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 88 | |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 89 | #if defined(__arm__) || defined(__sparc_v9__) |
| 90 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 |
| 91 | have limited branch ranges (possibly also PPC) so place it in a |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 92 | section close to code segment. */ |
| 93 | #define code_gen_section \ |
| 94 | __attribute__((__section__(".gen_code"))) \ |
| 95 | __attribute__((aligned (32))) |
Stefan Weil | f8e2af1 | 2009-06-18 23:04:48 +0200 | [diff] [blame] | 96 | #elif defined(_WIN32) |
| 97 | /* Maximum alignment for Win32 is 16. */ |
| 98 | #define code_gen_section \ |
| 99 | __attribute__((aligned (16))) |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 100 | #else |
| 101 | #define code_gen_section \ |
| 102 | __attribute__((aligned (32))) |
| 103 | #endif |
| 104 | |
| 105 | uint8_t code_gen_prologue[1024] code_gen_section; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 106 | static uint8_t *code_gen_buffer; |
| 107 | static unsigned long code_gen_buffer_size; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 108 | /* threshold to flush the translated code buffer */ |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 109 | static unsigned long code_gen_buffer_max_size; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 110 | static uint8_t *code_gen_ptr; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 111 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 112 | #if !defined(CONFIG_USER_ONLY) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 113 | int phys_ram_fd; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 114 | static int in_migration; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 115 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 116 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 117 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 118 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 119 | CPUState *first_cpu; |
| 120 | /* current CPU in the current thread. It is only valid inside |
| 121 | cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 122 | CPUState *cpu_single_env; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 123 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 124 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 125 | 2 = Adaptive rate instruction counting. */ |
| 126 | int use_icount = 0; |
| 127 | /* Current instruction counter. While executing translated code this may |
| 128 | include some instructions that have not yet been executed. */ |
| 129 | int64_t qemu_icount; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 130 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 131 | typedef struct PageDesc { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 132 | /* list of TBs intersecting this ram page */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 133 | TranslationBlock *first_tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 134 | /* in order to optimize self modifying code, we count the number |
| 135 | of lookups we do to a given page to use a bitmap */ |
| 136 | unsigned int code_write_count; |
| 137 | uint8_t *code_bitmap; |
| 138 | #if defined(CONFIG_USER_ONLY) |
| 139 | unsigned long flags; |
| 140 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 141 | } PageDesc; |
| 142 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 143 | /* In system mode we want L1_MAP to be based on ram offsets, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 144 | while in user mode we want it to be based on virtual addresses. */ |
| 145 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 146 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
| 147 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS |
| 148 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 149 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 150 | #endif |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 151 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 152 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 153 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 154 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 155 | /* Size of the L2 (and L3, etc) page tables. */ |
| 156 | #define L2_BITS 10 |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 157 | #define L2_SIZE (1 << L2_BITS) |
| 158 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 159 | /* The bits remaining after N lower levels of page tables. */ |
| 160 | #define P_L1_BITS_REM \ |
| 161 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 162 | #define V_L1_BITS_REM \ |
| 163 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 164 | |
| 165 | /* Size of the L1 page table. Avoid silly small sizes. */ |
| 166 | #if P_L1_BITS_REM < 4 |
| 167 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) |
| 168 | #else |
| 169 | #define P_L1_BITS P_L1_BITS_REM |
| 170 | #endif |
| 171 | |
| 172 | #if V_L1_BITS_REM < 4 |
| 173 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) |
| 174 | #else |
| 175 | #define V_L1_BITS V_L1_BITS_REM |
| 176 | #endif |
| 177 | |
| 178 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) |
| 179 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) |
| 180 | |
| 181 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) |
| 182 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) |
| 183 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 184 | unsigned long qemu_real_host_page_size; |
| 185 | unsigned long qemu_host_page_bits; |
| 186 | unsigned long qemu_host_page_size; |
| 187 | unsigned long qemu_host_page_mask; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 188 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 189 | /* This is a multi-level map on the virtual address space. |
| 190 | The bottom level has pointers to PageDesc. */ |
| 191 | static void *l1_map[V_L1_SIZE]; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 192 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 193 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 194 | typedef struct PhysPageDesc { |
| 195 | /* offset in host memory of the page + io_index in the low bits */ |
| 196 | ram_addr_t phys_offset; |
| 197 | ram_addr_t region_offset; |
| 198 | } PhysPageDesc; |
| 199 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 200 | /* This is a multi-level map on the physical address space. |
| 201 | The bottom level has pointers to PhysPageDesc. */ |
| 202 | static void *l1_phys_map[P_L1_SIZE]; |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 203 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 204 | static void io_mem_init(void); |
| 205 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 206 | /* io memory support */ |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 207 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 208 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 209 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
blueswir1 | 511d2b1 | 2009-03-07 15:32:56 +0000 | [diff] [blame] | 210 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 211 | static int io_mem_watch; |
| 212 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 213 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 214 | /* log support */ |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 215 | #ifdef WIN32 |
| 216 | static const char *logfilename = "qemu.log"; |
| 217 | #else |
blueswir1 | d9b630f | 2008-10-05 09:57:08 +0000 | [diff] [blame] | 218 | static const char *logfilename = "/tmp/qemu.log"; |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 219 | #endif |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 220 | FILE *logfile; |
| 221 | int loglevel; |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 222 | static int log_append = 0; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 223 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 224 | /* statistics */ |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 225 | #if !defined(CONFIG_USER_ONLY) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 226 | static int tlb_flush_count; |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 227 | #endif |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 228 | static int tb_flush_count; |
| 229 | static int tb_phys_invalidate_count; |
| 230 | |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 231 | #ifdef _WIN32 |
| 232 | static void map_exec(void *addr, long size) |
| 233 | { |
| 234 | DWORD old_protect; |
| 235 | VirtualProtect(addr, size, |
| 236 | PAGE_EXECUTE_READWRITE, &old_protect); |
| 237 | |
| 238 | } |
| 239 | #else |
| 240 | static void map_exec(void *addr, long size) |
| 241 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 242 | unsigned long start, end, page_size; |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 243 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 244 | page_size = getpagesize(); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 245 | start = (unsigned long)addr; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 246 | start &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 247 | |
| 248 | end = (unsigned long)addr + size; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 249 | end += page_size - 1; |
| 250 | end &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 251 | |
| 252 | mprotect((void *)start, end - start, |
| 253 | PROT_READ | PROT_WRITE | PROT_EXEC); |
| 254 | } |
| 255 | #endif |
| 256 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 257 | static void page_init(void) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 258 | { |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 259 | /* NOTE: we can always suppose that qemu_host_page_size >= |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 260 | TARGET_PAGE_SIZE */ |
aliguori | c2b48b6 | 2008-11-11 22:06:42 +0000 | [diff] [blame] | 261 | #ifdef _WIN32 |
| 262 | { |
| 263 | SYSTEM_INFO system_info; |
| 264 | |
| 265 | GetSystemInfo(&system_info); |
| 266 | qemu_real_host_page_size = system_info.dwPageSize; |
| 267 | } |
| 268 | #else |
| 269 | qemu_real_host_page_size = getpagesize(); |
| 270 | #endif |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 271 | if (qemu_host_page_size == 0) |
| 272 | qemu_host_page_size = qemu_real_host_page_size; |
| 273 | if (qemu_host_page_size < TARGET_PAGE_SIZE) |
| 274 | qemu_host_page_size = TARGET_PAGE_SIZE; |
| 275 | qemu_host_page_bits = 0; |
| 276 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) |
| 277 | qemu_host_page_bits++; |
| 278 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 279 | |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 280 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 281 | { |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 282 | #ifdef HAVE_KINFO_GETVMMAP |
| 283 | struct kinfo_vmentry *freep; |
| 284 | int i, cnt; |
| 285 | |
| 286 | freep = kinfo_getvmmap(getpid(), &cnt); |
| 287 | if (freep) { |
| 288 | mmap_lock(); |
| 289 | for (i = 0; i < cnt; i++) { |
| 290 | unsigned long startaddr, endaddr; |
| 291 | |
| 292 | startaddr = freep[i].kve_start; |
| 293 | endaddr = freep[i].kve_end; |
| 294 | if (h2g_valid(startaddr)) { |
| 295 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 296 | |
| 297 | if (h2g_valid(endaddr)) { |
| 298 | endaddr = h2g(endaddr); |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 299 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 300 | } else { |
| 301 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS |
| 302 | endaddr = ~0ul; |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 303 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 304 | #endif |
| 305 | } |
| 306 | } |
| 307 | } |
| 308 | free(freep); |
| 309 | mmap_unlock(); |
| 310 | } |
| 311 | #else |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 312 | FILE *f; |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 313 | |
pbrook | 0776590 | 2008-05-31 16:33:53 +0000 | [diff] [blame] | 314 | last_brk = (unsigned long)sbrk(0); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 315 | |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 316 | f = fopen("/compat/linux/proc/self/maps", "r"); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 317 | if (f) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 318 | mmap_lock(); |
| 319 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 320 | do { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 321 | unsigned long startaddr, endaddr; |
| 322 | int n; |
| 323 | |
| 324 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); |
| 325 | |
| 326 | if (n == 2 && h2g_valid(startaddr)) { |
| 327 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 328 | |
| 329 | if (h2g_valid(endaddr)) { |
| 330 | endaddr = h2g(endaddr); |
| 331 | } else { |
| 332 | endaddr = ~0ul; |
| 333 | } |
| 334 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 335 | } |
| 336 | } while (!feof(f)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 337 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 338 | fclose(f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 339 | mmap_unlock(); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 340 | } |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 341 | #endif |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 342 | } |
| 343 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 346 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 347 | { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 348 | PageDesc *pd; |
| 349 | void **lp; |
| 350 | int i; |
| 351 | |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 352 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 353 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 354 | # define ALLOC(P, SIZE) \ |
| 355 | do { \ |
| 356 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ |
| 357 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 358 | } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 359 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 360 | # define ALLOC(P, SIZE) \ |
| 361 | do { P = qemu_mallocz(SIZE); } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 362 | #endif |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 363 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 364 | /* Level 1. Always allocated. */ |
| 365 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); |
| 366 | |
| 367 | /* Level 2..N-1. */ |
| 368 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 369 | void **p = *lp; |
| 370 | |
| 371 | if (p == NULL) { |
| 372 | if (!alloc) { |
| 373 | return NULL; |
| 374 | } |
| 375 | ALLOC(p, sizeof(void *) * L2_SIZE); |
| 376 | *lp = p; |
| 377 | } |
| 378 | |
| 379 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 380 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 381 | |
| 382 | pd = *lp; |
| 383 | if (pd == NULL) { |
| 384 | if (!alloc) { |
| 385 | return NULL; |
| 386 | } |
| 387 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); |
| 388 | *lp = pd; |
| 389 | } |
| 390 | |
| 391 | #undef ALLOC |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 392 | |
| 393 | return pd + (index & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 396 | static inline PageDesc *page_find(tb_page_addr_t index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 397 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 398 | return page_find_alloc(index, 0); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 399 | } |
| 400 | |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 401 | #if !defined(CONFIG_USER_ONLY) |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 402 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 403 | { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 404 | PhysPageDesc *pd; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 405 | void **lp; |
| 406 | int i; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 407 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 408 | /* Level 1. Always allocated. */ |
| 409 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 410 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 411 | /* Level 2..N-1. */ |
| 412 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 413 | void **p = *lp; |
| 414 | if (p == NULL) { |
| 415 | if (!alloc) { |
| 416 | return NULL; |
| 417 | } |
| 418 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); |
| 419 | } |
| 420 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 421 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 422 | |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 423 | pd = *lp; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 424 | if (pd == NULL) { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 425 | int i; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 426 | |
| 427 | if (!alloc) { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 428 | return NULL; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); |
| 432 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 433 | for (i = 0; i < L2_SIZE; i++) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 434 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
| 435 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 436 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 437 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 438 | |
| 439 | return pd + (index & (L2_SIZE - 1)); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 440 | } |
| 441 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 442 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 443 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 444 | return phys_page_find_alloc(index, 0); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 445 | } |
| 446 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 447 | static void tlb_protect_code(ram_addr_t ram_addr); |
| 448 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 449 | target_ulong vaddr); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 450 | #define mmap_lock() do { } while(0) |
| 451 | #define mmap_unlock() do { } while(0) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 452 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 453 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 454 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
| 455 | |
| 456 | #if defined(CONFIG_USER_ONLY) |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 457 | /* Currently it is not recommended to allocate big chunks of data in |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 458 | user mode. It will change when a dedicated libc will be used */ |
| 459 | #define USE_STATIC_CODE_GEN_BUFFER |
| 460 | #endif |
| 461 | |
| 462 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
Aurelien Jarno | ebf50fb | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 463 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
| 464 | __attribute__((aligned (CODE_GEN_ALIGN))); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 465 | #endif |
| 466 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 467 | static void code_gen_alloc(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 468 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 469 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 470 | code_gen_buffer = static_code_gen_buffer; |
| 471 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 472 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 473 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 474 | code_gen_buffer_size = tb_size; |
| 475 | if (code_gen_buffer_size == 0) { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 476 | #if defined(CONFIG_USER_ONLY) |
| 477 | /* in user mode, phys_ram_size is not meaningful */ |
| 478 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 479 | #else |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 480 | /* XXX: needs adjustments */ |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 481 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 482 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 483 | } |
| 484 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) |
| 485 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; |
| 486 | /* The code gen buffer location may have constraints depending on |
| 487 | the host cpu and OS */ |
| 488 | #if defined(__linux__) |
| 489 | { |
| 490 | int flags; |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 491 | void *start = NULL; |
| 492 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 493 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 494 | #if defined(__x86_64__) |
| 495 | flags |= MAP_32BIT; |
| 496 | /* Cannot map more than that */ |
| 497 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 498 | code_gen_buffer_size = (800 * 1024 * 1024); |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 499 | #elif defined(__sparc_v9__) |
| 500 | // Map the buffer below 2G, so we can use direct calls and branches |
| 501 | flags |= MAP_FIXED; |
| 502 | start = (void *) 0x60000000UL; |
| 503 | if (code_gen_buffer_size > (512 * 1024 * 1024)) |
| 504 | code_gen_buffer_size = (512 * 1024 * 1024); |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 505 | #elif defined(__arm__) |
balrog | 63d4124 | 2008-12-01 02:19:41 +0000 | [diff] [blame] | 506 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 507 | flags |= MAP_FIXED; |
| 508 | start = (void *) 0x01000000UL; |
| 509 | if (code_gen_buffer_size > 16 * 1024 * 1024) |
| 510 | code_gen_buffer_size = 16 * 1024 * 1024; |
Richard Henderson | eba0b89 | 2010-06-04 12:14:14 -0700 | [diff] [blame] | 511 | #elif defined(__s390x__) |
| 512 | /* Map the buffer so that we can use direct calls and branches. */ |
| 513 | /* We have a +- 4GB range on the branches; leave some slop. */ |
| 514 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { |
| 515 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; |
| 516 | } |
| 517 | start = (void *)0x90000000UL; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 518 | #endif |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 519 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
| 520 | PROT_WRITE | PROT_READ | PROT_EXEC, |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 521 | flags, -1, 0); |
| 522 | if (code_gen_buffer == MAP_FAILED) { |
| 523 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 524 | exit(1); |
| 525 | } |
| 526 | } |
Aurelien Jarno | a167ba5 | 2009-11-29 18:00:41 +0100 | [diff] [blame] | 527 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 528 | { |
| 529 | int flags; |
| 530 | void *addr = NULL; |
| 531 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 532 | #if defined(__x86_64__) |
| 533 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume |
| 534 | * 0x40000000 is free */ |
| 535 | flags |= MAP_FIXED; |
| 536 | addr = (void *)0x40000000; |
| 537 | /* Cannot map more than that */ |
| 538 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 539 | code_gen_buffer_size = (800 * 1024 * 1024); |
| 540 | #endif |
| 541 | code_gen_buffer = mmap(addr, code_gen_buffer_size, |
| 542 | PROT_WRITE | PROT_READ | PROT_EXEC, |
| 543 | flags, -1, 0); |
| 544 | if (code_gen_buffer == MAP_FAILED) { |
| 545 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 546 | exit(1); |
| 547 | } |
| 548 | } |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 549 | #else |
| 550 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 551 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 552 | #endif |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 553 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 554 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
| 555 | code_gen_buffer_max_size = code_gen_buffer_size - |
Aurelien Jarno | 239fda3 | 2010-06-03 19:29:31 +0200 | [diff] [blame] | 556 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 557 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
| 558 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
| 559 | } |
| 560 | |
| 561 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
| 562 | (in bytes) allocated to the translation buffer. Zero means default |
| 563 | size. */ |
| 564 | void cpu_exec_init_all(unsigned long tb_size) |
| 565 | { |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 566 | cpu_gen_init(); |
| 567 | code_gen_alloc(tb_size); |
| 568 | code_gen_ptr = code_gen_buffer; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 569 | page_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 570 | #if !defined(CONFIG_USER_ONLY) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 571 | io_mem_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 572 | #endif |
Richard Henderson | 9002ec7 | 2010-05-06 08:50:41 -0700 | [diff] [blame] | 573 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
| 574 | /* There's no guest base to take into account, so go ahead and |
| 575 | initialize the prologue now. */ |
| 576 | tcg_prologue_init(&tcg_ctx); |
| 577 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 578 | } |
| 579 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 580 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
| 581 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 582 | static int cpu_common_post_load(void *opaque, int version_id) |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 583 | { |
| 584 | CPUState *env = opaque; |
| 585 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 586 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
| 587 | version_id is increased. */ |
| 588 | env->interrupt_request &= ~0x01; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 589 | tlb_flush(env, 1); |
| 590 | |
| 591 | return 0; |
| 592 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 593 | |
| 594 | static const VMStateDescription vmstate_cpu_common = { |
| 595 | .name = "cpu_common", |
| 596 | .version_id = 1, |
| 597 | .minimum_version_id = 1, |
| 598 | .minimum_version_id_old = 1, |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 599 | .post_load = cpu_common_post_load, |
| 600 | .fields = (VMStateField []) { |
| 601 | VMSTATE_UINT32(halted, CPUState), |
| 602 | VMSTATE_UINT32(interrupt_request, CPUState), |
| 603 | VMSTATE_END_OF_LIST() |
| 604 | } |
| 605 | }; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 606 | #endif |
| 607 | |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 608 | CPUState *qemu_get_cpu(int cpu) |
| 609 | { |
| 610 | CPUState *env = first_cpu; |
| 611 | |
| 612 | while (env) { |
| 613 | if (env->cpu_index == cpu) |
| 614 | break; |
| 615 | env = env->next_cpu; |
| 616 | } |
| 617 | |
| 618 | return env; |
| 619 | } |
| 620 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 621 | void cpu_exec_init(CPUState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 622 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 623 | CPUState **penv; |
| 624 | int cpu_index; |
| 625 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 626 | #if defined(CONFIG_USER_ONLY) |
| 627 | cpu_list_lock(); |
| 628 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 629 | env->next_cpu = NULL; |
| 630 | penv = &first_cpu; |
| 631 | cpu_index = 0; |
| 632 | while (*penv != NULL) { |
Nathan Froyd | 1e9fa73 | 2009-06-03 11:33:08 -0700 | [diff] [blame] | 633 | penv = &(*penv)->next_cpu; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 634 | cpu_index++; |
| 635 | } |
| 636 | env->cpu_index = cpu_index; |
aliguori | 268a362 | 2009-04-21 22:30:27 +0000 | [diff] [blame] | 637 | env->numa_node = 0; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 638 | QTAILQ_INIT(&env->breakpoints); |
| 639 | QTAILQ_INIT(&env->watchpoints); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 640 | *penv = env; |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 641 | #if defined(CONFIG_USER_ONLY) |
| 642 | cpu_list_unlock(); |
| 643 | #endif |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 644 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
Alex Williamson | 0be71e3 | 2010-06-25 11:09:07 -0600 | [diff] [blame] | 645 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
| 646 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 647 | cpu_save, cpu_load, env); |
| 648 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 649 | } |
| 650 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 651 | static inline void invalidate_page_bitmap(PageDesc *p) |
| 652 | { |
| 653 | if (p->code_bitmap) { |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 654 | qemu_free(p->code_bitmap); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 655 | p->code_bitmap = NULL; |
| 656 | } |
| 657 | p->code_write_count = 0; |
| 658 | } |
| 659 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 660 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
| 661 | |
| 662 | static void page_flush_tb_1 (int level, void **lp) |
| 663 | { |
| 664 | int i; |
| 665 | |
| 666 | if (*lp == NULL) { |
| 667 | return; |
| 668 | } |
| 669 | if (level == 0) { |
| 670 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 671 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 672 | pd[i].first_tb = NULL; |
| 673 | invalidate_page_bitmap(pd + i); |
| 674 | } |
| 675 | } else { |
| 676 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 677 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 678 | page_flush_tb_1 (level - 1, pp + i); |
| 679 | } |
| 680 | } |
| 681 | } |
| 682 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 683 | static void page_flush_tb(void) |
| 684 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 685 | int i; |
| 686 | for (i = 0; i < V_L1_SIZE; i++) { |
| 687 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 688 | } |
| 689 | } |
| 690 | |
| 691 | /* flush all the translation blocks */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 692 | /* XXX: tb_flush is currently not thread safe */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 693 | void tb_flush(CPUState *env1) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 694 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 695 | CPUState *env; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 696 | #if defined(DEBUG_FLUSH) |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 697 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
| 698 | (unsigned long)(code_gen_ptr - code_gen_buffer), |
| 699 | nb_tbs, nb_tbs > 0 ? |
| 700 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 701 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 702 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 703 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
| 704 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 705 | nb_tbs = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 706 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 707 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 708 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
| 709 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 710 | |
bellard | 8a8a608 | 2004-10-03 13:36:49 +0000 | [diff] [blame] | 711 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 712 | page_flush_tb(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 713 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 714 | code_gen_ptr = code_gen_buffer; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 715 | /* XXX: flush processor icache at this point if cache flush is |
| 716 | expensive */ |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 717 | tb_flush_count++; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | #ifdef DEBUG_TB_CHECK |
| 721 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 722 | static void tb_invalidate_check(target_ulong address) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 723 | { |
| 724 | TranslationBlock *tb; |
| 725 | int i; |
| 726 | address &= TARGET_PAGE_MASK; |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 727 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 728 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 729 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
| 730 | address >= tb->pc + tb->size)) { |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 731 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
| 732 | " PC=%08lx size=%04x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 733 | address, (long)tb->pc, tb->size); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | /* verify that all the pages have correct rights for code */ |
| 740 | static void tb_page_check(void) |
| 741 | { |
| 742 | TranslationBlock *tb; |
| 743 | int i, flags1, flags2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 744 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 745 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 746 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 747 | flags1 = page_get_flags(tb->pc); |
| 748 | flags2 = page_get_flags(tb->pc + tb->size - 1); |
| 749 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { |
| 750 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 751 | (long)tb->pc, tb->size, flags1, flags2); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 752 | } |
| 753 | } |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | #endif |
| 758 | |
| 759 | /* invalidate one TB */ |
| 760 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, |
| 761 | int next_offset) |
| 762 | { |
| 763 | TranslationBlock *tb1; |
| 764 | for(;;) { |
| 765 | tb1 = *ptb; |
| 766 | if (tb1 == tb) { |
| 767 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); |
| 768 | break; |
| 769 | } |
| 770 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); |
| 771 | } |
| 772 | } |
| 773 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 774 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
| 775 | { |
| 776 | TranslationBlock *tb1; |
| 777 | unsigned int n1; |
| 778 | |
| 779 | for(;;) { |
| 780 | tb1 = *ptb; |
| 781 | n1 = (long)tb1 & 3; |
| 782 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 783 | if (tb1 == tb) { |
| 784 | *ptb = tb1->page_next[n1]; |
| 785 | break; |
| 786 | } |
| 787 | ptb = &tb1->page_next[n1]; |
| 788 | } |
| 789 | } |
| 790 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 791 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
| 792 | { |
| 793 | TranslationBlock *tb1, **ptb; |
| 794 | unsigned int n1; |
| 795 | |
| 796 | ptb = &tb->jmp_next[n]; |
| 797 | tb1 = *ptb; |
| 798 | if (tb1) { |
| 799 | /* find tb(n) in circular list */ |
| 800 | for(;;) { |
| 801 | tb1 = *ptb; |
| 802 | n1 = (long)tb1 & 3; |
| 803 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 804 | if (n1 == n && tb1 == tb) |
| 805 | break; |
| 806 | if (n1 == 2) { |
| 807 | ptb = &tb1->jmp_first; |
| 808 | } else { |
| 809 | ptb = &tb1->jmp_next[n1]; |
| 810 | } |
| 811 | } |
| 812 | /* now we can suppress tb(n) from the list */ |
| 813 | *ptb = tb->jmp_next[n]; |
| 814 | |
| 815 | tb->jmp_next[n] = NULL; |
| 816 | } |
| 817 | } |
| 818 | |
| 819 | /* reset the jump entry 'n' of a TB so that it is not chained to |
| 820 | another TB */ |
| 821 | static inline void tb_reset_jump(TranslationBlock *tb, int n) |
| 822 | { |
| 823 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); |
| 824 | } |
| 825 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 826 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 827 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 828 | CPUState *env; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 829 | PageDesc *p; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 830 | unsigned int h, n1; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 831 | tb_page_addr_t phys_pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 832 | TranslationBlock *tb1, *tb2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 833 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 834 | /* remove the TB from the hash list */ |
| 835 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 836 | h = tb_phys_hash_func(phys_pc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 837 | tb_remove(&tb_phys_hash[h], tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 838 | offsetof(TranslationBlock, phys_hash_next)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 839 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 840 | /* remove the TB from the page list */ |
| 841 | if (tb->page_addr[0] != page_addr) { |
| 842 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); |
| 843 | tb_page_remove(&p->first_tb, tb); |
| 844 | invalidate_page_bitmap(p); |
| 845 | } |
| 846 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { |
| 847 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); |
| 848 | tb_page_remove(&p->first_tb, tb); |
| 849 | invalidate_page_bitmap(p); |
| 850 | } |
| 851 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 852 | tb_invalidated_flag = 1; |
| 853 | |
| 854 | /* remove the TB from the hash list */ |
| 855 | h = tb_jmp_cache_hash_func(tb->pc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 856 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 857 | if (env->tb_jmp_cache[h] == tb) |
| 858 | env->tb_jmp_cache[h] = NULL; |
| 859 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 860 | |
| 861 | /* suppress this TB from the two jump lists */ |
| 862 | tb_jmp_remove(tb, 0); |
| 863 | tb_jmp_remove(tb, 1); |
| 864 | |
| 865 | /* suppress any remaining jumps to this TB */ |
| 866 | tb1 = tb->jmp_first; |
| 867 | for(;;) { |
| 868 | n1 = (long)tb1 & 3; |
| 869 | if (n1 == 2) |
| 870 | break; |
| 871 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 872 | tb2 = tb1->jmp_next[n1]; |
| 873 | tb_reset_jump(tb1, n1); |
| 874 | tb1->jmp_next[n1] = NULL; |
| 875 | tb1 = tb2; |
| 876 | } |
| 877 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ |
| 878 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 879 | tb_phys_invalidate_count++; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | static inline void set_bits(uint8_t *tab, int start, int len) |
| 883 | { |
| 884 | int end, mask, end1; |
| 885 | |
| 886 | end = start + len; |
| 887 | tab += start >> 3; |
| 888 | mask = 0xff << (start & 7); |
| 889 | if ((start & ~7) == (end & ~7)) { |
| 890 | if (start < end) { |
| 891 | mask &= ~(0xff << (end & 7)); |
| 892 | *tab |= mask; |
| 893 | } |
| 894 | } else { |
| 895 | *tab++ |= mask; |
| 896 | start = (start + 8) & ~7; |
| 897 | end1 = end & ~7; |
| 898 | while (start < end1) { |
| 899 | *tab++ = 0xff; |
| 900 | start += 8; |
| 901 | } |
| 902 | if (start < end) { |
| 903 | mask = ~(0xff << (end & 7)); |
| 904 | *tab |= mask; |
| 905 | } |
| 906 | } |
| 907 | } |
| 908 | |
| 909 | static void build_page_bitmap(PageDesc *p) |
| 910 | { |
| 911 | int n, tb_start, tb_end; |
| 912 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 913 | |
pbrook | b2a7081 | 2008-06-09 13:57:23 +0000 | [diff] [blame] | 914 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 915 | |
| 916 | tb = p->first_tb; |
| 917 | while (tb != NULL) { |
| 918 | n = (long)tb & 3; |
| 919 | tb = (TranslationBlock *)((long)tb & ~3); |
| 920 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 921 | if (n == 0) { |
| 922 | /* NOTE: tb_end may be after the end of the page, but |
| 923 | it is not a problem */ |
| 924 | tb_start = tb->pc & ~TARGET_PAGE_MASK; |
| 925 | tb_end = tb_start + tb->size; |
| 926 | if (tb_end > TARGET_PAGE_SIZE) |
| 927 | tb_end = TARGET_PAGE_SIZE; |
| 928 | } else { |
| 929 | tb_start = 0; |
| 930 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 931 | } |
| 932 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); |
| 933 | tb = tb->page_next[n]; |
| 934 | } |
| 935 | } |
| 936 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 937 | TranslationBlock *tb_gen_code(CPUState *env, |
| 938 | target_ulong pc, target_ulong cs_base, |
| 939 | int flags, int cflags) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 940 | { |
| 941 | TranslationBlock *tb; |
| 942 | uint8_t *tc_ptr; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 943 | tb_page_addr_t phys_pc, phys_page2; |
| 944 | target_ulong virt_page2; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 945 | int code_gen_size; |
| 946 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 947 | phys_pc = get_page_addr_code(env, pc); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 948 | tb = tb_alloc(pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 949 | if (!tb) { |
| 950 | /* flush must be done */ |
| 951 | tb_flush(env); |
| 952 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 953 | tb = tb_alloc(pc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 954 | /* Don't forget to invalidate previous TB info. */ |
| 955 | tb_invalidated_flag = 1; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 956 | } |
| 957 | tc_ptr = code_gen_ptr; |
| 958 | tb->tc_ptr = tc_ptr; |
| 959 | tb->cs_base = cs_base; |
| 960 | tb->flags = flags; |
| 961 | tb->cflags = cflags; |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 962 | cpu_gen_code(env, tb, &code_gen_size); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 963 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 964 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 965 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 966 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 967 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 968 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 969 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 970 | } |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 971 | tb_link_page(tb, phys_pc, phys_page2); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 972 | return tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 973 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 974 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 975 | /* invalidate all TBs which intersect with the target physical page |
| 976 | starting in range [start;end[. NOTE: start and end must refer to |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 977 | the same physical page. 'is_cpu_write_access' should be true if called |
| 978 | from a real cpu write access: the virtual CPU will exit the current |
| 979 | TB if code is modified inside this TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 980 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 981 | int is_cpu_write_access) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 982 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 983 | TranslationBlock *tb, *tb_next, *saved_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 984 | CPUState *env = cpu_single_env; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 985 | tb_page_addr_t tb_start, tb_end; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 986 | PageDesc *p; |
| 987 | int n; |
| 988 | #ifdef TARGET_HAS_PRECISE_SMC |
| 989 | int current_tb_not_found = is_cpu_write_access; |
| 990 | TranslationBlock *current_tb = NULL; |
| 991 | int current_tb_modified = 0; |
| 992 | target_ulong current_pc = 0; |
| 993 | target_ulong current_cs_base = 0; |
| 994 | int current_flags = 0; |
| 995 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 996 | |
| 997 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 998 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 999 | return; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1000 | if (!p->code_bitmap && |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1001 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
| 1002 | is_cpu_write_access) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1003 | /* build code bitmap */ |
| 1004 | build_page_bitmap(p); |
| 1005 | } |
| 1006 | |
| 1007 | /* we remove all the TBs in the range [start, end[ */ |
| 1008 | /* XXX: see if in some cases it could be faster to invalidate all the code */ |
| 1009 | tb = p->first_tb; |
| 1010 | while (tb != NULL) { |
| 1011 | n = (long)tb & 3; |
| 1012 | tb = (TranslationBlock *)((long)tb & ~3); |
| 1013 | tb_next = tb->page_next[n]; |
| 1014 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 1015 | if (n == 0) { |
| 1016 | /* NOTE: tb_end may be after the end of the page, but |
| 1017 | it is not a problem */ |
| 1018 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 1019 | tb_end = tb_start + tb->size; |
| 1020 | } else { |
| 1021 | tb_start = tb->page_addr[1]; |
| 1022 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 1023 | } |
| 1024 | if (!(tb_end <= start || tb_start >= end)) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1025 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1026 | if (current_tb_not_found) { |
| 1027 | current_tb_not_found = 0; |
| 1028 | current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1029 | if (env->mem_io_pc) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1030 | /* now we have a real cpu fault */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1031 | current_tb = tb_find_pc(env->mem_io_pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1032 | } |
| 1033 | } |
| 1034 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1035 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1036 | /* If we are modifying the current TB, we must stop |
| 1037 | its execution. We could be more precise by checking |
| 1038 | that the modification is after the current PC, but it |
| 1039 | would require a specialized function to partially |
| 1040 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1041 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1042 | current_tb_modified = 1; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1043 | cpu_restore_state(current_tb, env, |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1044 | env->mem_io_pc, NULL); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1045 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1046 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1047 | } |
| 1048 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1049 | /* we need to do that to handle the case where a signal |
| 1050 | occurs while doing tb_phys_invalidate() */ |
| 1051 | saved_tb = NULL; |
| 1052 | if (env) { |
| 1053 | saved_tb = env->current_tb; |
| 1054 | env->current_tb = NULL; |
| 1055 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1056 | tb_phys_invalidate(tb, -1); |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1057 | if (env) { |
| 1058 | env->current_tb = saved_tb; |
| 1059 | if (env->interrupt_request && env->current_tb) |
| 1060 | cpu_interrupt(env, env->interrupt_request); |
| 1061 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1062 | } |
| 1063 | tb = tb_next; |
| 1064 | } |
| 1065 | #if !defined(CONFIG_USER_ONLY) |
| 1066 | /* if no code remaining, no need to continue to use slow writes */ |
| 1067 | if (!p->first_tb) { |
| 1068 | invalidate_page_bitmap(p); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1069 | if (is_cpu_write_access) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1070 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1071 | } |
| 1072 | } |
| 1073 | #endif |
| 1074 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1075 | if (current_tb_modified) { |
| 1076 | /* we generate a block containing just the instruction |
| 1077 | modifying the memory. It will ensure that it cannot modify |
| 1078 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1079 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1080 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1081 | cpu_resume_from_signal(env, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1082 | } |
| 1083 | #endif |
| 1084 | } |
| 1085 | |
| 1086 | /* len must be <= 8 and start must be a multiple of len */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1087 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1088 | { |
| 1089 | PageDesc *p; |
| 1090 | int offset, b; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1091 | #if 0 |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 1092 | if (1) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1093 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
| 1094 | cpu_single_env->mem_io_vaddr, len, |
| 1095 | cpu_single_env->eip, |
| 1096 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1097 | } |
| 1098 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1099 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1100 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1101 | return; |
| 1102 | if (p->code_bitmap) { |
| 1103 | offset = start & ~TARGET_PAGE_MASK; |
| 1104 | b = p->code_bitmap[offset >> 3] >> (offset & 7); |
| 1105 | if (b & ((1 << len) - 1)) |
| 1106 | goto do_invalidate; |
| 1107 | } else { |
| 1108 | do_invalidate: |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1109 | tb_invalidate_phys_page_range(start, start + len, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1110 | } |
| 1111 | } |
| 1112 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1113 | #if !defined(CONFIG_SOFTMMU) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1114 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1115 | unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1116 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1117 | TranslationBlock *tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1118 | PageDesc *p; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1119 | int n; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1120 | #ifdef TARGET_HAS_PRECISE_SMC |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1121 | TranslationBlock *current_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1122 | CPUState *env = cpu_single_env; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1123 | int current_tb_modified = 0; |
| 1124 | target_ulong current_pc = 0; |
| 1125 | target_ulong current_cs_base = 0; |
| 1126 | int current_flags = 0; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1127 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1128 | |
| 1129 | addr &= TARGET_PAGE_MASK; |
| 1130 | p = page_find(addr >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1131 | if (!p) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1132 | return; |
| 1133 | tb = p->first_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1134 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1135 | if (tb && pc != 0) { |
| 1136 | current_tb = tb_find_pc(pc); |
| 1137 | } |
| 1138 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1139 | while (tb != NULL) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1140 | n = (long)tb & 3; |
| 1141 | tb = (TranslationBlock *)((long)tb & ~3); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1142 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1143 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1144 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1145 | /* If we are modifying the current TB, we must stop |
| 1146 | its execution. We could be more precise by checking |
| 1147 | that the modification is after the current PC, but it |
| 1148 | would require a specialized function to partially |
| 1149 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1150 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1151 | current_tb_modified = 1; |
| 1152 | cpu_restore_state(current_tb, env, pc, puc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1153 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1154 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1155 | } |
| 1156 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1157 | tb_phys_invalidate(tb, addr); |
| 1158 | tb = tb->page_next[n]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1159 | } |
| 1160 | p->first_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1161 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1162 | if (current_tb_modified) { |
| 1163 | /* we generate a block containing just the instruction |
| 1164 | modifying the memory. It will ensure that it cannot modify |
| 1165 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1166 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1167 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1168 | cpu_resume_from_signal(env, puc); |
| 1169 | } |
| 1170 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1171 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1172 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1173 | |
| 1174 | /* add the tb in the target page and protect it if necessary */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1175 | static inline void tb_alloc_page(TranslationBlock *tb, |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1176 | unsigned int n, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1177 | { |
| 1178 | PageDesc *p; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1179 | TranslationBlock *last_first_tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1180 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1181 | tb->page_addr[n] = page_addr; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1182 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1183 | tb->page_next[n] = p->first_tb; |
| 1184 | last_first_tb = p->first_tb; |
| 1185 | p->first_tb = (TranslationBlock *)((long)tb | n); |
| 1186 | invalidate_page_bitmap(p); |
| 1187 | |
bellard | 107db44 | 2004-06-22 18:48:46 +0000 | [diff] [blame] | 1188 | #if defined(TARGET_HAS_SMC) || 1 |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1189 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1190 | #if defined(CONFIG_USER_ONLY) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1191 | if (p->flags & PAGE_WRITE) { |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1192 | target_ulong addr; |
| 1193 | PageDesc *p2; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1194 | int prot; |
| 1195 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1196 | /* force the host page as non writable (writes will have a |
| 1197 | page fault + mprotect overhead) */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1198 | page_addr &= qemu_host_page_mask; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1199 | prot = 0; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1200 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
| 1201 | addr += TARGET_PAGE_SIZE) { |
| 1202 | |
| 1203 | p2 = page_find (addr >> TARGET_PAGE_BITS); |
| 1204 | if (!p2) |
| 1205 | continue; |
| 1206 | prot |= p2->flags; |
| 1207 | p2->flags &= ~PAGE_WRITE; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1208 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1209 | mprotect(g2h(page_addr), qemu_host_page_size, |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1210 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
| 1211 | #ifdef DEBUG_TB_INVALIDATE |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 1212 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1213 | page_addr); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1214 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1215 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1216 | #else |
| 1217 | /* if some code is already present, then the pages are already |
| 1218 | protected. So we handle the case where only the first TB is |
| 1219 | allocated in a physical page */ |
| 1220 | if (!last_first_tb) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1221 | tlb_protect_code(page_addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1222 | } |
| 1223 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1224 | |
| 1225 | #endif /* TARGET_HAS_SMC */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1226 | } |
| 1227 | |
| 1228 | /* Allocate a new translation block. Flush the translation buffer if |
| 1229 | too many translation blocks or too much generated code. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1230 | TranslationBlock *tb_alloc(target_ulong pc) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1231 | { |
| 1232 | TranslationBlock *tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1233 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 1234 | if (nb_tbs >= code_gen_max_blocks || |
| 1235 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1236 | return NULL; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1237 | tb = &tbs[nb_tbs++]; |
| 1238 | tb->pc = pc; |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 1239 | tb->cflags = 0; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1240 | return tb; |
| 1241 | } |
| 1242 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1243 | void tb_free(TranslationBlock *tb) |
| 1244 | { |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 1245 | /* In practice this is mostly used for single use temporary TB |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1246 | Ignore the hard cases and just back up if this TB happens to |
| 1247 | be the last one generated. */ |
| 1248 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { |
| 1249 | code_gen_ptr = tb->tc_ptr; |
| 1250 | nb_tbs--; |
| 1251 | } |
| 1252 | } |
| 1253 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1254 | /* add a new TB and link it to the physical page tables. phys_page2 is |
| 1255 | (-1) to indicate that only one page contains the TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1256 | void tb_link_page(TranslationBlock *tb, |
| 1257 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1258 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1259 | unsigned int h; |
| 1260 | TranslationBlock **ptb; |
| 1261 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1262 | /* Grab the mmap lock to stop another thread invalidating this TB |
| 1263 | before we are done. */ |
| 1264 | mmap_lock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1265 | /* add in the physical hash table */ |
| 1266 | h = tb_phys_hash_func(phys_pc); |
| 1267 | ptb = &tb_phys_hash[h]; |
| 1268 | tb->phys_hash_next = *ptb; |
| 1269 | *ptb = tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1270 | |
| 1271 | /* add in the page list */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1272 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
| 1273 | if (phys_page2 != -1) |
| 1274 | tb_alloc_page(tb, 1, phys_page2); |
| 1275 | else |
| 1276 | tb->page_addr[1] = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1277 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1278 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
| 1279 | tb->jmp_next[0] = NULL; |
| 1280 | tb->jmp_next[1] = NULL; |
| 1281 | |
| 1282 | /* init original jump addresses */ |
| 1283 | if (tb->tb_next_offset[0] != 0xffff) |
| 1284 | tb_reset_jump(tb, 0); |
| 1285 | if (tb->tb_next_offset[1] != 0xffff) |
| 1286 | tb_reset_jump(tb, 1); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1287 | |
| 1288 | #ifdef DEBUG_TB_CHECK |
| 1289 | tb_page_check(); |
| 1290 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1291 | mmap_unlock(); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1294 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
| 1295 | tb[1].tc_ptr. Return NULL if not found */ |
| 1296 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) |
| 1297 | { |
| 1298 | int m_min, m_max, m; |
| 1299 | unsigned long v; |
| 1300 | TranslationBlock *tb; |
| 1301 | |
| 1302 | if (nb_tbs <= 0) |
| 1303 | return NULL; |
| 1304 | if (tc_ptr < (unsigned long)code_gen_buffer || |
| 1305 | tc_ptr >= (unsigned long)code_gen_ptr) |
| 1306 | return NULL; |
| 1307 | /* binary search (cf Knuth) */ |
| 1308 | m_min = 0; |
| 1309 | m_max = nb_tbs - 1; |
| 1310 | while (m_min <= m_max) { |
| 1311 | m = (m_min + m_max) >> 1; |
| 1312 | tb = &tbs[m]; |
| 1313 | v = (unsigned long)tb->tc_ptr; |
| 1314 | if (v == tc_ptr) |
| 1315 | return tb; |
| 1316 | else if (tc_ptr < v) { |
| 1317 | m_max = m - 1; |
| 1318 | } else { |
| 1319 | m_min = m + 1; |
| 1320 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1321 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1322 | return &tbs[m_max]; |
| 1323 | } |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1324 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1325 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
| 1326 | |
| 1327 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) |
| 1328 | { |
| 1329 | TranslationBlock *tb1, *tb_next, **ptb; |
| 1330 | unsigned int n1; |
| 1331 | |
| 1332 | tb1 = tb->jmp_next[n]; |
| 1333 | if (tb1 != NULL) { |
| 1334 | /* find head of list */ |
| 1335 | for(;;) { |
| 1336 | n1 = (long)tb1 & 3; |
| 1337 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1338 | if (n1 == 2) |
| 1339 | break; |
| 1340 | tb1 = tb1->jmp_next[n1]; |
| 1341 | } |
| 1342 | /* we are now sure now that tb jumps to tb1 */ |
| 1343 | tb_next = tb1; |
| 1344 | |
| 1345 | /* remove tb from the jmp_first list */ |
| 1346 | ptb = &tb_next->jmp_first; |
| 1347 | for(;;) { |
| 1348 | tb1 = *ptb; |
| 1349 | n1 = (long)tb1 & 3; |
| 1350 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1351 | if (n1 == n && tb1 == tb) |
| 1352 | break; |
| 1353 | ptb = &tb1->jmp_next[n1]; |
| 1354 | } |
| 1355 | *ptb = tb->jmp_next[n]; |
| 1356 | tb->jmp_next[n] = NULL; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1357 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1358 | /* suppress the jump to next tb in generated code */ |
| 1359 | tb_reset_jump(tb, n); |
| 1360 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1361 | /* suppress jumps in the tb on which we could have jumped */ |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1362 | tb_reset_jump_recursive(tb_next); |
| 1363 | } |
| 1364 | } |
| 1365 | |
| 1366 | static void tb_reset_jump_recursive(TranslationBlock *tb) |
| 1367 | { |
| 1368 | tb_reset_jump_recursive2(tb, 0); |
| 1369 | tb_reset_jump_recursive2(tb, 1); |
| 1370 | } |
| 1371 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1372 | #if defined(TARGET_HAS_ICE) |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1373 | #if defined(CONFIG_USER_ONLY) |
| 1374 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1375 | { |
| 1376 | tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 1377 | } |
| 1378 | #else |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1379 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1380 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1381 | target_phys_addr_t addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 1382 | target_ulong pd; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1383 | ram_addr_t ram_addr; |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1384 | PhysPageDesc *p; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1385 | |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1386 | addr = cpu_get_phys_page_debug(env, pc); |
| 1387 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 1388 | if (!p) { |
| 1389 | pd = IO_MEM_UNASSIGNED; |
| 1390 | } else { |
| 1391 | pd = p->phys_offset; |
| 1392 | } |
| 1393 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); |
pbrook | 706cd4b | 2006-04-08 17:36:21 +0000 | [diff] [blame] | 1394 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1395 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1396 | #endif |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1397 | #endif /* TARGET_HAS_ICE */ |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1398 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1399 | #if defined(CONFIG_USER_ONLY) |
| 1400 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1401 | |
| 1402 | { |
| 1403 | } |
| 1404 | |
| 1405 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1406 | int flags, CPUWatchpoint **watchpoint) |
| 1407 | { |
| 1408 | return -ENOSYS; |
| 1409 | } |
| 1410 | #else |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1411 | /* Add a watchpoint. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1412 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1413 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1414 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1415 | target_ulong len_mask = ~(len - 1); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1416 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1417 | |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1418 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
| 1419 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { |
| 1420 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
| 1421 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 1422 | return -EINVAL; |
| 1423 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1424 | wp = qemu_malloc(sizeof(*wp)); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1425 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1426 | wp->vaddr = addr; |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1427 | wp->len_mask = len_mask; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1428 | wp->flags = flags; |
| 1429 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1430 | /* keep all GDB-injected watchpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1431 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1432 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1433 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1434 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1435 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1436 | tlb_flush_page(env, addr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1437 | |
| 1438 | if (watchpoint) |
| 1439 | *watchpoint = wp; |
| 1440 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1441 | } |
| 1442 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1443 | /* Remove a specific watchpoint. */ |
| 1444 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, |
| 1445 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1446 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1447 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1448 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1449 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1450 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1451 | if (addr == wp->vaddr && len_mask == wp->len_mask |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1452 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1453 | cpu_watchpoint_remove_by_ref(env, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1454 | return 0; |
| 1455 | } |
| 1456 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1457 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1458 | } |
| 1459 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1460 | /* Remove a specific watchpoint by reference. */ |
| 1461 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) |
| 1462 | { |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1463 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1464 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1465 | tlb_flush_page(env, watchpoint->vaddr); |
| 1466 | |
| 1467 | qemu_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1468 | } |
| 1469 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1470 | /* Remove all matching watchpoints. */ |
| 1471 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1472 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1473 | CPUWatchpoint *wp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1474 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1475 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1476 | if (wp->flags & mask) |
| 1477 | cpu_watchpoint_remove_by_ref(env, wp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1478 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1479 | } |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1480 | #endif |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1481 | |
| 1482 | /* Add a breakpoint. */ |
| 1483 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 1484 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1485 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1486 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1487 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1488 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1489 | bp = qemu_malloc(sizeof(*bp)); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1490 | |
| 1491 | bp->pc = pc; |
| 1492 | bp->flags = flags; |
| 1493 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1494 | /* keep all GDB-injected breakpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1495 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1496 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1497 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1498 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1499 | |
| 1500 | breakpoint_invalidate(env, pc); |
| 1501 | |
| 1502 | if (breakpoint) |
| 1503 | *breakpoint = bp; |
| 1504 | return 0; |
| 1505 | #else |
| 1506 | return -ENOSYS; |
| 1507 | #endif |
| 1508 | } |
| 1509 | |
| 1510 | /* Remove a specific breakpoint. */ |
| 1511 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) |
| 1512 | { |
| 1513 | #if defined(TARGET_HAS_ICE) |
| 1514 | CPUBreakpoint *bp; |
| 1515 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1516 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1517 | if (bp->pc == pc && bp->flags == flags) { |
| 1518 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1519 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1520 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1521 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1522 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1523 | #else |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1524 | return -ENOSYS; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1525 | #endif |
| 1526 | } |
| 1527 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1528 | /* Remove a specific breakpoint by reference. */ |
| 1529 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1530 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1531 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1532 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1533 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1534 | breakpoint_invalidate(env, breakpoint->pc); |
| 1535 | |
| 1536 | qemu_free(breakpoint); |
| 1537 | #endif |
| 1538 | } |
| 1539 | |
| 1540 | /* Remove all matching breakpoints. */ |
| 1541 | void cpu_breakpoint_remove_all(CPUState *env, int mask) |
| 1542 | { |
| 1543 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1544 | CPUBreakpoint *bp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1545 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1546 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1547 | if (bp->flags & mask) |
| 1548 | cpu_breakpoint_remove_by_ref(env, bp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1549 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1550 | #endif |
| 1551 | } |
| 1552 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1553 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 1554 | CPU loop after each instruction */ |
| 1555 | void cpu_single_step(CPUState *env, int enabled) |
| 1556 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1557 | #if defined(TARGET_HAS_ICE) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1558 | if (env->singlestep_enabled != enabled) { |
| 1559 | env->singlestep_enabled = enabled; |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1560 | if (kvm_enabled()) |
| 1561 | kvm_update_guest_debug(env, 0); |
| 1562 | else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 1563 | /* must flush all the translated code to avoid inconsistencies */ |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1564 | /* XXX: only flush what is necessary */ |
| 1565 | tb_flush(env); |
| 1566 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1567 | } |
| 1568 | #endif |
| 1569 | } |
| 1570 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1571 | /* enable or disable low levels log */ |
| 1572 | void cpu_set_log(int log_flags) |
| 1573 | { |
| 1574 | loglevel = log_flags; |
| 1575 | if (loglevel && !logfile) { |
pbrook | 11fcfab | 2007-07-01 18:21:11 +0000 | [diff] [blame] | 1576 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1577 | if (!logfile) { |
| 1578 | perror(logfilename); |
| 1579 | _exit(1); |
| 1580 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1581 | #if !defined(CONFIG_SOFTMMU) |
| 1582 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
| 1583 | { |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1584 | static char logfile_buf[4096]; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1585 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
| 1586 | } |
Filip Navara | bf65f53 | 2009-07-27 10:02:04 -0500 | [diff] [blame] | 1587 | #elif !defined(_WIN32) |
| 1588 | /* Win32 doesn't support line-buffering and requires size >= 2 */ |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1589 | setvbuf(logfile, NULL, _IOLBF, 0); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1590 | #endif |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1591 | log_append = 1; |
| 1592 | } |
| 1593 | if (!loglevel && logfile) { |
| 1594 | fclose(logfile); |
| 1595 | logfile = NULL; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1596 | } |
| 1597 | } |
| 1598 | |
| 1599 | void cpu_set_log_filename(const char *filename) |
| 1600 | { |
| 1601 | logfilename = strdup(filename); |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1602 | if (logfile) { |
| 1603 | fclose(logfile); |
| 1604 | logfile = NULL; |
| 1605 | } |
| 1606 | cpu_set_log(loglevel); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1607 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1608 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1609 | static void cpu_unlink_tb(CPUState *env) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1610 | { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1611 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
| 1612 | problem and hope the cpu will stop of its own accord. For userspace |
| 1613 | emulation this often isn't actually as bad as it sounds. Often |
| 1614 | signals are used primarily to interrupt blocking syscalls. */ |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1615 | TranslationBlock *tb; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1616 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1617 | |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1618 | spin_lock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1619 | tb = env->current_tb; |
| 1620 | /* if the cpu is currently executing code, we must unlink it and |
| 1621 | all the potentially executing TB */ |
Riku Voipio | f76cfe5 | 2009-12-04 15:16:30 +0200 | [diff] [blame] | 1622 | if (tb) { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1623 | env->current_tb = NULL; |
| 1624 | tb_reset_jump_recursive(tb); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1625 | } |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1626 | spin_unlock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1627 | } |
| 1628 | |
| 1629 | /* mask must never be zero, except for A20 change call */ |
| 1630 | void cpu_interrupt(CPUState *env, int mask) |
| 1631 | { |
| 1632 | int old_mask; |
| 1633 | |
| 1634 | old_mask = env->interrupt_request; |
| 1635 | env->interrupt_request |= mask; |
| 1636 | |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1637 | #ifndef CONFIG_USER_ONLY |
| 1638 | /* |
| 1639 | * If called from iothread context, wake the target cpu in |
| 1640 | * case its halted. |
| 1641 | */ |
| 1642 | if (!qemu_cpu_self(env)) { |
| 1643 | qemu_cpu_kick(env); |
| 1644 | return; |
| 1645 | } |
| 1646 | #endif |
| 1647 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1648 | if (use_icount) { |
pbrook | 266910c | 2008-07-09 15:31:50 +0000 | [diff] [blame] | 1649 | env->icount_decr.u16.high = 0xffff; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1650 | #ifndef CONFIG_USER_ONLY |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1651 | if (!can_do_io(env) |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 1652 | && (mask & ~old_mask) != 0) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1653 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
| 1654 | } |
| 1655 | #endif |
| 1656 | } else { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1657 | cpu_unlink_tb(env); |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1658 | } |
| 1659 | } |
| 1660 | |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 1661 | void cpu_reset_interrupt(CPUState *env, int mask) |
| 1662 | { |
| 1663 | env->interrupt_request &= ~mask; |
| 1664 | } |
| 1665 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1666 | void cpu_exit(CPUState *env) |
| 1667 | { |
| 1668 | env->exit_request = 1; |
| 1669 | cpu_unlink_tb(env); |
| 1670 | } |
| 1671 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1672 | const CPULogItem cpu_log_items[] = { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1673 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1674 | "show generated host assembly code for each compiled TB" }, |
| 1675 | { CPU_LOG_TB_IN_ASM, "in_asm", |
| 1676 | "show target assembly code for each compiled TB" }, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1677 | { CPU_LOG_TB_OP, "op", |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 1678 | "show micro ops for each compiled TB" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1679 | { CPU_LOG_TB_OP_OPT, "op_opt", |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1680 | "show micro ops " |
| 1681 | #ifdef TARGET_I386 |
| 1682 | "before eflags optimization and " |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1683 | #endif |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1684 | "after liveness analysis" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1685 | { CPU_LOG_INT, "int", |
| 1686 | "show interrupts/exceptions in short format" }, |
| 1687 | { CPU_LOG_EXEC, "exec", |
| 1688 | "show trace before each executed TB (lots of logs)" }, |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1689 | { CPU_LOG_TB_CPU, "cpu", |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 1690 | "show CPU state before block translation" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1691 | #ifdef TARGET_I386 |
| 1692 | { CPU_LOG_PCALL, "pcall", |
| 1693 | "show protected mode far calls/returns/exceptions" }, |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 1694 | { CPU_LOG_RESET, "cpu_reset", |
| 1695 | "show CPU state before CPU resets" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1696 | #endif |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1697 | #ifdef DEBUG_IOPORT |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 1698 | { CPU_LOG_IOPORT, "ioport", |
| 1699 | "show all i/o ports accesses" }, |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1700 | #endif |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1701 | { 0, NULL, NULL }, |
| 1702 | }; |
| 1703 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1704 | #ifndef CONFIG_USER_ONLY |
| 1705 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list |
| 1706 | = QLIST_HEAD_INITIALIZER(memory_client_list); |
| 1707 | |
| 1708 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1709 | ram_addr_t size, |
| 1710 | ram_addr_t phys_offset) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1711 | { |
| 1712 | CPUPhysMemoryClient *client; |
| 1713 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1714 | client->set_memory(client, start_addr, size, phys_offset); |
| 1715 | } |
| 1716 | } |
| 1717 | |
| 1718 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1719 | target_phys_addr_t end) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1720 | { |
| 1721 | CPUPhysMemoryClient *client; |
| 1722 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1723 | int r = client->sync_dirty_bitmap(client, start, end); |
| 1724 | if (r < 0) |
| 1725 | return r; |
| 1726 | } |
| 1727 | return 0; |
| 1728 | } |
| 1729 | |
| 1730 | static int cpu_notify_migration_log(int enable) |
| 1731 | { |
| 1732 | CPUPhysMemoryClient *client; |
| 1733 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1734 | int r = client->migration_log(client, enable); |
| 1735 | if (r < 0) |
| 1736 | return r; |
| 1737 | } |
| 1738 | return 0; |
| 1739 | } |
| 1740 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1741 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, |
| 1742 | int level, void **lp) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1743 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1744 | int i; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1745 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1746 | if (*lp == NULL) { |
| 1747 | return; |
| 1748 | } |
| 1749 | if (level == 0) { |
| 1750 | PhysPageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1751 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1752 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
| 1753 | client->set_memory(client, pd[i].region_offset, |
| 1754 | TARGET_PAGE_SIZE, pd[i].phys_offset); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1755 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1756 | } |
| 1757 | } else { |
| 1758 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1759 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1760 | phys_page_for_each_1(client, level - 1, pp + i); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1761 | } |
| 1762 | } |
| 1763 | } |
| 1764 | |
| 1765 | static void phys_page_for_each(CPUPhysMemoryClient *client) |
| 1766 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1767 | int i; |
| 1768 | for (i = 0; i < P_L1_SIZE; ++i) { |
| 1769 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, |
| 1770 | l1_phys_map + 1); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1771 | } |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1772 | } |
| 1773 | |
| 1774 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) |
| 1775 | { |
| 1776 | QLIST_INSERT_HEAD(&memory_client_list, client, list); |
| 1777 | phys_page_for_each(client); |
| 1778 | } |
| 1779 | |
| 1780 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) |
| 1781 | { |
| 1782 | QLIST_REMOVE(client, list); |
| 1783 | } |
| 1784 | #endif |
| 1785 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1786 | static int cmp1(const char *s1, int n, const char *s2) |
| 1787 | { |
| 1788 | if (strlen(s2) != n) |
| 1789 | return 0; |
| 1790 | return memcmp(s1, s2, n) == 0; |
| 1791 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1792 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1793 | /* takes a comma separated list of log masks. Return 0 if error. */ |
| 1794 | int cpu_str_to_log_mask(const char *str) |
| 1795 | { |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1796 | const CPULogItem *item; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1797 | int mask; |
| 1798 | const char *p, *p1; |
| 1799 | |
| 1800 | p = str; |
| 1801 | mask = 0; |
| 1802 | for(;;) { |
| 1803 | p1 = strchr(p, ','); |
| 1804 | if (!p1) |
| 1805 | p1 = p + strlen(p); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1806 | if(cmp1(p,p1-p,"all")) { |
| 1807 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1808 | mask |= item->mask; |
| 1809 | } |
| 1810 | } else { |
| 1811 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1812 | if (cmp1(p, p1 - p, item->name)) |
| 1813 | goto found; |
| 1814 | } |
| 1815 | return 0; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1816 | } |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1817 | found: |
| 1818 | mask |= item->mask; |
| 1819 | if (*p1 != ',') |
| 1820 | break; |
| 1821 | p = p1 + 1; |
| 1822 | } |
| 1823 | return mask; |
| 1824 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1825 | |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1826 | void cpu_abort(CPUState *env, const char *fmt, ...) |
| 1827 | { |
| 1828 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1829 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1830 | |
| 1831 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1832 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1833 | fprintf(stderr, "qemu: fatal: "); |
| 1834 | vfprintf(stderr, fmt, ap); |
| 1835 | fprintf(stderr, "\n"); |
| 1836 | #ifdef TARGET_I386 |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 1837 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1838 | #else |
| 1839 | cpu_dump_state(env, stderr, fprintf, 0); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1840 | #endif |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1841 | if (qemu_log_enabled()) { |
| 1842 | qemu_log("qemu: fatal: "); |
| 1843 | qemu_log_vprintf(fmt, ap2); |
| 1844 | qemu_log("\n"); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1845 | #ifdef TARGET_I386 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1846 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1847 | #else |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1848 | log_cpu_state(env, 0); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1849 | #endif |
aliguori | 31b1a7b | 2009-01-15 22:35:09 +0000 | [diff] [blame] | 1850 | qemu_log_flush(); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1851 | qemu_log_close(); |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1852 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1853 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1854 | va_end(ap); |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 1855 | #if defined(CONFIG_USER_ONLY) |
| 1856 | { |
| 1857 | struct sigaction act; |
| 1858 | sigfillset(&act.sa_mask); |
| 1859 | act.sa_handler = SIG_DFL; |
| 1860 | sigaction(SIGABRT, &act, NULL); |
| 1861 | } |
| 1862 | #endif |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1863 | abort(); |
| 1864 | } |
| 1865 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1866 | CPUState *cpu_copy(CPUState *env) |
| 1867 | { |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 1868 | CPUState *new_env = cpu_init(env->cpu_model_str); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1869 | CPUState *next_cpu = new_env->next_cpu; |
| 1870 | int cpu_index = new_env->cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1871 | #if defined(TARGET_HAS_ICE) |
| 1872 | CPUBreakpoint *bp; |
| 1873 | CPUWatchpoint *wp; |
| 1874 | #endif |
| 1875 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1876 | memcpy(new_env, env, sizeof(CPUState)); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1877 | |
| 1878 | /* Preserve chaining and index. */ |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1879 | new_env->next_cpu = next_cpu; |
| 1880 | new_env->cpu_index = cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1881 | |
| 1882 | /* Clone all break/watchpoints. |
| 1883 | Note: Once we support ptrace with hw-debug register access, make sure |
| 1884 | BP_CPU break/watchpoints are handled correctly on clone. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1885 | QTAILQ_INIT(&env->breakpoints); |
| 1886 | QTAILQ_INIT(&env->watchpoints); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1887 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1888 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1889 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
| 1890 | } |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1891 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1892 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
| 1893 | wp->flags, NULL); |
| 1894 | } |
| 1895 | #endif |
| 1896 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1897 | return new_env; |
| 1898 | } |
| 1899 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1900 | #if !defined(CONFIG_USER_ONLY) |
| 1901 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1902 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
| 1903 | { |
| 1904 | unsigned int i; |
| 1905 | |
| 1906 | /* Discard jump cache entries for any tb which might potentially |
| 1907 | overlap the flushed page. */ |
| 1908 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); |
| 1909 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1910 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1911 | |
| 1912 | i = tb_jmp_cache_hash_page(addr); |
| 1913 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1914 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1915 | } |
| 1916 | |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1917 | static CPUTLBEntry s_cputlb_empty_entry = { |
| 1918 | .addr_read = -1, |
| 1919 | .addr_write = -1, |
| 1920 | .addr_code = -1, |
| 1921 | .addend = -1, |
| 1922 | }; |
| 1923 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 1924 | /* NOTE: if flush_global is true, also flush global entries (not |
| 1925 | implemented yet) */ |
| 1926 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1927 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1928 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1929 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1930 | #if defined(DEBUG_TLB) |
| 1931 | printf("tlb_flush:\n"); |
| 1932 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1933 | /* must reset current TB so that interrupts cannot modify the |
| 1934 | links while we are modifying them */ |
| 1935 | env->current_tb = NULL; |
| 1936 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1937 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1938 | int mmu_idx; |
| 1939 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1940 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1941 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1942 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1943 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1944 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1945 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1946 | env->tlb_flush_addr = -1; |
| 1947 | env->tlb_flush_mask = 0; |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 1948 | tlb_flush_count++; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1949 | } |
| 1950 | |
bellard | 274da6b | 2004-05-20 21:56:27 +0000 | [diff] [blame] | 1951 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1952 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1953 | if (addr == (tlb_entry->addr_read & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1954 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1955 | addr == (tlb_entry->addr_write & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1956 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1957 | addr == (tlb_entry->addr_code & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1958 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1959 | *tlb_entry = s_cputlb_empty_entry; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1960 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1961 | } |
| 1962 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 1963 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1964 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1965 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1966 | int mmu_idx; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1967 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1968 | #if defined(DEBUG_TLB) |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 1969 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1970 | #endif |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1971 | /* Check if we need to flush due to large pages. */ |
| 1972 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { |
| 1973 | #if defined(DEBUG_TLB) |
| 1974 | printf("tlb_flush_page: forced full flush (" |
| 1975 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
| 1976 | env->tlb_flush_addr, env->tlb_flush_mask); |
| 1977 | #endif |
| 1978 | tlb_flush(env, 1); |
| 1979 | return; |
| 1980 | } |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1981 | /* must reset current TB so that interrupts cannot modify the |
| 1982 | links while we are modifying them */ |
| 1983 | env->current_tb = NULL; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1984 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1985 | addr &= TARGET_PAGE_MASK; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1986 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1987 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 1988 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1989 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1990 | tlb_flush_jmp_cache(env, addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1991 | } |
| 1992 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1993 | /* update the TLBs so that writes to code in the virtual page 'addr' |
| 1994 | can be detected */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1995 | static void tlb_protect_code(ram_addr_t ram_addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1996 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1997 | cpu_physical_memory_reset_dirty(ram_addr, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1998 | ram_addr + TARGET_PAGE_SIZE, |
| 1999 | CODE_DIRTY_FLAG); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2000 | } |
| 2001 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2002 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2003 | tested for self modifying code */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2004 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2005 | target_ulong vaddr) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2006 | { |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2007 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2008 | } |
| 2009 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2010 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2011 | unsigned long start, unsigned long length) |
| 2012 | { |
| 2013 | unsigned long addr; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2014 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
| 2015 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2016 | if ((addr - start) < length) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2017 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2018 | } |
| 2019 | } |
| 2020 | } |
| 2021 | |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2022 | /* Note: start and end must be within the same ram block. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2023 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 2024 | int dirty_flags) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2025 | { |
| 2026 | CPUState *env; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2027 | unsigned long length, start1; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2028 | int i; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2029 | |
| 2030 | start &= TARGET_PAGE_MASK; |
| 2031 | end = TARGET_PAGE_ALIGN(end); |
| 2032 | |
| 2033 | length = end - start; |
| 2034 | if (length == 0) |
| 2035 | return; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2036 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2037 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2038 | /* we modify the TLB cache so that the dirty bit will be set again |
| 2039 | when accessing the range */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2040 | start1 = (unsigned long)qemu_get_ram_ptr(start); |
| 2041 | /* Chek that we don't span multiple blocks - this breaks the |
| 2042 | address comparisons below. */ |
| 2043 | if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1 |
| 2044 | != (end - 1) - start) { |
| 2045 | abort(); |
| 2046 | } |
| 2047 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2048 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2049 | int mmu_idx; |
| 2050 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2051 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2052 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
| 2053 | start1, length); |
| 2054 | } |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2055 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2056 | } |
| 2057 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2058 | int cpu_physical_memory_set_dirty_tracking(int enable) |
| 2059 | { |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2060 | int ret = 0; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2061 | in_migration = enable; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2062 | ret = cpu_notify_migration_log(!!enable); |
| 2063 | return ret; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2064 | } |
| 2065 | |
| 2066 | int cpu_physical_memory_get_dirty_tracking(void) |
| 2067 | { |
| 2068 | return in_migration; |
| 2069 | } |
| 2070 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2071 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
| 2072 | target_phys_addr_t end_addr) |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2073 | { |
Michael S. Tsirkin | 7b8f3b7 | 2010-01-27 22:07:21 +0200 | [diff] [blame] | 2074 | int ret; |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2075 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2076 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2077 | return ret; |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2078 | } |
| 2079 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2080 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
| 2081 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2082 | ram_addr_t ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2083 | void *p; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2084 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2085 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2086 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
| 2087 | + tlb_entry->addend); |
| 2088 | ram_addr = qemu_ram_addr_from_host(p); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2089 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2090 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2091 | } |
| 2092 | } |
| 2093 | } |
| 2094 | |
| 2095 | /* update the TLB according to the current state of the dirty bits */ |
| 2096 | void cpu_tlb_update_dirty(CPUState *env) |
| 2097 | { |
| 2098 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2099 | int mmu_idx; |
| 2100 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2101 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2102 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); |
| 2103 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2104 | } |
| 2105 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2106 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2107 | { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2108 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
| 2109 | tlb_entry->addr_write = vaddr; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2110 | } |
| 2111 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2112 | /* update the TLB corresponding to virtual page vaddr |
| 2113 | so that it is no longer dirty */ |
| 2114 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2115 | { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2116 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2117 | int mmu_idx; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2118 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2119 | vaddr &= TARGET_PAGE_MASK; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2120 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2121 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2122 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2123 | } |
| 2124 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2125 | /* Our TLB does not support large pages, so remember the area covered by |
| 2126 | large pages and trigger a full TLB flush if these are invalidated. */ |
| 2127 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, |
| 2128 | target_ulong size) |
| 2129 | { |
| 2130 | target_ulong mask = ~(size - 1); |
| 2131 | |
| 2132 | if (env->tlb_flush_addr == (target_ulong)-1) { |
| 2133 | env->tlb_flush_addr = vaddr & mask; |
| 2134 | env->tlb_flush_mask = mask; |
| 2135 | return; |
| 2136 | } |
| 2137 | /* Extend the existing region to include the new page. |
| 2138 | This is a compromise between unnecessary flushes and the cost |
| 2139 | of maintaining a full variable size TLB. */ |
| 2140 | mask &= env->tlb_flush_mask; |
| 2141 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
| 2142 | mask <<= 1; |
| 2143 | } |
| 2144 | env->tlb_flush_addr &= mask; |
| 2145 | env->tlb_flush_mask = mask; |
| 2146 | } |
| 2147 | |
| 2148 | /* Add a new TLB entry. At most one entry for a given virtual address |
| 2149 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the |
| 2150 | supplied size is only used by tlb_flush_page. */ |
| 2151 | void tlb_set_page(CPUState *env, target_ulong vaddr, |
| 2152 | target_phys_addr_t paddr, int prot, |
| 2153 | int mmu_idx, target_ulong size) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2154 | { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2155 | PhysPageDesc *p; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2156 | unsigned long pd; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2157 | unsigned int index; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2158 | target_ulong address; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2159 | target_ulong code_address; |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 2160 | unsigned long addend; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2161 | CPUTLBEntry *te; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2162 | CPUWatchpoint *wp; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2163 | target_phys_addr_t iotlb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2164 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2165 | assert(size >= TARGET_PAGE_SIZE); |
| 2166 | if (size != TARGET_PAGE_SIZE) { |
| 2167 | tlb_add_large_page(env, vaddr, size); |
| 2168 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2169 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2170 | if (!p) { |
| 2171 | pd = IO_MEM_UNASSIGNED; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2172 | } else { |
| 2173 | pd = p->phys_offset; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2174 | } |
| 2175 | #if defined(DEBUG_TLB) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 2176 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n", |
| 2177 | vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2178 | #endif |
| 2179 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2180 | address = vaddr; |
| 2181 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
| 2182 | /* IO memory case (romd handled later) */ |
| 2183 | address |= TLB_MMIO; |
| 2184 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2185 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2186 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
| 2187 | /* Normal RAM. */ |
| 2188 | iotlb = pd & TARGET_PAGE_MASK; |
| 2189 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 2190 | iotlb |= IO_MEM_NOTDIRTY; |
| 2191 | else |
| 2192 | iotlb |= IO_MEM_ROM; |
| 2193 | } else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2194 | /* IO handlers are currently passed a physical address. |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2195 | It would be nice to pass an offset from the base address |
| 2196 | of that region. This would avoid having to special case RAM, |
| 2197 | and avoid full address decoding in every device. |
| 2198 | We can't use the high bits of pd for this because |
| 2199 | IO_MEM_ROMD uses these as a ram address. */ |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2200 | iotlb = (pd & ~TARGET_PAGE_MASK); |
| 2201 | if (p) { |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2202 | iotlb += p->region_offset; |
| 2203 | } else { |
| 2204 | iotlb += paddr; |
| 2205 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2206 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2207 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2208 | code_address = address; |
| 2209 | /* Make accesses to pages with watchpoints go via the |
| 2210 | watchpoint trap routines. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2211 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2212 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
Jun Koi | bf298f8 | 2010-05-06 14:36:59 +0900 | [diff] [blame] | 2213 | /* Avoid trapping reads of pages with a write breakpoint. */ |
| 2214 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { |
| 2215 | iotlb = io_mem_watch + paddr; |
| 2216 | address |= TLB_MMIO; |
| 2217 | break; |
| 2218 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2219 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2220 | } |
balrog | d79acba | 2007-06-26 20:01:13 +0000 | [diff] [blame] | 2221 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2222 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 2223 | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
| 2224 | te = &env->tlb_table[mmu_idx][index]; |
| 2225 | te->addend = addend - vaddr; |
| 2226 | if (prot & PAGE_READ) { |
| 2227 | te->addr_read = address; |
| 2228 | } else { |
| 2229 | te->addr_read = -1; |
| 2230 | } |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2231 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2232 | if (prot & PAGE_EXEC) { |
| 2233 | te->addr_code = code_address; |
| 2234 | } else { |
| 2235 | te->addr_code = -1; |
| 2236 | } |
| 2237 | if (prot & PAGE_WRITE) { |
| 2238 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
| 2239 | (pd & IO_MEM_ROMD)) { |
| 2240 | /* Write access calls the I/O callback. */ |
| 2241 | te->addr_write = address | TLB_MMIO; |
| 2242 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
| 2243 | !cpu_physical_memory_is_dirty(pd)) { |
| 2244 | te->addr_write = address | TLB_NOTDIRTY; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2245 | } else { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2246 | te->addr_write = address; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2247 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2248 | } else { |
| 2249 | te->addr_write = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2250 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2251 | } |
| 2252 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2253 | #else |
| 2254 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 2255 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2256 | { |
| 2257 | } |
| 2258 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2259 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2260 | { |
| 2261 | } |
| 2262 | |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2263 | /* |
| 2264 | * Walks guest process memory "regions" one by one |
| 2265 | * and calls callback function 'fn' for each region. |
| 2266 | */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2267 | |
| 2268 | struct walk_memory_regions_data |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2269 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2270 | walk_memory_regions_fn fn; |
| 2271 | void *priv; |
| 2272 | unsigned long start; |
| 2273 | int prot; |
| 2274 | }; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2275 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2276 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2277 | abi_ulong end, int new_prot) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2278 | { |
| 2279 | if (data->start != -1ul) { |
| 2280 | int rc = data->fn(data->priv, data->start, end, data->prot); |
| 2281 | if (rc != 0) { |
| 2282 | return rc; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2283 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2284 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2285 | |
| 2286 | data->start = (new_prot ? end : -1ul); |
| 2287 | data->prot = new_prot; |
| 2288 | |
| 2289 | return 0; |
| 2290 | } |
| 2291 | |
| 2292 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2293 | abi_ulong base, int level, void **lp) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2294 | { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2295 | abi_ulong pa; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2296 | int i, rc; |
| 2297 | |
| 2298 | if (*lp == NULL) { |
| 2299 | return walk_memory_regions_end(data, base, 0); |
| 2300 | } |
| 2301 | |
| 2302 | if (level == 0) { |
| 2303 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2304 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2305 | int prot = pd[i].flags; |
| 2306 | |
| 2307 | pa = base | (i << TARGET_PAGE_BITS); |
| 2308 | if (prot != data->prot) { |
| 2309 | rc = walk_memory_regions_end(data, pa, prot); |
| 2310 | if (rc != 0) { |
| 2311 | return rc; |
| 2312 | } |
| 2313 | } |
| 2314 | } |
| 2315 | } else { |
| 2316 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2317 | for (i = 0; i < L2_SIZE; ++i) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2318 | pa = base | ((abi_ulong)i << |
| 2319 | (TARGET_PAGE_BITS + L2_BITS * level)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2320 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
| 2321 | if (rc != 0) { |
| 2322 | return rc; |
| 2323 | } |
| 2324 | } |
| 2325 | } |
| 2326 | |
| 2327 | return 0; |
| 2328 | } |
| 2329 | |
| 2330 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) |
| 2331 | { |
| 2332 | struct walk_memory_regions_data data; |
| 2333 | unsigned long i; |
| 2334 | |
| 2335 | data.fn = fn; |
| 2336 | data.priv = priv; |
| 2337 | data.start = -1ul; |
| 2338 | data.prot = 0; |
| 2339 | |
| 2340 | for (i = 0; i < V_L1_SIZE; i++) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2341 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2342 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
| 2343 | if (rc != 0) { |
| 2344 | return rc; |
| 2345 | } |
| 2346 | } |
| 2347 | |
| 2348 | return walk_memory_regions_end(&data, 0, 0); |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2349 | } |
| 2350 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2351 | static int dump_region(void *priv, abi_ulong start, |
| 2352 | abi_ulong end, unsigned long prot) |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2353 | { |
| 2354 | FILE *f = (FILE *)priv; |
| 2355 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2356 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
| 2357 | " "TARGET_ABI_FMT_lx" %c%c%c\n", |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2358 | start, end, end - start, |
| 2359 | ((prot & PAGE_READ) ? 'r' : '-'), |
| 2360 | ((prot & PAGE_WRITE) ? 'w' : '-'), |
| 2361 | ((prot & PAGE_EXEC) ? 'x' : '-')); |
| 2362 | |
| 2363 | return (0); |
| 2364 | } |
| 2365 | |
| 2366 | /* dump memory mappings */ |
| 2367 | void page_dump(FILE *f) |
| 2368 | { |
| 2369 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", |
| 2370 | "start", "end", "size", "prot"); |
| 2371 | walk_memory_regions(f, dump_region); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2372 | } |
| 2373 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2374 | int page_get_flags(target_ulong address) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2375 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2376 | PageDesc *p; |
| 2377 | |
| 2378 | p = page_find(address >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2379 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2380 | return 0; |
| 2381 | return p->flags; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2382 | } |
| 2383 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2384 | /* Modify the flags of a page and invalidate the code if necessary. |
| 2385 | The flag PAGE_WRITE_ORG is positioned automatically depending |
| 2386 | on PAGE_WRITE. The mmap_lock should already be held. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2387 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2388 | { |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2389 | target_ulong addr, len; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2390 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2391 | /* This function should never be called with addresses outside the |
| 2392 | guest address space. If this assert fires, it probably indicates |
| 2393 | a missing call to h2g_valid. */ |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2394 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2395 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2396 | #endif |
| 2397 | assert(start < end); |
| 2398 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2399 | start = start & TARGET_PAGE_MASK; |
| 2400 | end = TARGET_PAGE_ALIGN(end); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2401 | |
| 2402 | if (flags & PAGE_WRITE) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2403 | flags |= PAGE_WRITE_ORG; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2404 | } |
| 2405 | |
| 2406 | for (addr = start, len = end - start; |
| 2407 | len != 0; |
| 2408 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
| 2409 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2410 | |
| 2411 | /* If the write protection bit is set, then we invalidate |
| 2412 | the code inside. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2413 | if (!(p->flags & PAGE_WRITE) && |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2414 | (flags & PAGE_WRITE) && |
| 2415 | p->first_tb) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2416 | tb_invalidate_phys_page(addr, 0, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2417 | } |
| 2418 | p->flags = flags; |
| 2419 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2420 | } |
| 2421 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2422 | int page_check_range(target_ulong start, target_ulong len, int flags) |
| 2423 | { |
| 2424 | PageDesc *p; |
| 2425 | target_ulong end; |
| 2426 | target_ulong addr; |
| 2427 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2428 | /* This function should never be called with addresses outside the |
| 2429 | guest address space. If this assert fires, it probably indicates |
| 2430 | a missing call to h2g_valid. */ |
Blue Swirl | 338e9e6 | 2010-03-13 09:48:08 +0000 | [diff] [blame] | 2431 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2432 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2433 | #endif |
| 2434 | |
Richard Henderson | 3e0650a | 2010-03-29 10:54:42 -0700 | [diff] [blame] | 2435 | if (len == 0) { |
| 2436 | return 0; |
| 2437 | } |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2438 | if (start + len - 1 < start) { |
| 2439 | /* We've wrapped around. */ |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2440 | return -1; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2441 | } |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2442 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2443 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
| 2444 | start = start & TARGET_PAGE_MASK; |
| 2445 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2446 | for (addr = start, len = end - start; |
| 2447 | len != 0; |
| 2448 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2449 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2450 | if( !p ) |
| 2451 | return -1; |
| 2452 | if( !(p->flags & PAGE_VALID) ) |
| 2453 | return -1; |
| 2454 | |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2455 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2456 | return -1; |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2457 | if (flags & PAGE_WRITE) { |
| 2458 | if (!(p->flags & PAGE_WRITE_ORG)) |
| 2459 | return -1; |
| 2460 | /* unprotect the page if it was put read-only because it |
| 2461 | contains translated code */ |
| 2462 | if (!(p->flags & PAGE_WRITE)) { |
| 2463 | if (!page_unprotect(addr, 0, NULL)) |
| 2464 | return -1; |
| 2465 | } |
| 2466 | return 0; |
| 2467 | } |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2468 | } |
| 2469 | return 0; |
| 2470 | } |
| 2471 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2472 | /* called from signal handler: invalidate the code and unprotect the |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2473 | page. Return TRUE if the fault was successfully handled. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2474 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2475 | { |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2476 | unsigned int prot; |
| 2477 | PageDesc *p; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2478 | target_ulong host_start, host_end, addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2479 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2480 | /* Technically this isn't safe inside a signal handler. However we |
| 2481 | know this only ever happens in a synchronous SEGV handler, so in |
| 2482 | practice it seems to be ok. */ |
| 2483 | mmap_lock(); |
| 2484 | |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2485 | p = page_find(address >> TARGET_PAGE_BITS); |
| 2486 | if (!p) { |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2487 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2488 | return 0; |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2489 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2490 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2491 | /* if the page was really writable, then we change its |
| 2492 | protection back to writable */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2493 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
| 2494 | host_start = address & qemu_host_page_mask; |
| 2495 | host_end = host_start + qemu_host_page_size; |
| 2496 | |
| 2497 | prot = 0; |
| 2498 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { |
| 2499 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2500 | p->flags |= PAGE_WRITE; |
| 2501 | prot |= p->flags; |
| 2502 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2503 | /* and since the content will be modified, we must invalidate |
| 2504 | the corresponding translated code. */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2505 | tb_invalidate_phys_page(addr, pc, puc); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2506 | #ifdef DEBUG_TB_CHECK |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2507 | tb_invalidate_check(addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2508 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2509 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2510 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
| 2511 | prot & PAGE_BITS); |
| 2512 | |
| 2513 | mmap_unlock(); |
| 2514 | return 1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2515 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2516 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2517 | return 0; |
| 2518 | } |
| 2519 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2520 | static inline void tlb_set_dirty(CPUState *env, |
| 2521 | unsigned long addr, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2522 | { |
| 2523 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2524 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 2525 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2526 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2527 | |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2528 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 2529 | typedef struct subpage_t { |
| 2530 | target_phys_addr_t base; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2531 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
| 2532 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2533 | } subpage_t; |
| 2534 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2535 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 2536 | ram_addr_t memory, ram_addr_t region_offset); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2537 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2538 | ram_addr_t orig_memory, |
| 2539 | ram_addr_t region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2540 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2541 | need_subpage) \ |
| 2542 | do { \ |
| 2543 | if (addr > start_addr) \ |
| 2544 | start_addr2 = 0; \ |
| 2545 | else { \ |
| 2546 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ |
| 2547 | if (start_addr2 > 0) \ |
| 2548 | need_subpage = 1; \ |
| 2549 | } \ |
| 2550 | \ |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2551 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2552 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
| 2553 | else { \ |
| 2554 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ |
| 2555 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ |
| 2556 | need_subpage = 1; \ |
| 2557 | } \ |
| 2558 | } while (0) |
| 2559 | |
Michael S. Tsirkin | 8f2498f | 2009-09-29 18:53:16 +0200 | [diff] [blame] | 2560 | /* register physical memory. |
| 2561 | For RAM, 'size' must be a multiple of the target page size. |
| 2562 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2563 | io memory page. The address used when calling the IO function is |
| 2564 | the offset from the start of the region, plus region_offset. Both |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2565 | start_addr and region_offset are rounded down to a page boundary |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2566 | before calculating this offset. This should not be a problem unless |
| 2567 | the low bits of start_addr and region_offset differ. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2568 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
| 2569 | ram_addr_t size, |
| 2570 | ram_addr_t phys_offset, |
| 2571 | ram_addr_t region_offset) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2572 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2573 | target_phys_addr_t addr, end_addr; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2574 | PhysPageDesc *p; |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2575 | CPUState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2576 | ram_addr_t orig_size = size; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2577 | subpage_t *subpage; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2578 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2579 | cpu_notify_set_memory(start_addr, size, phys_offset); |
| 2580 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2581 | if (phys_offset == IO_MEM_UNASSIGNED) { |
| 2582 | region_offset = start_addr; |
| 2583 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2584 | region_offset &= TARGET_PAGE_MASK; |
bellard | 5fd386f | 2004-05-23 21:11:22 +0000 | [diff] [blame] | 2585 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2586 | end_addr = start_addr + (target_phys_addr_t)size; |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2587 | for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2588 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2589 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2590 | ram_addr_t orig_memory = p->phys_offset; |
| 2591 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2592 | int need_subpage = 0; |
| 2593 | |
| 2594 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, |
| 2595 | need_subpage); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2596 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2597 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
| 2598 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2599 | &p->phys_offset, orig_memory, |
| 2600 | p->region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2601 | } else { |
| 2602 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) |
| 2603 | >> IO_MEM_SHIFT]; |
| 2604 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2605 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
| 2606 | region_offset); |
| 2607 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2608 | } else { |
| 2609 | p->phys_offset = phys_offset; |
| 2610 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2611 | (phys_offset & IO_MEM_ROMD)) |
| 2612 | phys_offset += TARGET_PAGE_SIZE; |
| 2613 | } |
| 2614 | } else { |
| 2615 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2616 | p->phys_offset = phys_offset; |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2617 | p->region_offset = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2618 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2619 | (phys_offset & IO_MEM_ROMD)) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2620 | phys_offset += TARGET_PAGE_SIZE; |
pbrook | 0e8f096 | 2008-12-02 09:02:15 +0000 | [diff] [blame] | 2621 | } else { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2622 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2623 | int need_subpage = 0; |
| 2624 | |
| 2625 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, |
| 2626 | end_addr2, need_subpage); |
| 2627 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2628 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2629 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2630 | &p->phys_offset, IO_MEM_UNASSIGNED, |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2631 | addr & TARGET_PAGE_MASK); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2632 | subpage_register(subpage, start_addr2, end_addr2, |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2633 | phys_offset, region_offset); |
| 2634 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2635 | } |
| 2636 | } |
| 2637 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2638 | region_offset += TARGET_PAGE_SIZE; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2639 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2640 | |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2641 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2642 | reset the modified entries */ |
| 2643 | /* XXX: slow ! */ |
| 2644 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 2645 | tlb_flush(env, 1); |
| 2646 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2647 | } |
| 2648 | |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2649 | /* XXX: temporary until new memory mapping API */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2650 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2651 | { |
| 2652 | PhysPageDesc *p; |
| 2653 | |
| 2654 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2655 | if (!p) |
| 2656 | return IO_MEM_UNASSIGNED; |
| 2657 | return p->phys_offset; |
| 2658 | } |
| 2659 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2660 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2661 | { |
| 2662 | if (kvm_enabled()) |
| 2663 | kvm_coalesce_mmio_region(addr, size); |
| 2664 | } |
| 2665 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2666 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2667 | { |
| 2668 | if (kvm_enabled()) |
| 2669 | kvm_uncoalesce_mmio_region(addr, size); |
| 2670 | } |
| 2671 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 2672 | void qemu_flush_coalesced_mmio_buffer(void) |
| 2673 | { |
| 2674 | if (kvm_enabled()) |
| 2675 | kvm_flush_coalesced_mmio_buffer(); |
| 2676 | } |
| 2677 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2678 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 2679 | |
| 2680 | #include <sys/vfs.h> |
| 2681 | |
| 2682 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 2683 | |
| 2684 | static long gethugepagesize(const char *path) |
| 2685 | { |
| 2686 | struct statfs fs; |
| 2687 | int ret; |
| 2688 | |
| 2689 | do { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2690 | ret = statfs(path, &fs); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2691 | } while (ret != 0 && errno == EINTR); |
| 2692 | |
| 2693 | if (ret != 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2694 | perror(path); |
| 2695 | return 0; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2696 | } |
| 2697 | |
| 2698 | if (fs.f_type != HUGETLBFS_MAGIC) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2699 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2700 | |
| 2701 | return fs.f_bsize; |
| 2702 | } |
| 2703 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2704 | static void *file_ram_alloc(RAMBlock *block, |
| 2705 | ram_addr_t memory, |
| 2706 | const char *path) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2707 | { |
| 2708 | char *filename; |
| 2709 | void *area; |
| 2710 | int fd; |
| 2711 | #ifdef MAP_POPULATE |
| 2712 | int flags; |
| 2713 | #endif |
| 2714 | unsigned long hpagesize; |
| 2715 | |
| 2716 | hpagesize = gethugepagesize(path); |
| 2717 | if (!hpagesize) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2718 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2719 | } |
| 2720 | |
| 2721 | if (memory < hpagesize) { |
| 2722 | return NULL; |
| 2723 | } |
| 2724 | |
| 2725 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
| 2726 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); |
| 2727 | return NULL; |
| 2728 | } |
| 2729 | |
| 2730 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2731 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2732 | } |
| 2733 | |
| 2734 | fd = mkstemp(filename); |
| 2735 | if (fd < 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2736 | perror("unable to create backing store for hugepages"); |
| 2737 | free(filename); |
| 2738 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2739 | } |
| 2740 | unlink(filename); |
| 2741 | free(filename); |
| 2742 | |
| 2743 | memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 2744 | |
| 2745 | /* |
| 2746 | * ftruncate is not supported by hugetlbfs in older |
| 2747 | * hosts, so don't bother bailing out on errors. |
| 2748 | * If anything goes wrong with it under other filesystems, |
| 2749 | * mmap will fail. |
| 2750 | */ |
| 2751 | if (ftruncate(fd, memory)) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2752 | perror("ftruncate"); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2753 | |
| 2754 | #ifdef MAP_POPULATE |
| 2755 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case |
| 2756 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED |
| 2757 | * to sidestep this quirk. |
| 2758 | */ |
| 2759 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; |
| 2760 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); |
| 2761 | #else |
| 2762 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
| 2763 | #endif |
| 2764 | if (area == MAP_FAILED) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2765 | perror("file_ram_alloc: can't mmap RAM pages"); |
| 2766 | close(fd); |
| 2767 | return (NULL); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2768 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2769 | block->fd = fd; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2770 | return area; |
| 2771 | } |
| 2772 | #endif |
| 2773 | |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2774 | static ram_addr_t find_ram_offset(ram_addr_t size) |
| 2775 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2776 | RAMBlock *block, *next_block; |
Blue Swirl | 09d7ae9 | 2010-07-07 19:37:53 +0000 | [diff] [blame] | 2777 | ram_addr_t offset = 0, mingap = ULONG_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2778 | |
| 2779 | if (QLIST_EMPTY(&ram_list.blocks)) |
| 2780 | return 0; |
| 2781 | |
| 2782 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2783 | ram_addr_t end, next = ULONG_MAX; |
| 2784 | |
| 2785 | end = block->offset + block->length; |
| 2786 | |
| 2787 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { |
| 2788 | if (next_block->offset >= end) { |
| 2789 | next = MIN(next, next_block->offset); |
| 2790 | } |
| 2791 | } |
| 2792 | if (next - end >= size && next - end < mingap) { |
| 2793 | offset = end; |
| 2794 | mingap = next - end; |
| 2795 | } |
| 2796 | } |
| 2797 | return offset; |
| 2798 | } |
| 2799 | |
| 2800 | static ram_addr_t last_ram_offset(void) |
| 2801 | { |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2802 | RAMBlock *block; |
| 2803 | ram_addr_t last = 0; |
| 2804 | |
| 2805 | QLIST_FOREACH(block, &ram_list.blocks, next) |
| 2806 | last = MAX(last, block->offset + block->length); |
| 2807 | |
| 2808 | return last; |
| 2809 | } |
| 2810 | |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2811 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2812 | ram_addr_t size, void *host) |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2813 | { |
| 2814 | RAMBlock *new_block, *block; |
| 2815 | |
| 2816 | size = TARGET_PAGE_ALIGN(size); |
| 2817 | new_block = qemu_mallocz(sizeof(*new_block)); |
| 2818 | |
| 2819 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { |
| 2820 | char *id = dev->parent_bus->info->get_dev_path(dev); |
| 2821 | if (id) { |
| 2822 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
| 2823 | qemu_free(id); |
| 2824 | } |
| 2825 | } |
| 2826 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); |
| 2827 | |
| 2828 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2829 | if (!strcmp(block->idstr, new_block->idstr)) { |
| 2830 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
| 2831 | new_block->idstr); |
| 2832 | abort(); |
| 2833 | } |
| 2834 | } |
| 2835 | |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2836 | if (host) { |
| 2837 | new_block->host = host; |
| 2838 | } else { |
| 2839 | if (mem_path) { |
| 2840 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2841 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
| 2842 | if (!new_block->host) { |
| 2843 | new_block->host = qemu_vmalloc(size); |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame^] | 2844 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2845 | } |
| 2846 | #else |
| 2847 | fprintf(stderr, "-mem-path option unsupported\n"); |
| 2848 | exit(1); |
| 2849 | #endif |
| 2850 | } else { |
| 2851 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 2852 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
| 2853 | new_block->host = mmap((void*)0x1000000, size, |
| 2854 | PROT_EXEC|PROT_READ|PROT_WRITE, |
| 2855 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); |
| 2856 | #else |
| 2857 | new_block->host = qemu_vmalloc(size); |
| 2858 | #endif |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame^] | 2859 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2860 | } |
| 2861 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2862 | |
| 2863 | new_block->offset = find_ram_offset(size); |
| 2864 | new_block->length = size; |
| 2865 | |
| 2866 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
| 2867 | |
| 2868 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
| 2869 | last_ram_offset() >> TARGET_PAGE_BITS); |
| 2870 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
| 2871 | 0xff, size >> TARGET_PAGE_BITS); |
| 2872 | |
| 2873 | if (kvm_enabled()) |
| 2874 | kvm_setup_guest_memory(new_block->host, size); |
| 2875 | |
| 2876 | return new_block->offset; |
| 2877 | } |
| 2878 | |
Alex Williamson | 1724f04 | 2010-06-25 11:09:35 -0600 | [diff] [blame] | 2879 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2880 | { |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2881 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2882 | } |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2883 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2884 | void qemu_ram_free(ram_addr_t addr) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2885 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2886 | RAMBlock *block; |
| 2887 | |
| 2888 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2889 | if (addr == block->offset) { |
| 2890 | QLIST_REMOVE(block, next); |
| 2891 | if (mem_path) { |
| 2892 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2893 | if (block->fd) { |
| 2894 | munmap(block->host, block->length); |
| 2895 | close(block->fd); |
| 2896 | } else { |
| 2897 | qemu_vfree(block->host); |
| 2898 | } |
| 2899 | #endif |
| 2900 | } else { |
| 2901 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 2902 | munmap(block->host, block->length); |
| 2903 | #else |
| 2904 | qemu_vfree(block->host); |
| 2905 | #endif |
| 2906 | } |
| 2907 | qemu_free(block); |
| 2908 | return; |
| 2909 | } |
| 2910 | } |
| 2911 | |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2912 | } |
| 2913 | |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 2914 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2915 | With the exception of the softmmu code in this file, this should |
| 2916 | only be used for local memory (e.g. video ram) that the device owns, |
| 2917 | and knows it isn't going to access beyond the end of the block. |
| 2918 | |
| 2919 | It should not be used for general purpose DMA. |
| 2920 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. |
| 2921 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2922 | void *qemu_get_ram_ptr(ram_addr_t addr) |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 2923 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2924 | RAMBlock *block; |
| 2925 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 2926 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2927 | if (addr - block->offset < block->length) { |
| 2928 | QLIST_REMOVE(block, next); |
| 2929 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); |
| 2930 | return block->host + (addr - block->offset); |
| 2931 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2932 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 2933 | |
| 2934 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 2935 | abort(); |
| 2936 | |
| 2937 | return NULL; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 2938 | } |
| 2939 | |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2940 | /* Some of the softmmu routines need to translate from a host pointer |
| 2941 | (typically a TLB entry) back to a ram offset. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2942 | ram_addr_t qemu_ram_addr_from_host(void *ptr) |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2943 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2944 | RAMBlock *block; |
| 2945 | uint8_t *host = ptr; |
| 2946 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 2947 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2948 | if (host - block->host < block->length) { |
| 2949 | return block->offset + (host - block->host); |
| 2950 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2951 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 2952 | |
| 2953 | fprintf(stderr, "Bad ram pointer %p\n", ptr); |
| 2954 | abort(); |
| 2955 | |
| 2956 | return 0; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2957 | } |
| 2958 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2959 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2960 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2961 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 2962 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2963 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 2964 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2965 | do_unassigned_access(addr, 0, 0, 0, 1); |
| 2966 | #endif |
| 2967 | return 0; |
| 2968 | } |
| 2969 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2970 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2971 | { |
| 2972 | #ifdef DEBUG_UNASSIGNED |
| 2973 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 2974 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 2975 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2976 | do_unassigned_access(addr, 0, 0, 0, 2); |
| 2977 | #endif |
| 2978 | return 0; |
| 2979 | } |
| 2980 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2981 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2982 | { |
| 2983 | #ifdef DEBUG_UNASSIGNED |
| 2984 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 2985 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 2986 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2987 | do_unassigned_access(addr, 0, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 2988 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2989 | return 0; |
| 2990 | } |
| 2991 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2992 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2993 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2994 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 2995 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 2996 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 2997 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 2998 | do_unassigned_access(addr, 1, 0, 0, 1); |
| 2999 | #endif |
| 3000 | } |
| 3001 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3002 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3003 | { |
| 3004 | #ifdef DEBUG_UNASSIGNED |
| 3005 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3006 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3007 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3008 | do_unassigned_access(addr, 1, 0, 0, 2); |
| 3009 | #endif |
| 3010 | } |
| 3011 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3012 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3013 | { |
| 3014 | #ifdef DEBUG_UNASSIGNED |
| 3015 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3016 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3017 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3018 | do_unassigned_access(addr, 1, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 3019 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3020 | } |
| 3021 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3022 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3023 | unassigned_mem_readb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3024 | unassigned_mem_readw, |
| 3025 | unassigned_mem_readl, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3026 | }; |
| 3027 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3028 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3029 | unassigned_mem_writeb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3030 | unassigned_mem_writew, |
| 3031 | unassigned_mem_writel, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3032 | }; |
| 3033 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3034 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3035 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3036 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3037 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3038 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3039 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3040 | #if !defined(CONFIG_USER_ONLY) |
| 3041 | tb_invalidate_phys_page_fast(ram_addr, 1); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3042 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3043 | #endif |
| 3044 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3045 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3046 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3047 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3048 | /* we remove the notdirty callback only if the code has been |
| 3049 | flushed */ |
| 3050 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3051 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3052 | } |
| 3053 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3054 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3055 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3056 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3057 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3058 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3059 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3060 | #if !defined(CONFIG_USER_ONLY) |
| 3061 | tb_invalidate_phys_page_fast(ram_addr, 2); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3062 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3063 | #endif |
| 3064 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3065 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3066 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3067 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3068 | /* we remove the notdirty callback only if the code has been |
| 3069 | flushed */ |
| 3070 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3071 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3072 | } |
| 3073 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3074 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3075 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3076 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3077 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3078 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3079 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3080 | #if !defined(CONFIG_USER_ONLY) |
| 3081 | tb_invalidate_phys_page_fast(ram_addr, 4); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3082 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3083 | #endif |
| 3084 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3085 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3086 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3087 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3088 | /* we remove the notdirty callback only if the code has been |
| 3089 | flushed */ |
| 3090 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3091 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3092 | } |
| 3093 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3094 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3095 | NULL, /* never used */ |
| 3096 | NULL, /* never used */ |
| 3097 | NULL, /* never used */ |
| 3098 | }; |
| 3099 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3100 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3101 | notdirty_mem_writeb, |
| 3102 | notdirty_mem_writew, |
| 3103 | notdirty_mem_writel, |
| 3104 | }; |
| 3105 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3106 | /* Generate a debug exception if a watchpoint has been hit. */ |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3107 | static void check_watchpoint(int offset, int len_mask, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3108 | { |
| 3109 | CPUState *env = cpu_single_env; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3110 | target_ulong pc, cs_base; |
| 3111 | TranslationBlock *tb; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3112 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 3113 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3114 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3115 | |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3116 | if (env->watchpoint_hit) { |
| 3117 | /* We re-entered the check after replacing the TB. Now raise |
| 3118 | * the debug interrupt so that is will trigger after the |
| 3119 | * current instruction. */ |
| 3120 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); |
| 3121 | return; |
| 3122 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3123 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3124 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3125 | if ((vaddr == (wp->vaddr & len_mask) || |
| 3126 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3127 | wp->flags |= BP_WATCHPOINT_HIT; |
| 3128 | if (!env->watchpoint_hit) { |
| 3129 | env->watchpoint_hit = wp; |
| 3130 | tb = tb_find_pc(env->mem_io_pc); |
| 3131 | if (!tb) { |
| 3132 | cpu_abort(env, "check_watchpoint: could not find TB for " |
| 3133 | "pc=%p", (void *)env->mem_io_pc); |
| 3134 | } |
| 3135 | cpu_restore_state(tb, env, env->mem_io_pc, NULL); |
| 3136 | tb_phys_invalidate(tb, -1); |
| 3137 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
| 3138 | env->exception_index = EXCP_DEBUG; |
| 3139 | } else { |
| 3140 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 3141 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); |
| 3142 | } |
| 3143 | cpu_resume_from_signal(env, NULL); |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3144 | } |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3145 | } else { |
| 3146 | wp->flags &= ~BP_WATCHPOINT_HIT; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3147 | } |
| 3148 | } |
| 3149 | } |
| 3150 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3151 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 3152 | so these check for a hit then pass through to the normal out-of-line |
| 3153 | phys routines. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3154 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3155 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3156 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3157 | return ldub_phys(addr); |
| 3158 | } |
| 3159 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3160 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3161 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3162 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3163 | return lduw_phys(addr); |
| 3164 | } |
| 3165 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3166 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3167 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3168 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3169 | return ldl_phys(addr); |
| 3170 | } |
| 3171 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3172 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3173 | uint32_t val) |
| 3174 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3175 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3176 | stb_phys(addr, val); |
| 3177 | } |
| 3178 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3179 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3180 | uint32_t val) |
| 3181 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3182 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3183 | stw_phys(addr, val); |
| 3184 | } |
| 3185 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3186 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3187 | uint32_t val) |
| 3188 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3189 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3190 | stl_phys(addr, val); |
| 3191 | } |
| 3192 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3193 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3194 | watch_mem_readb, |
| 3195 | watch_mem_readw, |
| 3196 | watch_mem_readl, |
| 3197 | }; |
| 3198 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3199 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3200 | watch_mem_writeb, |
| 3201 | watch_mem_writew, |
| 3202 | watch_mem_writel, |
| 3203 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3204 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3205 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
| 3206 | target_phys_addr_t addr, |
| 3207 | unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3208 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3209 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3210 | #if defined(DEBUG_SUBPAGE) |
| 3211 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, |
| 3212 | mmio, len, addr, idx); |
| 3213 | #endif |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3214 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3215 | addr += mmio->region_offset[idx]; |
| 3216 | idx = mmio->sub_io_index[idx]; |
| 3217 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3218 | } |
| 3219 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3220 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3221 | uint32_t value, unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3222 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3223 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3224 | #if defined(DEBUG_SUBPAGE) |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3225 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
| 3226 | __func__, mmio, len, addr, idx, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3227 | #endif |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3228 | |
| 3229 | addr += mmio->region_offset[idx]; |
| 3230 | idx = mmio->sub_io_index[idx]; |
| 3231 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3232 | } |
| 3233 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3234 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3235 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3236 | return subpage_readlen(opaque, addr, 0); |
| 3237 | } |
| 3238 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3239 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3240 | uint32_t value) |
| 3241 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3242 | subpage_writelen(opaque, addr, value, 0); |
| 3243 | } |
| 3244 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3245 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3246 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3247 | return subpage_readlen(opaque, addr, 1); |
| 3248 | } |
| 3249 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3250 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3251 | uint32_t value) |
| 3252 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3253 | subpage_writelen(opaque, addr, value, 1); |
| 3254 | } |
| 3255 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3256 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3257 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3258 | return subpage_readlen(opaque, addr, 2); |
| 3259 | } |
| 3260 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3261 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
| 3262 | uint32_t value) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3263 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3264 | subpage_writelen(opaque, addr, value, 2); |
| 3265 | } |
| 3266 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3267 | static CPUReadMemoryFunc * const subpage_read[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3268 | &subpage_readb, |
| 3269 | &subpage_readw, |
| 3270 | &subpage_readl, |
| 3271 | }; |
| 3272 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3273 | static CPUWriteMemoryFunc * const subpage_write[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3274 | &subpage_writeb, |
| 3275 | &subpage_writew, |
| 3276 | &subpage_writel, |
| 3277 | }; |
| 3278 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3279 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 3280 | ram_addr_t memory, ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3281 | { |
| 3282 | int idx, eidx; |
| 3283 | |
| 3284 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 3285 | return -1; |
| 3286 | idx = SUBPAGE_IDX(start); |
| 3287 | eidx = SUBPAGE_IDX(end); |
| 3288 | #if defined(DEBUG_SUBPAGE) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 3289 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3290 | mmio, start, end, idx, eidx, memory); |
| 3291 | #endif |
Gleb Natapov | 95c318f | 2010-07-29 10:41:45 +0300 | [diff] [blame] | 3292 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 3293 | memory = IO_MEM_UNASSIGNED; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3294 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3295 | for (; idx <= eidx; idx++) { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3296 | mmio->sub_io_index[idx] = memory; |
| 3297 | mmio->region_offset[idx] = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3298 | } |
| 3299 | |
| 3300 | return 0; |
| 3301 | } |
| 3302 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3303 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 3304 | ram_addr_t orig_memory, |
| 3305 | ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3306 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3307 | subpage_t *mmio; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3308 | int subpage_memory; |
| 3309 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3310 | mmio = qemu_mallocz(sizeof(subpage_t)); |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3311 | |
| 3312 | mmio->base = base; |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3313 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3314 | #if defined(DEBUG_SUBPAGE) |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3315 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
| 3316 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3317 | #endif |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3318 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3319 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3320 | |
| 3321 | return mmio; |
| 3322 | } |
| 3323 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3324 | static int get_free_io_mem_idx(void) |
| 3325 | { |
| 3326 | int i; |
| 3327 | |
| 3328 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) |
| 3329 | if (!io_mem_used[i]) { |
| 3330 | io_mem_used[i] = 1; |
| 3331 | return i; |
| 3332 | } |
Riku Voipio | c6703b4 | 2009-12-03 15:56:05 +0200 | [diff] [blame] | 3333 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3334 | return -1; |
| 3335 | } |
| 3336 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3337 | /* mem_read and mem_write are arrays of functions containing the |
| 3338 | function to access byte (index 0), word (index 1) and dword (index |
Paul Brook | 0b4e6e3 | 2009-04-30 18:37:55 +0100 | [diff] [blame] | 3339 | 2). Functions can be omitted with a NULL function pointer. |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 3340 | If io_index is non zero, the corresponding io zone is |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 3341 | modified. If it is zero, a new io zone is allocated. The return |
| 3342 | value can be used with cpu_register_physical_memory(). (-1) is |
| 3343 | returned if error. */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3344 | static int cpu_register_io_memory_fixed(int io_index, |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3345 | CPUReadMemoryFunc * const *mem_read, |
| 3346 | CPUWriteMemoryFunc * const *mem_write, |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3347 | void *opaque) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3348 | { |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3349 | int i; |
| 3350 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3351 | if (io_index <= 0) { |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3352 | io_index = get_free_io_mem_idx(); |
| 3353 | if (io_index == -1) |
| 3354 | return io_index; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3355 | } else { |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3356 | io_index >>= IO_MEM_SHIFT; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3357 | if (io_index >= IO_MEM_NB_ENTRIES) |
| 3358 | return -1; |
| 3359 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3360 | |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3361 | for (i = 0; i < 3; ++i) { |
| 3362 | io_mem_read[io_index][i] |
| 3363 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); |
| 3364 | } |
| 3365 | for (i = 0; i < 3; ++i) { |
| 3366 | io_mem_write[io_index][i] |
| 3367 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); |
| 3368 | } |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 3369 | io_mem_opaque[io_index] = opaque; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3370 | |
| 3371 | return (io_index << IO_MEM_SHIFT); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3372 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3373 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3374 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
| 3375 | CPUWriteMemoryFunc * const *mem_write, |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3376 | void *opaque) |
| 3377 | { |
| 3378 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque); |
| 3379 | } |
| 3380 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3381 | void cpu_unregister_io_memory(int io_table_address) |
| 3382 | { |
| 3383 | int i; |
| 3384 | int io_index = io_table_address >> IO_MEM_SHIFT; |
| 3385 | |
| 3386 | for (i=0;i < 3; i++) { |
| 3387 | io_mem_read[io_index][i] = unassigned_mem_read[i]; |
| 3388 | io_mem_write[io_index][i] = unassigned_mem_write[i]; |
| 3389 | } |
| 3390 | io_mem_opaque[io_index] = NULL; |
| 3391 | io_mem_used[io_index] = 0; |
| 3392 | } |
| 3393 | |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3394 | static void io_mem_init(void) |
| 3395 | { |
| 3396 | int i; |
| 3397 | |
| 3398 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL); |
| 3399 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL); |
| 3400 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL); |
| 3401 | for (i=0; i<5; i++) |
| 3402 | io_mem_used[i] = 1; |
| 3403 | |
| 3404 | io_mem_watch = cpu_register_io_memory(watch_mem_read, |
| 3405 | watch_mem_write, NULL); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3406 | } |
| 3407 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 3408 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 3409 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3410 | /* physical memory access (slow version, mainly for debug) */ |
| 3411 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3412 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 3413 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3414 | { |
| 3415 | int l, flags; |
| 3416 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 3417 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3418 | |
| 3419 | while (len > 0) { |
| 3420 | page = addr & TARGET_PAGE_MASK; |
| 3421 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3422 | if (l > len) |
| 3423 | l = len; |
| 3424 | flags = page_get_flags(page); |
| 3425 | if (!(flags & PAGE_VALID)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3426 | return -1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3427 | if (is_write) { |
| 3428 | if (!(flags & PAGE_WRITE)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3429 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3430 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3431 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3432 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3433 | memcpy(p, buf, l); |
| 3434 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3435 | } else { |
| 3436 | if (!(flags & PAGE_READ)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3437 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3438 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3439 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3440 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3441 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 3442 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3443 | } |
| 3444 | len -= l; |
| 3445 | buf += l; |
| 3446 | addr += l; |
| 3447 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3448 | return 0; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3449 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3450 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3451 | #else |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3452 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3453 | int len, int is_write) |
| 3454 | { |
| 3455 | int l, io_index; |
| 3456 | uint8_t *ptr; |
| 3457 | uint32_t val; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3458 | target_phys_addr_t page; |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 3459 | unsigned long pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3460 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3461 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3462 | while (len > 0) { |
| 3463 | page = addr & TARGET_PAGE_MASK; |
| 3464 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3465 | if (l > len) |
| 3466 | l = len; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3467 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3468 | if (!p) { |
| 3469 | pd = IO_MEM_UNASSIGNED; |
| 3470 | } else { |
| 3471 | pd = p->phys_offset; |
| 3472 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3473 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3474 | if (is_write) { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3475 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3476 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3477 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3478 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3479 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 3480 | /* XXX: could force cpu_single_env to NULL to avoid |
| 3481 | potential bugs */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3482 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3483 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3484 | val = ldl_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3485 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3486 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3487 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3488 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3489 | val = lduw_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3490 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3491 | l = 2; |
| 3492 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3493 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3494 | val = ldub_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3495 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3496 | l = 1; |
| 3497 | } |
| 3498 | } else { |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3499 | unsigned long addr1; |
| 3500 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3501 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3502 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3503 | memcpy(ptr, buf, l); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3504 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3505 | /* invalidate code */ |
| 3506 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 3507 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3508 | cpu_physical_memory_set_dirty_flags( |
| 3509 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3510 | } |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3511 | } |
| 3512 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3513 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3514 | !(pd & IO_MEM_ROMD)) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3515 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3516 | /* I/O case */ |
| 3517 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3518 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3519 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 3520 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3521 | /* 32 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3522 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3523 | stl_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3524 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3525 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3526 | /* 16 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3527 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3528 | stw_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3529 | l = 2; |
| 3530 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3531 | /* 8 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3532 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3533 | stb_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3534 | l = 1; |
| 3535 | } |
| 3536 | } else { |
| 3537 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3538 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3539 | (addr & ~TARGET_PAGE_MASK); |
| 3540 | memcpy(buf, ptr, l); |
| 3541 | } |
| 3542 | } |
| 3543 | len -= l; |
| 3544 | buf += l; |
| 3545 | addr += l; |
| 3546 | } |
| 3547 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3548 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3549 | /* used for ROM loading : can write in RAM and ROM */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3550 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3551 | const uint8_t *buf, int len) |
| 3552 | { |
| 3553 | int l; |
| 3554 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3555 | target_phys_addr_t page; |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3556 | unsigned long pd; |
| 3557 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3558 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3559 | while (len > 0) { |
| 3560 | page = addr & TARGET_PAGE_MASK; |
| 3561 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3562 | if (l > len) |
| 3563 | l = len; |
| 3564 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 3565 | if (!p) { |
| 3566 | pd = IO_MEM_UNASSIGNED; |
| 3567 | } else { |
| 3568 | pd = p->phys_offset; |
| 3569 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3570 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3571 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3572 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
| 3573 | !(pd & IO_MEM_ROMD)) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3574 | /* do nothing */ |
| 3575 | } else { |
| 3576 | unsigned long addr1; |
| 3577 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3578 | /* ROM/RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3579 | ptr = qemu_get_ram_ptr(addr1); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3580 | memcpy(ptr, buf, l); |
| 3581 | } |
| 3582 | len -= l; |
| 3583 | buf += l; |
| 3584 | addr += l; |
| 3585 | } |
| 3586 | } |
| 3587 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3588 | typedef struct { |
| 3589 | void *buffer; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3590 | target_phys_addr_t addr; |
| 3591 | target_phys_addr_t len; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3592 | } BounceBuffer; |
| 3593 | |
| 3594 | static BounceBuffer bounce; |
| 3595 | |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3596 | typedef struct MapClient { |
| 3597 | void *opaque; |
| 3598 | void (*callback)(void *opaque); |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3599 | QLIST_ENTRY(MapClient) link; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3600 | } MapClient; |
| 3601 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3602 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
| 3603 | = QLIST_HEAD_INITIALIZER(map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3604 | |
| 3605 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 3606 | { |
| 3607 | MapClient *client = qemu_malloc(sizeof(*client)); |
| 3608 | |
| 3609 | client->opaque = opaque; |
| 3610 | client->callback = callback; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3611 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3612 | return client; |
| 3613 | } |
| 3614 | |
| 3615 | void cpu_unregister_map_client(void *_client) |
| 3616 | { |
| 3617 | MapClient *client = (MapClient *)_client; |
| 3618 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3619 | QLIST_REMOVE(client, link); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 3620 | qemu_free(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3621 | } |
| 3622 | |
| 3623 | static void cpu_notify_map_clients(void) |
| 3624 | { |
| 3625 | MapClient *client; |
| 3626 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3627 | while (!QLIST_EMPTY(&map_client_list)) { |
| 3628 | client = QLIST_FIRST(&map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3629 | client->callback(client->opaque); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 3630 | cpu_unregister_map_client(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3631 | } |
| 3632 | } |
| 3633 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3634 | /* Map a physical memory region into a host virtual address. |
| 3635 | * May map a subset of the requested range, given by and returned in *plen. |
| 3636 | * May return NULL if resources needed to perform the mapping are exhausted. |
| 3637 | * Use only for reads OR writes - not for read-modify-write operations. |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3638 | * Use cpu_register_map_client() to know when retrying the map operation is |
| 3639 | * likely to succeed. |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3640 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3641 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
| 3642 | target_phys_addr_t *plen, |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3643 | int is_write) |
| 3644 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3645 | target_phys_addr_t len = *plen; |
| 3646 | target_phys_addr_t done = 0; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3647 | int l; |
| 3648 | uint8_t *ret = NULL; |
| 3649 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3650 | target_phys_addr_t page; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3651 | unsigned long pd; |
| 3652 | PhysPageDesc *p; |
| 3653 | unsigned long addr1; |
| 3654 | |
| 3655 | while (len > 0) { |
| 3656 | page = addr & TARGET_PAGE_MASK; |
| 3657 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3658 | if (l > len) |
| 3659 | l = len; |
| 3660 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 3661 | if (!p) { |
| 3662 | pd = IO_MEM_UNASSIGNED; |
| 3663 | } else { |
| 3664 | pd = p->phys_offset; |
| 3665 | } |
| 3666 | |
| 3667 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 3668 | if (done || bounce.buffer) { |
| 3669 | break; |
| 3670 | } |
| 3671 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); |
| 3672 | bounce.addr = addr; |
| 3673 | bounce.len = l; |
| 3674 | if (!is_write) { |
| 3675 | cpu_physical_memory_rw(addr, bounce.buffer, l, 0); |
| 3676 | } |
| 3677 | ptr = bounce.buffer; |
| 3678 | } else { |
| 3679 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3680 | ptr = qemu_get_ram_ptr(addr1); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3681 | } |
| 3682 | if (!done) { |
| 3683 | ret = ptr; |
| 3684 | } else if (ret + done != ptr) { |
| 3685 | break; |
| 3686 | } |
| 3687 | |
| 3688 | len -= l; |
| 3689 | addr += l; |
| 3690 | done += l; |
| 3691 | } |
| 3692 | *plen = done; |
| 3693 | return ret; |
| 3694 | } |
| 3695 | |
| 3696 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). |
| 3697 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
| 3698 | * the amount of memory that was actually read or written by the caller. |
| 3699 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3700 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
| 3701 | int is_write, target_phys_addr_t access_len) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3702 | { |
| 3703 | if (buffer != bounce.buffer) { |
| 3704 | if (is_write) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3705 | ram_addr_t addr1 = qemu_ram_addr_from_host(buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3706 | while (access_len) { |
| 3707 | unsigned l; |
| 3708 | l = TARGET_PAGE_SIZE; |
| 3709 | if (l > access_len) |
| 3710 | l = access_len; |
| 3711 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3712 | /* invalidate code */ |
| 3713 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 3714 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3715 | cpu_physical_memory_set_dirty_flags( |
| 3716 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3717 | } |
| 3718 | addr1 += l; |
| 3719 | access_len -= l; |
| 3720 | } |
| 3721 | } |
| 3722 | return; |
| 3723 | } |
| 3724 | if (is_write) { |
| 3725 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); |
| 3726 | } |
Herve Poussineau | f8a8324 | 2010-01-24 21:23:56 +0000 | [diff] [blame] | 3727 | qemu_vfree(bounce.buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3728 | bounce.buffer = NULL; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3729 | cpu_notify_map_clients(); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3730 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3731 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3732 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3733 | uint32_t ldl_phys(target_phys_addr_t addr) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3734 | { |
| 3735 | int io_index; |
| 3736 | uint8_t *ptr; |
| 3737 | uint32_t val; |
| 3738 | unsigned long pd; |
| 3739 | PhysPageDesc *p; |
| 3740 | |
| 3741 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3742 | if (!p) { |
| 3743 | pd = IO_MEM_UNASSIGNED; |
| 3744 | } else { |
| 3745 | pd = p->phys_offset; |
| 3746 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3747 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3748 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3749 | !(pd & IO_MEM_ROMD)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3750 | /* I/O case */ |
| 3751 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3752 | if (p) |
| 3753 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3754 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 3755 | } else { |
| 3756 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3757 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3758 | (addr & ~TARGET_PAGE_MASK); |
| 3759 | val = ldl_p(ptr); |
| 3760 | } |
| 3761 | return val; |
| 3762 | } |
| 3763 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3764 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3765 | uint64_t ldq_phys(target_phys_addr_t addr) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3766 | { |
| 3767 | int io_index; |
| 3768 | uint8_t *ptr; |
| 3769 | uint64_t val; |
| 3770 | unsigned long pd; |
| 3771 | PhysPageDesc *p; |
| 3772 | |
| 3773 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3774 | if (!p) { |
| 3775 | pd = IO_MEM_UNASSIGNED; |
| 3776 | } else { |
| 3777 | pd = p->phys_offset; |
| 3778 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3779 | |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3780 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 3781 | !(pd & IO_MEM_ROMD)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3782 | /* I/O case */ |
| 3783 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3784 | if (p) |
| 3785 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3786 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3787 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; |
| 3788 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); |
| 3789 | #else |
| 3790 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 3791 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; |
| 3792 | #endif |
| 3793 | } else { |
| 3794 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3795 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 3796 | (addr & ~TARGET_PAGE_MASK); |
| 3797 | val = ldq_p(ptr); |
| 3798 | } |
| 3799 | return val; |
| 3800 | } |
| 3801 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3802 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3803 | uint32_t ldub_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3804 | { |
| 3805 | uint8_t val; |
| 3806 | cpu_physical_memory_read(addr, &val, 1); |
| 3807 | return val; |
| 3808 | } |
| 3809 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3810 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3811 | uint32_t lduw_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3812 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3813 | int io_index; |
| 3814 | uint8_t *ptr; |
| 3815 | uint64_t val; |
| 3816 | unsigned long pd; |
| 3817 | PhysPageDesc *p; |
| 3818 | |
| 3819 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3820 | if (!p) { |
| 3821 | pd = IO_MEM_UNASSIGNED; |
| 3822 | } else { |
| 3823 | pd = p->phys_offset; |
| 3824 | } |
| 3825 | |
| 3826 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 3827 | !(pd & IO_MEM_ROMD)) { |
| 3828 | /* I/O case */ |
| 3829 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3830 | if (p) |
| 3831 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 3832 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
| 3833 | } else { |
| 3834 | /* RAM case */ |
| 3835 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
| 3836 | (addr & ~TARGET_PAGE_MASK); |
| 3837 | val = lduw_p(ptr); |
| 3838 | } |
| 3839 | return val; |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3840 | } |
| 3841 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3842 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 3843 | and the code inside is not invalidated. It is useful if the dirty |
| 3844 | bits are used to track modified PTEs */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3845 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3846 | { |
| 3847 | int io_index; |
| 3848 | uint8_t *ptr; |
| 3849 | unsigned long pd; |
| 3850 | PhysPageDesc *p; |
| 3851 | |
| 3852 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3853 | if (!p) { |
| 3854 | pd = IO_MEM_UNASSIGNED; |
| 3855 | } else { |
| 3856 | pd = p->phys_offset; |
| 3857 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3858 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3859 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3860 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3861 | if (p) |
| 3862 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3863 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3864 | } else { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 3865 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3866 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3867 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 3868 | |
| 3869 | if (unlikely(in_migration)) { |
| 3870 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3871 | /* invalidate code */ |
| 3872 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 3873 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3874 | cpu_physical_memory_set_dirty_flags( |
| 3875 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 3876 | } |
| 3877 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3878 | } |
| 3879 | } |
| 3880 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3881 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3882 | { |
| 3883 | int io_index; |
| 3884 | uint8_t *ptr; |
| 3885 | unsigned long pd; |
| 3886 | PhysPageDesc *p; |
| 3887 | |
| 3888 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3889 | if (!p) { |
| 3890 | pd = IO_MEM_UNASSIGNED; |
| 3891 | } else { |
| 3892 | pd = p->phys_offset; |
| 3893 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3894 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3895 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 3896 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3897 | if (p) |
| 3898 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3899 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3900 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); |
| 3901 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); |
| 3902 | #else |
| 3903 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3904 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); |
| 3905 | #endif |
| 3906 | } else { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3907 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 3908 | (addr & ~TARGET_PAGE_MASK); |
| 3909 | stq_p(ptr, val); |
| 3910 | } |
| 3911 | } |
| 3912 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3913 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3914 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3915 | { |
| 3916 | int io_index; |
| 3917 | uint8_t *ptr; |
| 3918 | unsigned long pd; |
| 3919 | PhysPageDesc *p; |
| 3920 | |
| 3921 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3922 | if (!p) { |
| 3923 | pd = IO_MEM_UNASSIGNED; |
| 3924 | } else { |
| 3925 | pd = p->phys_offset; |
| 3926 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3927 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3928 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3929 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3930 | if (p) |
| 3931 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3932 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 3933 | } else { |
| 3934 | unsigned long addr1; |
| 3935 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3936 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3937 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3938 | stl_p(ptr, val); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3939 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3940 | /* invalidate code */ |
| 3941 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 3942 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3943 | cpu_physical_memory_set_dirty_flags(addr1, |
| 3944 | (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3945 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3946 | } |
| 3947 | } |
| 3948 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3949 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3950 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3951 | { |
| 3952 | uint8_t v = val; |
| 3953 | cpu_physical_memory_write(addr, &v, 1); |
| 3954 | } |
| 3955 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3956 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3957 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3958 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 3959 | int io_index; |
| 3960 | uint8_t *ptr; |
| 3961 | unsigned long pd; |
| 3962 | PhysPageDesc *p; |
| 3963 | |
| 3964 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 3965 | if (!p) { |
| 3966 | pd = IO_MEM_UNASSIGNED; |
| 3967 | } else { |
| 3968 | pd = p->phys_offset; |
| 3969 | } |
| 3970 | |
| 3971 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 3972 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 3973 | if (p) |
| 3974 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 3975 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
| 3976 | } else { |
| 3977 | unsigned long addr1; |
| 3978 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3979 | /* RAM case */ |
| 3980 | ptr = qemu_get_ram_ptr(addr1); |
| 3981 | stw_p(ptr, val); |
| 3982 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3983 | /* invalidate code */ |
| 3984 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); |
| 3985 | /* set dirty bit */ |
| 3986 | cpu_physical_memory_set_dirty_flags(addr1, |
| 3987 | (0xff & ~CODE_DIRTY_FLAG)); |
| 3988 | } |
| 3989 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3990 | } |
| 3991 | |
| 3992 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3993 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 3994 | { |
| 3995 | val = tswap64(val); |
| 3996 | cpu_physical_memory_write(addr, (const uint8_t *)&val, 8); |
| 3997 | } |
| 3998 | |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 3999 | /* virtual memory access for debug (includes writing to ROM) */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4000 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 4001 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4002 | { |
| 4003 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4004 | target_phys_addr_t phys_addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 4005 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4006 | |
| 4007 | while (len > 0) { |
| 4008 | page = addr & TARGET_PAGE_MASK; |
| 4009 | phys_addr = cpu_get_phys_page_debug(env, page); |
| 4010 | /* if no physical page mapped, return an error */ |
| 4011 | if (phys_addr == -1) |
| 4012 | return -1; |
| 4013 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4014 | if (l > len) |
| 4015 | l = len; |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4016 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4017 | if (is_write) |
| 4018 | cpu_physical_memory_write_rom(phys_addr, buf, l); |
| 4019 | else |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4020 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4021 | len -= l; |
| 4022 | buf += l; |
| 4023 | addr += l; |
| 4024 | } |
| 4025 | return 0; |
| 4026 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 4027 | #endif |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4028 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4029 | /* in deterministic execution mode, instructions doing device I/Os |
| 4030 | must be at the end of the TB */ |
| 4031 | void cpu_io_recompile(CPUState *env, void *retaddr) |
| 4032 | { |
| 4033 | TranslationBlock *tb; |
| 4034 | uint32_t n, cflags; |
| 4035 | target_ulong pc, cs_base; |
| 4036 | uint64_t flags; |
| 4037 | |
| 4038 | tb = tb_find_pc((unsigned long)retaddr); |
| 4039 | if (!tb) { |
| 4040 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", |
| 4041 | retaddr); |
| 4042 | } |
| 4043 | n = env->icount_decr.u16.low + tb->icount; |
| 4044 | cpu_restore_state(tb, env, (unsigned long)retaddr, NULL); |
| 4045 | /* Calculate how many instructions had been executed before the fault |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4046 | occurred. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4047 | n = n - env->icount_decr.u16.low; |
| 4048 | /* Generate a new TB ending on the I/O insn. */ |
| 4049 | n++; |
| 4050 | /* On MIPS and SH, delay slot instructions can only be restarted if |
| 4051 | they were already the first instruction in the TB. If this is not |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4052 | the first instruction in a TB then re-execute the preceding |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4053 | branch. */ |
| 4054 | #if defined(TARGET_MIPS) |
| 4055 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { |
| 4056 | env->active_tc.PC -= 4; |
| 4057 | env->icount_decr.u16.low++; |
| 4058 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 4059 | } |
| 4060 | #elif defined(TARGET_SH4) |
| 4061 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
| 4062 | && n > 1) { |
| 4063 | env->pc -= 2; |
| 4064 | env->icount_decr.u16.low++; |
| 4065 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 4066 | } |
| 4067 | #endif |
| 4068 | /* This should never happen. */ |
| 4069 | if (n > CF_COUNT_MASK) |
| 4070 | cpu_abort(env, "TB too big during recompile"); |
| 4071 | |
| 4072 | cflags = n | CF_LAST_IO; |
| 4073 | pc = tb->pc; |
| 4074 | cs_base = tb->cs_base; |
| 4075 | flags = tb->flags; |
| 4076 | tb_phys_invalidate(tb, -1); |
| 4077 | /* FIXME: In theory this could raise an exception. In practice |
| 4078 | we have already translated the block once so it's probably ok. */ |
| 4079 | tb_gen_code(env, pc, cs_base, flags, cflags); |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4080 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4081 | the first in the TB) then we end up generating a whole new TB and |
| 4082 | repeating the fault, which is horribly inefficient. |
| 4083 | Better would be to execute just this insn uncached, or generate a |
| 4084 | second new TB. */ |
| 4085 | cpu_resume_from_signal(env, NULL); |
| 4086 | } |
| 4087 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 4088 | #if !defined(CONFIG_USER_ONLY) |
| 4089 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4090 | void dump_exec_info(FILE *f, |
| 4091 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| 4092 | { |
| 4093 | int i, target_code_size, max_target_code_size; |
| 4094 | int direct_jmp_count, direct_jmp2_count, cross_page; |
| 4095 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4096 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4097 | target_code_size = 0; |
| 4098 | max_target_code_size = 0; |
| 4099 | cross_page = 0; |
| 4100 | direct_jmp_count = 0; |
| 4101 | direct_jmp2_count = 0; |
| 4102 | for(i = 0; i < nb_tbs; i++) { |
| 4103 | tb = &tbs[i]; |
| 4104 | target_code_size += tb->size; |
| 4105 | if (tb->size > max_target_code_size) |
| 4106 | max_target_code_size = tb->size; |
| 4107 | if (tb->page_addr[1] != -1) |
| 4108 | cross_page++; |
| 4109 | if (tb->tb_next_offset[0] != 0xffff) { |
| 4110 | direct_jmp_count++; |
| 4111 | if (tb->tb_next_offset[1] != 0xffff) { |
| 4112 | direct_jmp2_count++; |
| 4113 | } |
| 4114 | } |
| 4115 | } |
| 4116 | /* XXX: avoid using doubles ? */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4117 | cpu_fprintf(f, "Translation buffer state:\n"); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 4118 | cpu_fprintf(f, "gen code size %ld/%ld\n", |
| 4119 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
| 4120 | cpu_fprintf(f, "TB count %d/%d\n", |
| 4121 | nb_tbs, code_gen_max_blocks); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4122 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4123 | nb_tbs ? target_code_size / nb_tbs : 0, |
| 4124 | max_target_code_size); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4125 | cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4126 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
| 4127 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4128 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
| 4129 | cross_page, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4130 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
| 4131 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4132 | direct_jmp_count, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4133 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
| 4134 | direct_jmp2_count, |
| 4135 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4136 | cpu_fprintf(f, "\nStatistics:\n"); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4137 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
| 4138 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); |
| 4139 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 4140 | tcg_dump_info(f, cpu_fprintf); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4141 | } |
| 4142 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4143 | #define MMUSUFFIX _cmmu |
| 4144 | #define GETPC() NULL |
| 4145 | #define env cpu_single_env |
bellard | b769d8f | 2004-10-03 15:07:13 +0000 | [diff] [blame] | 4146 | #define SOFTMMU_CODE_ACCESS |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4147 | |
| 4148 | #define SHIFT 0 |
| 4149 | #include "softmmu_template.h" |
| 4150 | |
| 4151 | #define SHIFT 1 |
| 4152 | #include "softmmu_template.h" |
| 4153 | |
| 4154 | #define SHIFT 2 |
| 4155 | #include "softmmu_template.h" |
| 4156 | |
| 4157 | #define SHIFT 3 |
| 4158 | #include "softmmu_template.h" |
| 4159 | |
| 4160 | #undef env |
| 4161 | |
| 4162 | #endif |