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bellard54936002003-05-13 00:25:15 +00001/*
bellardfd6ce8f2003-05-14 19:00:11 +00002 * virtual page mapping and translated block handling
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard54936002003-05-13 00:25:15 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard54936002003-05-13 00:25:15 +000018 */
bellard67b915a2004-03-31 23:37:16 +000019#include "config.h"
bellardd5a8f072004-09-29 21:15:28 +000020#ifdef _WIN32
21#include <windows.h>
22#else
bellarda98d49b2004-11-14 16:22:05 +000023#include <sys/types.h>
bellardd5a8f072004-09-29 21:15:28 +000024#include <sys/mman.h>
25#endif
bellard54936002003-05-13 00:25:15 +000026#include <stdlib.h>
27#include <stdio.h>
28#include <stdarg.h>
29#include <string.h>
30#include <errno.h>
31#include <unistd.h>
32#include <inttypes.h>
33
bellard6180a182003-09-30 21:04:53 +000034#include "cpu.h"
35#include "exec-all.h"
aurel32ca10f862008-04-11 21:35:42 +000036#include "qemu-common.h"
bellardb67d9a52008-05-23 09:57:34 +000037#include "tcg.h"
pbrookb3c77242008-06-30 16:31:04 +000038#include "hw/hw.h"
Alex Williamsoncc9e98c2010-06-25 11:09:43 -060039#include "hw/qdev.h"
aliguori74576192008-10-06 14:02:03 +000040#include "osdep.h"
aliguori7ba1e612008-11-05 16:04:33 +000041#include "kvm.h"
Blue Swirl29e922b2010-03-29 19:24:00 +000042#include "qemu-timer.h"
pbrook53a59602006-03-25 19:31:22 +000043#if defined(CONFIG_USER_ONLY)
44#include <qemu.h>
Riku Voipiofd052bf2010-01-25 14:30:49 +020045#include <signal.h>
Juergen Lockf01576f2010-03-25 22:32:16 +010046#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
47#include <sys/param.h>
48#if __FreeBSD_version >= 700104
49#define HAVE_KINFO_GETVMMAP
50#define sigqueue sigqueue_freebsd /* avoid redefinition */
51#include <sys/time.h>
52#include <sys/proc.h>
53#include <machine/profile.h>
54#define _KERNEL
55#include <sys/user.h>
56#undef _KERNEL
57#undef sigqueue
58#include <libutil.h>
59#endif
60#endif
pbrook53a59602006-03-25 19:31:22 +000061#endif
bellard54936002003-05-13 00:25:15 +000062
bellardfd6ce8f2003-05-14 19:00:11 +000063//#define DEBUG_TB_INVALIDATE
bellard66e85a22003-06-24 13:28:12 +000064//#define DEBUG_FLUSH
bellard9fa3e852004-01-04 18:06:42 +000065//#define DEBUG_TLB
pbrook67d3b952006-12-18 05:03:52 +000066//#define DEBUG_UNASSIGNED
bellardfd6ce8f2003-05-14 19:00:11 +000067
68/* make various TB consistency checks */
ths5fafdf22007-09-16 21:08:06 +000069//#define DEBUG_TB_CHECK
70//#define DEBUG_TLB_CHECK
bellardfd6ce8f2003-05-14 19:00:11 +000071
ths1196be32007-03-17 15:17:58 +000072//#define DEBUG_IOPORT
blueswir1db7b5422007-05-26 17:36:03 +000073//#define DEBUG_SUBPAGE
ths1196be32007-03-17 15:17:58 +000074
pbrook99773bd2006-04-16 15:14:59 +000075#if !defined(CONFIG_USER_ONLY)
76/* TB consistency checks only implemented for usermode emulation. */
77#undef DEBUG_TB_CHECK
78#endif
79
bellard9fa3e852004-01-04 18:06:42 +000080#define SMC_BITMAP_USE_THRESHOLD 10
81
blueswir1bdaf78e2008-10-04 07:24:27 +000082static TranslationBlock *tbs;
Stefan Weil24ab68a2010-07-19 18:23:17 +020083static int code_gen_max_blocks;
bellard9fa3e852004-01-04 18:06:42 +000084TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
blueswir1bdaf78e2008-10-04 07:24:27 +000085static int nb_tbs;
bellardeb51d102003-05-14 21:51:13 +000086/* any access to the tbs or the page table must use this lock */
Anthony Liguoric227f092009-10-01 16:12:16 -050087spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
bellardfd6ce8f2003-05-14 19:00:11 +000088
blueswir1141ac462008-07-26 15:05:57 +000089#if defined(__arm__) || defined(__sparc_v9__)
90/* The prologue must be reachable with a direct jump. ARM and Sparc64
91 have limited branch ranges (possibly also PPC) so place it in a
blueswir1d03d8602008-07-10 17:21:31 +000092 section close to code segment. */
93#define code_gen_section \
94 __attribute__((__section__(".gen_code"))) \
95 __attribute__((aligned (32)))
Stefan Weilf8e2af12009-06-18 23:04:48 +020096#elif defined(_WIN32)
97/* Maximum alignment for Win32 is 16. */
98#define code_gen_section \
99 __attribute__((aligned (16)))
blueswir1d03d8602008-07-10 17:21:31 +0000100#else
101#define code_gen_section \
102 __attribute__((aligned (32)))
103#endif
104
105uint8_t code_gen_prologue[1024] code_gen_section;
blueswir1bdaf78e2008-10-04 07:24:27 +0000106static uint8_t *code_gen_buffer;
107static unsigned long code_gen_buffer_size;
bellard26a5f132008-05-28 12:30:31 +0000108/* threshold to flush the translated code buffer */
blueswir1bdaf78e2008-10-04 07:24:27 +0000109static unsigned long code_gen_buffer_max_size;
Stefan Weil24ab68a2010-07-19 18:23:17 +0200110static uint8_t *code_gen_ptr;
bellardfd6ce8f2003-05-14 19:00:11 +0000111
pbrooke2eef172008-06-08 01:09:01 +0000112#if !defined(CONFIG_USER_ONLY)
bellard9fa3e852004-01-04 18:06:42 +0000113int phys_ram_fd;
aliguori74576192008-10-06 14:02:03 +0000114static int in_migration;
pbrook94a6b542009-04-11 17:15:54 +0000115
Alex Williamsonf471a172010-06-11 11:11:42 -0600116RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) };
pbrooke2eef172008-06-08 01:09:01 +0000117#endif
bellard9fa3e852004-01-04 18:06:42 +0000118
bellard6a00d602005-11-21 23:25:50 +0000119CPUState *first_cpu;
120/* current CPU in the current thread. It is only valid inside
121 cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000122CPUState *cpu_single_env;
pbrook2e70f6e2008-06-29 01:03:05 +0000123/* 0 = Do not count executed instructions.
thsbf20dc02008-06-30 17:22:19 +0000124 1 = Precise instruction counting.
pbrook2e70f6e2008-06-29 01:03:05 +0000125 2 = Adaptive rate instruction counting. */
126int use_icount = 0;
127/* Current instruction counter. While executing translated code this may
128 include some instructions that have not yet been executed. */
129int64_t qemu_icount;
bellard6a00d602005-11-21 23:25:50 +0000130
bellard54936002003-05-13 00:25:15 +0000131typedef struct PageDesc {
bellard92e873b2004-05-21 14:52:29 +0000132 /* list of TBs intersecting this ram page */
bellardfd6ce8f2003-05-14 19:00:11 +0000133 TranslationBlock *first_tb;
bellard9fa3e852004-01-04 18:06:42 +0000134 /* in order to optimize self modifying code, we count the number
135 of lookups we do to a given page to use a bitmap */
136 unsigned int code_write_count;
137 uint8_t *code_bitmap;
138#if defined(CONFIG_USER_ONLY)
139 unsigned long flags;
140#endif
bellard54936002003-05-13 00:25:15 +0000141} PageDesc;
142
Paul Brook41c1b1c2010-03-12 16:54:58 +0000143/* In system mode we want L1_MAP to be based on ram offsets,
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800144 while in user mode we want it to be based on virtual addresses. */
145#if !defined(CONFIG_USER_ONLY)
Paul Brook41c1b1c2010-03-12 16:54:58 +0000146#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
147# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
148#else
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800149# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
Paul Brook41c1b1c2010-03-12 16:54:58 +0000150#endif
j_mayerbedb69e2007-04-05 20:08:21 +0000151#else
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800152# define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
j_mayerbedb69e2007-04-05 20:08:21 +0000153#endif
bellard54936002003-05-13 00:25:15 +0000154
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800155/* Size of the L2 (and L3, etc) page tables. */
156#define L2_BITS 10
bellard54936002003-05-13 00:25:15 +0000157#define L2_SIZE (1 << L2_BITS)
158
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800159/* The bits remaining after N lower levels of page tables. */
160#define P_L1_BITS_REM \
161 ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
162#define V_L1_BITS_REM \
163 ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS)
164
165/* Size of the L1 page table. Avoid silly small sizes. */
166#if P_L1_BITS_REM < 4
167#define P_L1_BITS (P_L1_BITS_REM + L2_BITS)
168#else
169#define P_L1_BITS P_L1_BITS_REM
170#endif
171
172#if V_L1_BITS_REM < 4
173#define V_L1_BITS (V_L1_BITS_REM + L2_BITS)
174#else
175#define V_L1_BITS V_L1_BITS_REM
176#endif
177
178#define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS)
179#define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
180
181#define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
182#define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
183
bellard83fb7ad2004-07-05 21:25:26 +0000184unsigned long qemu_real_host_page_size;
185unsigned long qemu_host_page_bits;
186unsigned long qemu_host_page_size;
187unsigned long qemu_host_page_mask;
bellard54936002003-05-13 00:25:15 +0000188
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800189/* This is a multi-level map on the virtual address space.
190 The bottom level has pointers to PageDesc. */
191static void *l1_map[V_L1_SIZE];
bellard54936002003-05-13 00:25:15 +0000192
pbrooke2eef172008-06-08 01:09:01 +0000193#if !defined(CONFIG_USER_ONLY)
Paul Brook41c1b1c2010-03-12 16:54:58 +0000194typedef struct PhysPageDesc {
195 /* offset in host memory of the page + io_index in the low bits */
196 ram_addr_t phys_offset;
197 ram_addr_t region_offset;
198} PhysPageDesc;
199
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800200/* This is a multi-level map on the physical address space.
201 The bottom level has pointers to PhysPageDesc. */
202static void *l1_phys_map[P_L1_SIZE];
Paul Brook6d9a1302010-02-28 23:55:53 +0000203
pbrooke2eef172008-06-08 01:09:01 +0000204static void io_mem_init(void);
205
bellard33417e72003-08-10 21:47:01 +0000206/* io memory support */
bellard33417e72003-08-10 21:47:01 +0000207CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
208CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
bellarda4193c82004-06-03 14:01:43 +0000209void *io_mem_opaque[IO_MEM_NB_ENTRIES];
blueswir1511d2b12009-03-07 15:32:56 +0000210static char io_mem_used[IO_MEM_NB_ENTRIES];
pbrook6658ffb2007-03-16 23:58:11 +0000211static int io_mem_watch;
212#endif
bellard33417e72003-08-10 21:47:01 +0000213
bellard34865132003-10-05 14:28:56 +0000214/* log support */
Juha Riihimäki1e8b27c2009-12-03 15:56:02 +0200215#ifdef WIN32
216static const char *logfilename = "qemu.log";
217#else
blueswir1d9b630f2008-10-05 09:57:08 +0000218static const char *logfilename = "/tmp/qemu.log";
Juha Riihimäki1e8b27c2009-12-03 15:56:02 +0200219#endif
bellard34865132003-10-05 14:28:56 +0000220FILE *logfile;
221int loglevel;
pbrooke735b912007-06-30 13:53:24 +0000222static int log_append = 0;
bellard34865132003-10-05 14:28:56 +0000223
bellarde3db7222005-01-26 22:00:47 +0000224/* statistics */
Paul Brookb3755a92010-03-12 16:54:58 +0000225#if !defined(CONFIG_USER_ONLY)
bellarde3db7222005-01-26 22:00:47 +0000226static int tlb_flush_count;
Paul Brookb3755a92010-03-12 16:54:58 +0000227#endif
bellarde3db7222005-01-26 22:00:47 +0000228static int tb_flush_count;
229static int tb_phys_invalidate_count;
230
bellard7cb69ca2008-05-10 10:55:51 +0000231#ifdef _WIN32
232static void map_exec(void *addr, long size)
233{
234 DWORD old_protect;
235 VirtualProtect(addr, size,
236 PAGE_EXECUTE_READWRITE, &old_protect);
237
238}
239#else
240static void map_exec(void *addr, long size)
241{
bellard43694152008-05-29 09:35:57 +0000242 unsigned long start, end, page_size;
bellard7cb69ca2008-05-10 10:55:51 +0000243
bellard43694152008-05-29 09:35:57 +0000244 page_size = getpagesize();
bellard7cb69ca2008-05-10 10:55:51 +0000245 start = (unsigned long)addr;
bellard43694152008-05-29 09:35:57 +0000246 start &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000247
248 end = (unsigned long)addr + size;
bellard43694152008-05-29 09:35:57 +0000249 end += page_size - 1;
250 end &= ~(page_size - 1);
bellard7cb69ca2008-05-10 10:55:51 +0000251
252 mprotect((void *)start, end - start,
253 PROT_READ | PROT_WRITE | PROT_EXEC);
254}
255#endif
256
bellardb346ff42003-06-15 20:05:50 +0000257static void page_init(void)
bellard54936002003-05-13 00:25:15 +0000258{
bellard83fb7ad2004-07-05 21:25:26 +0000259 /* NOTE: we can always suppose that qemu_host_page_size >=
bellard54936002003-05-13 00:25:15 +0000260 TARGET_PAGE_SIZE */
aliguoric2b48b62008-11-11 22:06:42 +0000261#ifdef _WIN32
262 {
263 SYSTEM_INFO system_info;
264
265 GetSystemInfo(&system_info);
266 qemu_real_host_page_size = system_info.dwPageSize;
267 }
268#else
269 qemu_real_host_page_size = getpagesize();
270#endif
bellard83fb7ad2004-07-05 21:25:26 +0000271 if (qemu_host_page_size == 0)
272 qemu_host_page_size = qemu_real_host_page_size;
273 if (qemu_host_page_size < TARGET_PAGE_SIZE)
274 qemu_host_page_size = TARGET_PAGE_SIZE;
275 qemu_host_page_bits = 0;
276 while ((1 << qemu_host_page_bits) < qemu_host_page_size)
277 qemu_host_page_bits++;
278 qemu_host_page_mask = ~(qemu_host_page_size - 1);
balrog50a95692007-12-12 01:16:23 +0000279
Paul Brook2e9a5712010-05-05 16:32:59 +0100280#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
balrog50a95692007-12-12 01:16:23 +0000281 {
Juergen Lockf01576f2010-03-25 22:32:16 +0100282#ifdef HAVE_KINFO_GETVMMAP
283 struct kinfo_vmentry *freep;
284 int i, cnt;
285
286 freep = kinfo_getvmmap(getpid(), &cnt);
287 if (freep) {
288 mmap_lock();
289 for (i = 0; i < cnt; i++) {
290 unsigned long startaddr, endaddr;
291
292 startaddr = freep[i].kve_start;
293 endaddr = freep[i].kve_end;
294 if (h2g_valid(startaddr)) {
295 startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
296
297 if (h2g_valid(endaddr)) {
298 endaddr = h2g(endaddr);
Aurelien Jarnofd436902010-04-10 17:20:36 +0200299 page_set_flags(startaddr, endaddr, PAGE_RESERVED);
Juergen Lockf01576f2010-03-25 22:32:16 +0100300 } else {
301#if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
302 endaddr = ~0ul;
Aurelien Jarnofd436902010-04-10 17:20:36 +0200303 page_set_flags(startaddr, endaddr, PAGE_RESERVED);
Juergen Lockf01576f2010-03-25 22:32:16 +0100304#endif
305 }
306 }
307 }
308 free(freep);
309 mmap_unlock();
310 }
311#else
balrog50a95692007-12-12 01:16:23 +0000312 FILE *f;
balrog50a95692007-12-12 01:16:23 +0000313
pbrook07765902008-05-31 16:33:53 +0000314 last_brk = (unsigned long)sbrk(0);
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800315
Aurelien Jarnofd436902010-04-10 17:20:36 +0200316 f = fopen("/compat/linux/proc/self/maps", "r");
balrog50a95692007-12-12 01:16:23 +0000317 if (f) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800318 mmap_lock();
319
balrog50a95692007-12-12 01:16:23 +0000320 do {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800321 unsigned long startaddr, endaddr;
322 int n;
323
324 n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr);
325
326 if (n == 2 && h2g_valid(startaddr)) {
327 startaddr = h2g(startaddr) & TARGET_PAGE_MASK;
328
329 if (h2g_valid(endaddr)) {
330 endaddr = h2g(endaddr);
331 } else {
332 endaddr = ~0ul;
333 }
334 page_set_flags(startaddr, endaddr, PAGE_RESERVED);
balrog50a95692007-12-12 01:16:23 +0000335 }
336 } while (!feof(f));
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800337
balrog50a95692007-12-12 01:16:23 +0000338 fclose(f);
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800339 mmap_unlock();
balrog50a95692007-12-12 01:16:23 +0000340 }
Juergen Lockf01576f2010-03-25 22:32:16 +0100341#endif
balrog50a95692007-12-12 01:16:23 +0000342 }
343#endif
bellard54936002003-05-13 00:25:15 +0000344}
345
Paul Brook41c1b1c2010-03-12 16:54:58 +0000346static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
bellard54936002003-05-13 00:25:15 +0000347{
Paul Brook41c1b1c2010-03-12 16:54:58 +0000348 PageDesc *pd;
349 void **lp;
350 int i;
351
pbrook17e23772008-06-09 13:47:45 +0000352#if defined(CONFIG_USER_ONLY)
Paul Brook2e9a5712010-05-05 16:32:59 +0100353 /* We can't use qemu_malloc because it may recurse into a locked mutex. */
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800354# define ALLOC(P, SIZE) \
355 do { \
356 P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \
357 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800358 } while (0)
pbrook17e23772008-06-09 13:47:45 +0000359#else
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800360# define ALLOC(P, SIZE) \
361 do { P = qemu_mallocz(SIZE); } while (0)
pbrook17e23772008-06-09 13:47:45 +0000362#endif
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800363
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800364 /* Level 1. Always allocated. */
365 lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1));
366
367 /* Level 2..N-1. */
368 for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
369 void **p = *lp;
370
371 if (p == NULL) {
372 if (!alloc) {
373 return NULL;
374 }
375 ALLOC(p, sizeof(void *) * L2_SIZE);
376 *lp = p;
377 }
378
379 lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000380 }
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800381
382 pd = *lp;
383 if (pd == NULL) {
384 if (!alloc) {
385 return NULL;
386 }
387 ALLOC(pd, sizeof(PageDesc) * L2_SIZE);
388 *lp = pd;
389 }
390
391#undef ALLOC
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800392
393 return pd + (index & (L2_SIZE - 1));
bellard54936002003-05-13 00:25:15 +0000394}
395
Paul Brook41c1b1c2010-03-12 16:54:58 +0000396static inline PageDesc *page_find(tb_page_addr_t index)
bellard54936002003-05-13 00:25:15 +0000397{
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800398 return page_find_alloc(index, 0);
bellard54936002003-05-13 00:25:15 +0000399}
400
Paul Brook6d9a1302010-02-28 23:55:53 +0000401#if !defined(CONFIG_USER_ONLY)
Anthony Liguoric227f092009-10-01 16:12:16 -0500402static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
bellard92e873b2004-05-21 14:52:29 +0000403{
pbrooke3f4e2a2006-04-08 20:02:06 +0000404 PhysPageDesc *pd;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800405 void **lp;
406 int i;
bellard92e873b2004-05-21 14:52:29 +0000407
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800408 /* Level 1. Always allocated. */
409 lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1));
bellard108c49b2005-07-24 12:55:09 +0000410
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800411 /* Level 2..N-1. */
412 for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) {
413 void **p = *lp;
414 if (p == NULL) {
415 if (!alloc) {
416 return NULL;
417 }
418 *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE);
419 }
420 lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1));
bellard108c49b2005-07-24 12:55:09 +0000421 }
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800422
pbrooke3f4e2a2006-04-08 20:02:06 +0000423 pd = *lp;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800424 if (pd == NULL) {
pbrooke3f4e2a2006-04-08 20:02:06 +0000425 int i;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800426
427 if (!alloc) {
bellard108c49b2005-07-24 12:55:09 +0000428 return NULL;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800429 }
430
431 *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE);
432
pbrook67c4d232009-02-23 13:16:07 +0000433 for (i = 0; i < L2_SIZE; i++) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800434 pd[i].phys_offset = IO_MEM_UNASSIGNED;
435 pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
pbrook67c4d232009-02-23 13:16:07 +0000436 }
bellard92e873b2004-05-21 14:52:29 +0000437 }
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800438
439 return pd + (index & (L2_SIZE - 1));
bellard92e873b2004-05-21 14:52:29 +0000440}
441
Anthony Liguoric227f092009-10-01 16:12:16 -0500442static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
bellard92e873b2004-05-21 14:52:29 +0000443{
bellard108c49b2005-07-24 12:55:09 +0000444 return phys_page_find_alloc(index, 0);
bellard92e873b2004-05-21 14:52:29 +0000445}
446
Anthony Liguoric227f092009-10-01 16:12:16 -0500447static void tlb_protect_code(ram_addr_t ram_addr);
448static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +0000449 target_ulong vaddr);
pbrookc8a706f2008-06-02 16:16:42 +0000450#define mmap_lock() do { } while(0)
451#define mmap_unlock() do { } while(0)
bellard9fa3e852004-01-04 18:06:42 +0000452#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000453
bellard43694152008-05-29 09:35:57 +0000454#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
455
456#if defined(CONFIG_USER_ONLY)
Stuart Bradyccbb4d42009-05-03 12:15:06 +0100457/* Currently it is not recommended to allocate big chunks of data in
bellard43694152008-05-29 09:35:57 +0000458 user mode. It will change when a dedicated libc will be used */
459#define USE_STATIC_CODE_GEN_BUFFER
460#endif
461
462#ifdef USE_STATIC_CODE_GEN_BUFFER
Aurelien Jarnoebf50fb2010-03-29 02:12:51 +0200463static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]
464 __attribute__((aligned (CODE_GEN_ALIGN)));
bellard43694152008-05-29 09:35:57 +0000465#endif
466
blueswir18fcd3692008-08-17 20:26:25 +0000467static void code_gen_alloc(unsigned long tb_size)
bellard26a5f132008-05-28 12:30:31 +0000468{
bellard43694152008-05-29 09:35:57 +0000469#ifdef USE_STATIC_CODE_GEN_BUFFER
470 code_gen_buffer = static_code_gen_buffer;
471 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
472 map_exec(code_gen_buffer, code_gen_buffer_size);
473#else
bellard26a5f132008-05-28 12:30:31 +0000474 code_gen_buffer_size = tb_size;
475 if (code_gen_buffer_size == 0) {
bellard43694152008-05-29 09:35:57 +0000476#if defined(CONFIG_USER_ONLY)
477 /* in user mode, phys_ram_size is not meaningful */
478 code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
479#else
Stuart Bradyccbb4d42009-05-03 12:15:06 +0100480 /* XXX: needs adjustments */
pbrook94a6b542009-04-11 17:15:54 +0000481 code_gen_buffer_size = (unsigned long)(ram_size / 4);
bellard43694152008-05-29 09:35:57 +0000482#endif
bellard26a5f132008-05-28 12:30:31 +0000483 }
484 if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
485 code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
486 /* The code gen buffer location may have constraints depending on
487 the host cpu and OS */
488#if defined(__linux__)
489 {
490 int flags;
blueswir1141ac462008-07-26 15:05:57 +0000491 void *start = NULL;
492
bellard26a5f132008-05-28 12:30:31 +0000493 flags = MAP_PRIVATE | MAP_ANONYMOUS;
494#if defined(__x86_64__)
495 flags |= MAP_32BIT;
496 /* Cannot map more than that */
497 if (code_gen_buffer_size > (800 * 1024 * 1024))
498 code_gen_buffer_size = (800 * 1024 * 1024);
blueswir1141ac462008-07-26 15:05:57 +0000499#elif defined(__sparc_v9__)
500 // Map the buffer below 2G, so we can use direct calls and branches
501 flags |= MAP_FIXED;
502 start = (void *) 0x60000000UL;
503 if (code_gen_buffer_size > (512 * 1024 * 1024))
504 code_gen_buffer_size = (512 * 1024 * 1024);
balrog1cb06612008-12-01 02:10:17 +0000505#elif defined(__arm__)
balrog63d41242008-12-01 02:19:41 +0000506 /* Map the buffer below 32M, so we can use direct calls and branches */
balrog1cb06612008-12-01 02:10:17 +0000507 flags |= MAP_FIXED;
508 start = (void *) 0x01000000UL;
509 if (code_gen_buffer_size > 16 * 1024 * 1024)
510 code_gen_buffer_size = 16 * 1024 * 1024;
Richard Hendersoneba0b892010-06-04 12:14:14 -0700511#elif defined(__s390x__)
512 /* Map the buffer so that we can use direct calls and branches. */
513 /* We have a +- 4GB range on the branches; leave some slop. */
514 if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) {
515 code_gen_buffer_size = 3ul * 1024 * 1024 * 1024;
516 }
517 start = (void *)0x90000000UL;
bellard26a5f132008-05-28 12:30:31 +0000518#endif
blueswir1141ac462008-07-26 15:05:57 +0000519 code_gen_buffer = mmap(start, code_gen_buffer_size,
520 PROT_WRITE | PROT_READ | PROT_EXEC,
bellard26a5f132008-05-28 12:30:31 +0000521 flags, -1, 0);
522 if (code_gen_buffer == MAP_FAILED) {
523 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
524 exit(1);
525 }
526 }
Aurelien Jarnoa167ba52009-11-29 18:00:41 +0100527#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
aliguori06e67a82008-09-27 15:32:41 +0000528 {
529 int flags;
530 void *addr = NULL;
531 flags = MAP_PRIVATE | MAP_ANONYMOUS;
532#if defined(__x86_64__)
533 /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
534 * 0x40000000 is free */
535 flags |= MAP_FIXED;
536 addr = (void *)0x40000000;
537 /* Cannot map more than that */
538 if (code_gen_buffer_size > (800 * 1024 * 1024))
539 code_gen_buffer_size = (800 * 1024 * 1024);
540#endif
541 code_gen_buffer = mmap(addr, code_gen_buffer_size,
542 PROT_WRITE | PROT_READ | PROT_EXEC,
543 flags, -1, 0);
544 if (code_gen_buffer == MAP_FAILED) {
545 fprintf(stderr, "Could not allocate dynamic translator buffer\n");
546 exit(1);
547 }
548 }
bellard26a5f132008-05-28 12:30:31 +0000549#else
550 code_gen_buffer = qemu_malloc(code_gen_buffer_size);
bellard26a5f132008-05-28 12:30:31 +0000551 map_exec(code_gen_buffer, code_gen_buffer_size);
552#endif
bellard43694152008-05-29 09:35:57 +0000553#endif /* !USE_STATIC_CODE_GEN_BUFFER */
bellard26a5f132008-05-28 12:30:31 +0000554 map_exec(code_gen_prologue, sizeof(code_gen_prologue));
555 code_gen_buffer_max_size = code_gen_buffer_size -
Aurelien Jarno239fda32010-06-03 19:29:31 +0200556 (TCG_MAX_OP_SIZE * OPC_MAX_SIZE);
bellard26a5f132008-05-28 12:30:31 +0000557 code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
558 tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
559}
560
561/* Must be called before using the QEMU cpus. 'tb_size' is the size
562 (in bytes) allocated to the translation buffer. Zero means default
563 size. */
564void cpu_exec_init_all(unsigned long tb_size)
565{
bellard26a5f132008-05-28 12:30:31 +0000566 cpu_gen_init();
567 code_gen_alloc(tb_size);
568 code_gen_ptr = code_gen_buffer;
bellard43694152008-05-29 09:35:57 +0000569 page_init();
pbrooke2eef172008-06-08 01:09:01 +0000570#if !defined(CONFIG_USER_ONLY)
bellard26a5f132008-05-28 12:30:31 +0000571 io_mem_init();
pbrooke2eef172008-06-08 01:09:01 +0000572#endif
Richard Henderson9002ec72010-05-06 08:50:41 -0700573#if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE)
574 /* There's no guest base to take into account, so go ahead and
575 initialize the prologue now. */
576 tcg_prologue_init(&tcg_ctx);
577#endif
bellard26a5f132008-05-28 12:30:31 +0000578}
579
pbrook9656f322008-07-01 20:01:19 +0000580#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
581
Juan Quintelae59fb372009-09-29 22:48:21 +0200582static int cpu_common_post_load(void *opaque, int version_id)
Juan Quintelae7f4eff2009-09-10 03:04:33 +0200583{
584 CPUState *env = opaque;
585
aurel323098dba2009-03-07 21:28:24 +0000586 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
587 version_id is increased. */
588 env->interrupt_request &= ~0x01;
pbrook9656f322008-07-01 20:01:19 +0000589 tlb_flush(env, 1);
590
591 return 0;
592}
Juan Quintelae7f4eff2009-09-10 03:04:33 +0200593
594static const VMStateDescription vmstate_cpu_common = {
595 .name = "cpu_common",
596 .version_id = 1,
597 .minimum_version_id = 1,
598 .minimum_version_id_old = 1,
Juan Quintelae7f4eff2009-09-10 03:04:33 +0200599 .post_load = cpu_common_post_load,
600 .fields = (VMStateField []) {
601 VMSTATE_UINT32(halted, CPUState),
602 VMSTATE_UINT32(interrupt_request, CPUState),
603 VMSTATE_END_OF_LIST()
604 }
605};
pbrook9656f322008-07-01 20:01:19 +0000606#endif
607
Glauber Costa950f1472009-06-09 12:15:18 -0400608CPUState *qemu_get_cpu(int cpu)
609{
610 CPUState *env = first_cpu;
611
612 while (env) {
613 if (env->cpu_index == cpu)
614 break;
615 env = env->next_cpu;
616 }
617
618 return env;
619}
620
bellard6a00d602005-11-21 23:25:50 +0000621void cpu_exec_init(CPUState *env)
bellardfd6ce8f2003-05-14 19:00:11 +0000622{
bellard6a00d602005-11-21 23:25:50 +0000623 CPUState **penv;
624 int cpu_index;
625
pbrookc2764712009-03-07 15:24:59 +0000626#if defined(CONFIG_USER_ONLY)
627 cpu_list_lock();
628#endif
bellard6a00d602005-11-21 23:25:50 +0000629 env->next_cpu = NULL;
630 penv = &first_cpu;
631 cpu_index = 0;
632 while (*penv != NULL) {
Nathan Froyd1e9fa732009-06-03 11:33:08 -0700633 penv = &(*penv)->next_cpu;
bellard6a00d602005-11-21 23:25:50 +0000634 cpu_index++;
635 }
636 env->cpu_index = cpu_index;
aliguori268a3622009-04-21 22:30:27 +0000637 env->numa_node = 0;
Blue Swirl72cf2d42009-09-12 07:36:22 +0000638 QTAILQ_INIT(&env->breakpoints);
639 QTAILQ_INIT(&env->watchpoints);
bellard6a00d602005-11-21 23:25:50 +0000640 *penv = env;
pbrookc2764712009-03-07 15:24:59 +0000641#if defined(CONFIG_USER_ONLY)
642 cpu_list_unlock();
643#endif
pbrookb3c77242008-06-30 16:31:04 +0000644#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
Alex Williamson0be71e32010-06-25 11:09:07 -0600645 vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
646 register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
pbrookb3c77242008-06-30 16:31:04 +0000647 cpu_save, cpu_load, env);
648#endif
bellardfd6ce8f2003-05-14 19:00:11 +0000649}
650
bellard9fa3e852004-01-04 18:06:42 +0000651static inline void invalidate_page_bitmap(PageDesc *p)
652{
653 if (p->code_bitmap) {
bellard59817cc2004-02-16 22:01:13 +0000654 qemu_free(p->code_bitmap);
bellard9fa3e852004-01-04 18:06:42 +0000655 p->code_bitmap = NULL;
656 }
657 p->code_write_count = 0;
658}
659
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800660/* Set to NULL all the 'first_tb' fields in all PageDescs. */
661
662static void page_flush_tb_1 (int level, void **lp)
663{
664 int i;
665
666 if (*lp == NULL) {
667 return;
668 }
669 if (level == 0) {
670 PageDesc *pd = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +0000671 for (i = 0; i < L2_SIZE; ++i) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800672 pd[i].first_tb = NULL;
673 invalidate_page_bitmap(pd + i);
674 }
675 } else {
676 void **pp = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +0000677 for (i = 0; i < L2_SIZE; ++i) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800678 page_flush_tb_1 (level - 1, pp + i);
679 }
680 }
681}
682
bellardfd6ce8f2003-05-14 19:00:11 +0000683static void page_flush_tb(void)
684{
Richard Henderson5cd2c5b2010-03-10 15:53:37 -0800685 int i;
686 for (i = 0; i < V_L1_SIZE; i++) {
687 page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i);
bellardfd6ce8f2003-05-14 19:00:11 +0000688 }
689}
690
691/* flush all the translation blocks */
bellardd4e81642003-05-25 16:46:15 +0000692/* XXX: tb_flush is currently not thread safe */
bellard6a00d602005-11-21 23:25:50 +0000693void tb_flush(CPUState *env1)
bellardfd6ce8f2003-05-14 19:00:11 +0000694{
bellard6a00d602005-11-21 23:25:50 +0000695 CPUState *env;
bellard01243112004-01-04 15:48:17 +0000696#if defined(DEBUG_FLUSH)
blueswir1ab3d1722007-11-04 07:31:40 +0000697 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
698 (unsigned long)(code_gen_ptr - code_gen_buffer),
699 nb_tbs, nb_tbs > 0 ?
700 ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
bellardfd6ce8f2003-05-14 19:00:11 +0000701#endif
bellard26a5f132008-05-28 12:30:31 +0000702 if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
pbrooka208e542008-03-31 17:07:36 +0000703 cpu_abort(env1, "Internal error: code buffer overflow\n");
704
bellardfd6ce8f2003-05-14 19:00:11 +0000705 nb_tbs = 0;
ths3b46e622007-09-17 08:09:54 +0000706
bellard6a00d602005-11-21 23:25:50 +0000707 for(env = first_cpu; env != NULL; env = env->next_cpu) {
708 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
709 }
bellard9fa3e852004-01-04 18:06:42 +0000710
bellard8a8a6082004-10-03 13:36:49 +0000711 memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
bellardfd6ce8f2003-05-14 19:00:11 +0000712 page_flush_tb();
bellard9fa3e852004-01-04 18:06:42 +0000713
bellardfd6ce8f2003-05-14 19:00:11 +0000714 code_gen_ptr = code_gen_buffer;
bellardd4e81642003-05-25 16:46:15 +0000715 /* XXX: flush processor icache at this point if cache flush is
716 expensive */
bellarde3db7222005-01-26 22:00:47 +0000717 tb_flush_count++;
bellardfd6ce8f2003-05-14 19:00:11 +0000718}
719
720#ifdef DEBUG_TB_CHECK
721
j_mayerbc98a7e2007-04-04 07:55:12 +0000722static void tb_invalidate_check(target_ulong address)
bellardfd6ce8f2003-05-14 19:00:11 +0000723{
724 TranslationBlock *tb;
725 int i;
726 address &= TARGET_PAGE_MASK;
pbrook99773bd2006-04-16 15:14:59 +0000727 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
728 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000729 if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
730 address >= tb->pc + tb->size)) {
Blue Swirl0bf9e312009-07-20 17:19:25 +0000731 printf("ERROR invalidate: address=" TARGET_FMT_lx
732 " PC=%08lx size=%04x\n",
pbrook99773bd2006-04-16 15:14:59 +0000733 address, (long)tb->pc, tb->size);
bellardfd6ce8f2003-05-14 19:00:11 +0000734 }
735 }
736 }
737}
738
739/* verify that all the pages have correct rights for code */
740static void tb_page_check(void)
741{
742 TranslationBlock *tb;
743 int i, flags1, flags2;
ths3b46e622007-09-17 08:09:54 +0000744
pbrook99773bd2006-04-16 15:14:59 +0000745 for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
746 for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
bellardfd6ce8f2003-05-14 19:00:11 +0000747 flags1 = page_get_flags(tb->pc);
748 flags2 = page_get_flags(tb->pc + tb->size - 1);
749 if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
750 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
pbrook99773bd2006-04-16 15:14:59 +0000751 (long)tb->pc, tb->size, flags1, flags2);
bellardfd6ce8f2003-05-14 19:00:11 +0000752 }
753 }
754 }
755}
756
757#endif
758
759/* invalidate one TB */
760static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
761 int next_offset)
762{
763 TranslationBlock *tb1;
764 for(;;) {
765 tb1 = *ptb;
766 if (tb1 == tb) {
767 *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
768 break;
769 }
770 ptb = (TranslationBlock **)((char *)tb1 + next_offset);
771 }
772}
773
bellard9fa3e852004-01-04 18:06:42 +0000774static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
775{
776 TranslationBlock *tb1;
777 unsigned int n1;
778
779 for(;;) {
780 tb1 = *ptb;
781 n1 = (long)tb1 & 3;
782 tb1 = (TranslationBlock *)((long)tb1 & ~3);
783 if (tb1 == tb) {
784 *ptb = tb1->page_next[n1];
785 break;
786 }
787 ptb = &tb1->page_next[n1];
788 }
789}
790
bellardd4e81642003-05-25 16:46:15 +0000791static inline void tb_jmp_remove(TranslationBlock *tb, int n)
792{
793 TranslationBlock *tb1, **ptb;
794 unsigned int n1;
795
796 ptb = &tb->jmp_next[n];
797 tb1 = *ptb;
798 if (tb1) {
799 /* find tb(n) in circular list */
800 for(;;) {
801 tb1 = *ptb;
802 n1 = (long)tb1 & 3;
803 tb1 = (TranslationBlock *)((long)tb1 & ~3);
804 if (n1 == n && tb1 == tb)
805 break;
806 if (n1 == 2) {
807 ptb = &tb1->jmp_first;
808 } else {
809 ptb = &tb1->jmp_next[n1];
810 }
811 }
812 /* now we can suppress tb(n) from the list */
813 *ptb = tb->jmp_next[n];
814
815 tb->jmp_next[n] = NULL;
816 }
817}
818
819/* reset the jump entry 'n' of a TB so that it is not chained to
820 another TB */
821static inline void tb_reset_jump(TranslationBlock *tb, int n)
822{
823 tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
824}
825
Paul Brook41c1b1c2010-03-12 16:54:58 +0000826void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +0000827{
bellard6a00d602005-11-21 23:25:50 +0000828 CPUState *env;
bellardfd6ce8f2003-05-14 19:00:11 +0000829 PageDesc *p;
bellard8a40a182005-11-20 10:35:40 +0000830 unsigned int h, n1;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000831 tb_page_addr_t phys_pc;
bellard8a40a182005-11-20 10:35:40 +0000832 TranslationBlock *tb1, *tb2;
ths3b46e622007-09-17 08:09:54 +0000833
bellard9fa3e852004-01-04 18:06:42 +0000834 /* remove the TB from the hash list */
835 phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
836 h = tb_phys_hash_func(phys_pc);
ths5fafdf22007-09-16 21:08:06 +0000837 tb_remove(&tb_phys_hash[h], tb,
bellard9fa3e852004-01-04 18:06:42 +0000838 offsetof(TranslationBlock, phys_hash_next));
bellardfd6ce8f2003-05-14 19:00:11 +0000839
bellard9fa3e852004-01-04 18:06:42 +0000840 /* remove the TB from the page list */
841 if (tb->page_addr[0] != page_addr) {
842 p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
843 tb_page_remove(&p->first_tb, tb);
844 invalidate_page_bitmap(p);
845 }
846 if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
847 p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
848 tb_page_remove(&p->first_tb, tb);
849 invalidate_page_bitmap(p);
850 }
851
bellard8a40a182005-11-20 10:35:40 +0000852 tb_invalidated_flag = 1;
853
854 /* remove the TB from the hash list */
855 h = tb_jmp_cache_hash_func(tb->pc);
bellard6a00d602005-11-21 23:25:50 +0000856 for(env = first_cpu; env != NULL; env = env->next_cpu) {
857 if (env->tb_jmp_cache[h] == tb)
858 env->tb_jmp_cache[h] = NULL;
859 }
bellard8a40a182005-11-20 10:35:40 +0000860
861 /* suppress this TB from the two jump lists */
862 tb_jmp_remove(tb, 0);
863 tb_jmp_remove(tb, 1);
864
865 /* suppress any remaining jumps to this TB */
866 tb1 = tb->jmp_first;
867 for(;;) {
868 n1 = (long)tb1 & 3;
869 if (n1 == 2)
870 break;
871 tb1 = (TranslationBlock *)((long)tb1 & ~3);
872 tb2 = tb1->jmp_next[n1];
873 tb_reset_jump(tb1, n1);
874 tb1->jmp_next[n1] = NULL;
875 tb1 = tb2;
876 }
877 tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
878
bellarde3db7222005-01-26 22:00:47 +0000879 tb_phys_invalidate_count++;
bellard9fa3e852004-01-04 18:06:42 +0000880}
881
882static inline void set_bits(uint8_t *tab, int start, int len)
883{
884 int end, mask, end1;
885
886 end = start + len;
887 tab += start >> 3;
888 mask = 0xff << (start & 7);
889 if ((start & ~7) == (end & ~7)) {
890 if (start < end) {
891 mask &= ~(0xff << (end & 7));
892 *tab |= mask;
893 }
894 } else {
895 *tab++ |= mask;
896 start = (start + 8) & ~7;
897 end1 = end & ~7;
898 while (start < end1) {
899 *tab++ = 0xff;
900 start += 8;
901 }
902 if (start < end) {
903 mask = ~(0xff << (end & 7));
904 *tab |= mask;
905 }
906 }
907}
908
909static void build_page_bitmap(PageDesc *p)
910{
911 int n, tb_start, tb_end;
912 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +0000913
pbrookb2a70812008-06-09 13:57:23 +0000914 p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
bellard9fa3e852004-01-04 18:06:42 +0000915
916 tb = p->first_tb;
917 while (tb != NULL) {
918 n = (long)tb & 3;
919 tb = (TranslationBlock *)((long)tb & ~3);
920 /* NOTE: this is subtle as a TB may span two physical pages */
921 if (n == 0) {
922 /* NOTE: tb_end may be after the end of the page, but
923 it is not a problem */
924 tb_start = tb->pc & ~TARGET_PAGE_MASK;
925 tb_end = tb_start + tb->size;
926 if (tb_end > TARGET_PAGE_SIZE)
927 tb_end = TARGET_PAGE_SIZE;
928 } else {
929 tb_start = 0;
930 tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
931 }
932 set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
933 tb = tb->page_next[n];
934 }
935}
936
pbrook2e70f6e2008-06-29 01:03:05 +0000937TranslationBlock *tb_gen_code(CPUState *env,
938 target_ulong pc, target_ulong cs_base,
939 int flags, int cflags)
bellardd720b932004-04-25 17:57:43 +0000940{
941 TranslationBlock *tb;
942 uint8_t *tc_ptr;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000943 tb_page_addr_t phys_pc, phys_page2;
944 target_ulong virt_page2;
bellardd720b932004-04-25 17:57:43 +0000945 int code_gen_size;
946
Paul Brook41c1b1c2010-03-12 16:54:58 +0000947 phys_pc = get_page_addr_code(env, pc);
bellardc27004e2005-01-03 23:35:10 +0000948 tb = tb_alloc(pc);
bellardd720b932004-04-25 17:57:43 +0000949 if (!tb) {
950 /* flush must be done */
951 tb_flush(env);
952 /* cannot fail at this point */
bellardc27004e2005-01-03 23:35:10 +0000953 tb = tb_alloc(pc);
pbrook2e70f6e2008-06-29 01:03:05 +0000954 /* Don't forget to invalidate previous TB info. */
955 tb_invalidated_flag = 1;
bellardd720b932004-04-25 17:57:43 +0000956 }
957 tc_ptr = code_gen_ptr;
958 tb->tc_ptr = tc_ptr;
959 tb->cs_base = cs_base;
960 tb->flags = flags;
961 tb->cflags = cflags;
blueswir1d07bde82007-12-11 19:35:45 +0000962 cpu_gen_code(env, tb, &code_gen_size);
bellardd720b932004-04-25 17:57:43 +0000963 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
ths3b46e622007-09-17 08:09:54 +0000964
bellardd720b932004-04-25 17:57:43 +0000965 /* check next page if needed */
bellardc27004e2005-01-03 23:35:10 +0000966 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
bellardd720b932004-04-25 17:57:43 +0000967 phys_page2 = -1;
bellardc27004e2005-01-03 23:35:10 +0000968 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
Paul Brook41c1b1c2010-03-12 16:54:58 +0000969 phys_page2 = get_page_addr_code(env, virt_page2);
bellardd720b932004-04-25 17:57:43 +0000970 }
Paul Brook41c1b1c2010-03-12 16:54:58 +0000971 tb_link_page(tb, phys_pc, phys_page2);
pbrook2e70f6e2008-06-29 01:03:05 +0000972 return tb;
bellardd720b932004-04-25 17:57:43 +0000973}
ths3b46e622007-09-17 08:09:54 +0000974
bellard9fa3e852004-01-04 18:06:42 +0000975/* invalidate all TBs which intersect with the target physical page
976 starting in range [start;end[. NOTE: start and end must refer to
bellardd720b932004-04-25 17:57:43 +0000977 the same physical page. 'is_cpu_write_access' should be true if called
978 from a real cpu write access: the virtual CPU will exit the current
979 TB if code is modified inside this TB. */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000980void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
bellardd720b932004-04-25 17:57:43 +0000981 int is_cpu_write_access)
bellard9fa3e852004-01-04 18:06:42 +0000982{
aliguori6b917542008-11-18 19:46:41 +0000983 TranslationBlock *tb, *tb_next, *saved_tb;
bellardd720b932004-04-25 17:57:43 +0000984 CPUState *env = cpu_single_env;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000985 tb_page_addr_t tb_start, tb_end;
aliguori6b917542008-11-18 19:46:41 +0000986 PageDesc *p;
987 int n;
988#ifdef TARGET_HAS_PRECISE_SMC
989 int current_tb_not_found = is_cpu_write_access;
990 TranslationBlock *current_tb = NULL;
991 int current_tb_modified = 0;
992 target_ulong current_pc = 0;
993 target_ulong current_cs_base = 0;
994 int current_flags = 0;
995#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +0000996
997 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +0000998 if (!p)
bellard9fa3e852004-01-04 18:06:42 +0000999 return;
ths5fafdf22007-09-16 21:08:06 +00001000 if (!p->code_bitmap &&
bellardd720b932004-04-25 17:57:43 +00001001 ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
1002 is_cpu_write_access) {
bellard9fa3e852004-01-04 18:06:42 +00001003 /* build code bitmap */
1004 build_page_bitmap(p);
1005 }
1006
1007 /* we remove all the TBs in the range [start, end[ */
1008 /* XXX: see if in some cases it could be faster to invalidate all the code */
1009 tb = p->first_tb;
1010 while (tb != NULL) {
1011 n = (long)tb & 3;
1012 tb = (TranslationBlock *)((long)tb & ~3);
1013 tb_next = tb->page_next[n];
1014 /* NOTE: this is subtle as a TB may span two physical pages */
1015 if (n == 0) {
1016 /* NOTE: tb_end may be after the end of the page, but
1017 it is not a problem */
1018 tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
1019 tb_end = tb_start + tb->size;
1020 } else {
1021 tb_start = tb->page_addr[1];
1022 tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
1023 }
1024 if (!(tb_end <= start || tb_start >= end)) {
bellardd720b932004-04-25 17:57:43 +00001025#ifdef TARGET_HAS_PRECISE_SMC
1026 if (current_tb_not_found) {
1027 current_tb_not_found = 0;
1028 current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001029 if (env->mem_io_pc) {
bellardd720b932004-04-25 17:57:43 +00001030 /* now we have a real cpu fault */
pbrook2e70f6e2008-06-29 01:03:05 +00001031 current_tb = tb_find_pc(env->mem_io_pc);
bellardd720b932004-04-25 17:57:43 +00001032 }
1033 }
1034 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +00001035 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +00001036 /* If we are modifying the current TB, we must stop
1037 its execution. We could be more precise by checking
1038 that the modification is after the current PC, but it
1039 would require a specialized function to partially
1040 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +00001041
bellardd720b932004-04-25 17:57:43 +00001042 current_tb_modified = 1;
ths5fafdf22007-09-16 21:08:06 +00001043 cpu_restore_state(current_tb, env,
pbrook2e70f6e2008-06-29 01:03:05 +00001044 env->mem_io_pc, NULL);
aliguori6b917542008-11-18 19:46:41 +00001045 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1046 &current_flags);
bellardd720b932004-04-25 17:57:43 +00001047 }
1048#endif /* TARGET_HAS_PRECISE_SMC */
bellard6f5a9f72005-11-26 20:12:28 +00001049 /* we need to do that to handle the case where a signal
1050 occurs while doing tb_phys_invalidate() */
1051 saved_tb = NULL;
1052 if (env) {
1053 saved_tb = env->current_tb;
1054 env->current_tb = NULL;
1055 }
bellard9fa3e852004-01-04 18:06:42 +00001056 tb_phys_invalidate(tb, -1);
bellard6f5a9f72005-11-26 20:12:28 +00001057 if (env) {
1058 env->current_tb = saved_tb;
1059 if (env->interrupt_request && env->current_tb)
1060 cpu_interrupt(env, env->interrupt_request);
1061 }
bellard9fa3e852004-01-04 18:06:42 +00001062 }
1063 tb = tb_next;
1064 }
1065#if !defined(CONFIG_USER_ONLY)
1066 /* if no code remaining, no need to continue to use slow writes */
1067 if (!p->first_tb) {
1068 invalidate_page_bitmap(p);
bellardd720b932004-04-25 17:57:43 +00001069 if (is_cpu_write_access) {
pbrook2e70f6e2008-06-29 01:03:05 +00001070 tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
bellardd720b932004-04-25 17:57:43 +00001071 }
1072 }
1073#endif
1074#ifdef TARGET_HAS_PRECISE_SMC
1075 if (current_tb_modified) {
1076 /* we generate a block containing just the instruction
1077 modifying the memory. It will ensure that it cannot modify
1078 itself */
bellardea1c1802004-06-14 18:56:36 +00001079 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001080 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001081 cpu_resume_from_signal(env, NULL);
bellard9fa3e852004-01-04 18:06:42 +00001082 }
1083#endif
1084}
1085
1086/* len must be <= 8 and start must be a multiple of len */
Paul Brook41c1b1c2010-03-12 16:54:58 +00001087static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len)
bellard9fa3e852004-01-04 18:06:42 +00001088{
1089 PageDesc *p;
1090 int offset, b;
bellard59817cc2004-02-16 22:01:13 +00001091#if 0
bellarda4193c82004-06-03 14:01:43 +00001092 if (1) {
aliguori93fcfe32009-01-15 22:34:14 +00001093 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1094 cpu_single_env->mem_io_vaddr, len,
1095 cpu_single_env->eip,
1096 cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
bellard59817cc2004-02-16 22:01:13 +00001097 }
1098#endif
bellard9fa3e852004-01-04 18:06:42 +00001099 p = page_find(start >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001100 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00001101 return;
1102 if (p->code_bitmap) {
1103 offset = start & ~TARGET_PAGE_MASK;
1104 b = p->code_bitmap[offset >> 3] >> (offset & 7);
1105 if (b & ((1 << len) - 1))
1106 goto do_invalidate;
1107 } else {
1108 do_invalidate:
bellardd720b932004-04-25 17:57:43 +00001109 tb_invalidate_phys_page_range(start, start + len, 1);
bellard9fa3e852004-01-04 18:06:42 +00001110 }
1111}
1112
bellard9fa3e852004-01-04 18:06:42 +00001113#if !defined(CONFIG_SOFTMMU)
Paul Brook41c1b1c2010-03-12 16:54:58 +00001114static void tb_invalidate_phys_page(tb_page_addr_t addr,
bellardd720b932004-04-25 17:57:43 +00001115 unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00001116{
aliguori6b917542008-11-18 19:46:41 +00001117 TranslationBlock *tb;
bellard9fa3e852004-01-04 18:06:42 +00001118 PageDesc *p;
aliguori6b917542008-11-18 19:46:41 +00001119 int n;
bellardd720b932004-04-25 17:57:43 +00001120#ifdef TARGET_HAS_PRECISE_SMC
aliguori6b917542008-11-18 19:46:41 +00001121 TranslationBlock *current_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001122 CPUState *env = cpu_single_env;
aliguori6b917542008-11-18 19:46:41 +00001123 int current_tb_modified = 0;
1124 target_ulong current_pc = 0;
1125 target_ulong current_cs_base = 0;
1126 int current_flags = 0;
bellardd720b932004-04-25 17:57:43 +00001127#endif
bellard9fa3e852004-01-04 18:06:42 +00001128
1129 addr &= TARGET_PAGE_MASK;
1130 p = page_find(addr >> TARGET_PAGE_BITS);
ths5fafdf22007-09-16 21:08:06 +00001131 if (!p)
bellardfd6ce8f2003-05-14 19:00:11 +00001132 return;
1133 tb = p->first_tb;
bellardd720b932004-04-25 17:57:43 +00001134#ifdef TARGET_HAS_PRECISE_SMC
1135 if (tb && pc != 0) {
1136 current_tb = tb_find_pc(pc);
1137 }
1138#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001139 while (tb != NULL) {
bellard9fa3e852004-01-04 18:06:42 +00001140 n = (long)tb & 3;
1141 tb = (TranslationBlock *)((long)tb & ~3);
bellardd720b932004-04-25 17:57:43 +00001142#ifdef TARGET_HAS_PRECISE_SMC
1143 if (current_tb == tb &&
pbrook2e70f6e2008-06-29 01:03:05 +00001144 (current_tb->cflags & CF_COUNT_MASK) != 1) {
bellardd720b932004-04-25 17:57:43 +00001145 /* If we are modifying the current TB, we must stop
1146 its execution. We could be more precise by checking
1147 that the modification is after the current PC, but it
1148 would require a specialized function to partially
1149 restore the CPU state */
ths3b46e622007-09-17 08:09:54 +00001150
bellardd720b932004-04-25 17:57:43 +00001151 current_tb_modified = 1;
1152 cpu_restore_state(current_tb, env, pc, puc);
aliguori6b917542008-11-18 19:46:41 +00001153 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
1154 &current_flags);
bellardd720b932004-04-25 17:57:43 +00001155 }
1156#endif /* TARGET_HAS_PRECISE_SMC */
bellard9fa3e852004-01-04 18:06:42 +00001157 tb_phys_invalidate(tb, addr);
1158 tb = tb->page_next[n];
bellardfd6ce8f2003-05-14 19:00:11 +00001159 }
1160 p->first_tb = NULL;
bellardd720b932004-04-25 17:57:43 +00001161#ifdef TARGET_HAS_PRECISE_SMC
1162 if (current_tb_modified) {
1163 /* we generate a block containing just the instruction
1164 modifying the memory. It will ensure that it cannot modify
1165 itself */
bellardea1c1802004-06-14 18:56:36 +00001166 env->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +00001167 tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
bellardd720b932004-04-25 17:57:43 +00001168 cpu_resume_from_signal(env, puc);
1169 }
1170#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001171}
bellard9fa3e852004-01-04 18:06:42 +00001172#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001173
1174/* add the tb in the target page and protect it if necessary */
ths5fafdf22007-09-16 21:08:06 +00001175static inline void tb_alloc_page(TranslationBlock *tb,
Paul Brook41c1b1c2010-03-12 16:54:58 +00001176 unsigned int n, tb_page_addr_t page_addr)
bellardfd6ce8f2003-05-14 19:00:11 +00001177{
1178 PageDesc *p;
bellard9fa3e852004-01-04 18:06:42 +00001179 TranslationBlock *last_first_tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001180
bellard9fa3e852004-01-04 18:06:42 +00001181 tb->page_addr[n] = page_addr;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001182 p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1);
bellard9fa3e852004-01-04 18:06:42 +00001183 tb->page_next[n] = p->first_tb;
1184 last_first_tb = p->first_tb;
1185 p->first_tb = (TranslationBlock *)((long)tb | n);
1186 invalidate_page_bitmap(p);
1187
bellard107db442004-06-22 18:48:46 +00001188#if defined(TARGET_HAS_SMC) || 1
bellardd720b932004-04-25 17:57:43 +00001189
bellard9fa3e852004-01-04 18:06:42 +00001190#if defined(CONFIG_USER_ONLY)
bellardfd6ce8f2003-05-14 19:00:11 +00001191 if (p->flags & PAGE_WRITE) {
pbrook53a59602006-03-25 19:31:22 +00001192 target_ulong addr;
1193 PageDesc *p2;
bellard9fa3e852004-01-04 18:06:42 +00001194 int prot;
1195
bellardfd6ce8f2003-05-14 19:00:11 +00001196 /* force the host page as non writable (writes will have a
1197 page fault + mprotect overhead) */
pbrook53a59602006-03-25 19:31:22 +00001198 page_addr &= qemu_host_page_mask;
bellardfd6ce8f2003-05-14 19:00:11 +00001199 prot = 0;
pbrook53a59602006-03-25 19:31:22 +00001200 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1201 addr += TARGET_PAGE_SIZE) {
1202
1203 p2 = page_find (addr >> TARGET_PAGE_BITS);
1204 if (!p2)
1205 continue;
1206 prot |= p2->flags;
1207 p2->flags &= ~PAGE_WRITE;
pbrook53a59602006-03-25 19:31:22 +00001208 }
ths5fafdf22007-09-16 21:08:06 +00001209 mprotect(g2h(page_addr), qemu_host_page_size,
bellardfd6ce8f2003-05-14 19:00:11 +00001210 (prot & PAGE_BITS) & ~PAGE_WRITE);
1211#ifdef DEBUG_TB_INVALIDATE
blueswir1ab3d1722007-11-04 07:31:40 +00001212 printf("protecting code page: 0x" TARGET_FMT_lx "\n",
pbrook53a59602006-03-25 19:31:22 +00001213 page_addr);
bellardfd6ce8f2003-05-14 19:00:11 +00001214#endif
bellardfd6ce8f2003-05-14 19:00:11 +00001215 }
bellard9fa3e852004-01-04 18:06:42 +00001216#else
1217 /* if some code is already present, then the pages are already
1218 protected. So we handle the case where only the first TB is
1219 allocated in a physical page */
1220 if (!last_first_tb) {
bellard6a00d602005-11-21 23:25:50 +00001221 tlb_protect_code(page_addr);
bellard9fa3e852004-01-04 18:06:42 +00001222 }
1223#endif
bellardd720b932004-04-25 17:57:43 +00001224
1225#endif /* TARGET_HAS_SMC */
bellardfd6ce8f2003-05-14 19:00:11 +00001226}
1227
1228/* Allocate a new translation block. Flush the translation buffer if
1229 too many translation blocks or too much generated code. */
bellardc27004e2005-01-03 23:35:10 +00001230TranslationBlock *tb_alloc(target_ulong pc)
bellardfd6ce8f2003-05-14 19:00:11 +00001231{
1232 TranslationBlock *tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001233
bellard26a5f132008-05-28 12:30:31 +00001234 if (nb_tbs >= code_gen_max_blocks ||
1235 (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
bellardd4e81642003-05-25 16:46:15 +00001236 return NULL;
bellardfd6ce8f2003-05-14 19:00:11 +00001237 tb = &tbs[nb_tbs++];
1238 tb->pc = pc;
bellardb448f2f2004-02-25 23:24:04 +00001239 tb->cflags = 0;
bellardd4e81642003-05-25 16:46:15 +00001240 return tb;
1241}
1242
pbrook2e70f6e2008-06-29 01:03:05 +00001243void tb_free(TranslationBlock *tb)
1244{
thsbf20dc02008-06-30 17:22:19 +00001245 /* In practice this is mostly used for single use temporary TB
pbrook2e70f6e2008-06-29 01:03:05 +00001246 Ignore the hard cases and just back up if this TB happens to
1247 be the last one generated. */
1248 if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
1249 code_gen_ptr = tb->tc_ptr;
1250 nb_tbs--;
1251 }
1252}
1253
bellard9fa3e852004-01-04 18:06:42 +00001254/* add a new TB and link it to the physical page tables. phys_page2 is
1255 (-1) to indicate that only one page contains the TB. */
Paul Brook41c1b1c2010-03-12 16:54:58 +00001256void tb_link_page(TranslationBlock *tb,
1257 tb_page_addr_t phys_pc, tb_page_addr_t phys_page2)
bellardd4e81642003-05-25 16:46:15 +00001258{
bellard9fa3e852004-01-04 18:06:42 +00001259 unsigned int h;
1260 TranslationBlock **ptb;
1261
pbrookc8a706f2008-06-02 16:16:42 +00001262 /* Grab the mmap lock to stop another thread invalidating this TB
1263 before we are done. */
1264 mmap_lock();
bellard9fa3e852004-01-04 18:06:42 +00001265 /* add in the physical hash table */
1266 h = tb_phys_hash_func(phys_pc);
1267 ptb = &tb_phys_hash[h];
1268 tb->phys_hash_next = *ptb;
1269 *ptb = tb;
bellardfd6ce8f2003-05-14 19:00:11 +00001270
1271 /* add in the page list */
bellard9fa3e852004-01-04 18:06:42 +00001272 tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
1273 if (phys_page2 != -1)
1274 tb_alloc_page(tb, 1, phys_page2);
1275 else
1276 tb->page_addr[1] = -1;
bellard9fa3e852004-01-04 18:06:42 +00001277
bellardd4e81642003-05-25 16:46:15 +00001278 tb->jmp_first = (TranslationBlock *)((long)tb | 2);
1279 tb->jmp_next[0] = NULL;
1280 tb->jmp_next[1] = NULL;
1281
1282 /* init original jump addresses */
1283 if (tb->tb_next_offset[0] != 0xffff)
1284 tb_reset_jump(tb, 0);
1285 if (tb->tb_next_offset[1] != 0xffff)
1286 tb_reset_jump(tb, 1);
bellard8a40a182005-11-20 10:35:40 +00001287
1288#ifdef DEBUG_TB_CHECK
1289 tb_page_check();
1290#endif
pbrookc8a706f2008-06-02 16:16:42 +00001291 mmap_unlock();
bellardfd6ce8f2003-05-14 19:00:11 +00001292}
1293
bellarda513fe12003-05-27 23:29:48 +00001294/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1295 tb[1].tc_ptr. Return NULL if not found */
1296TranslationBlock *tb_find_pc(unsigned long tc_ptr)
1297{
1298 int m_min, m_max, m;
1299 unsigned long v;
1300 TranslationBlock *tb;
1301
1302 if (nb_tbs <= 0)
1303 return NULL;
1304 if (tc_ptr < (unsigned long)code_gen_buffer ||
1305 tc_ptr >= (unsigned long)code_gen_ptr)
1306 return NULL;
1307 /* binary search (cf Knuth) */
1308 m_min = 0;
1309 m_max = nb_tbs - 1;
1310 while (m_min <= m_max) {
1311 m = (m_min + m_max) >> 1;
1312 tb = &tbs[m];
1313 v = (unsigned long)tb->tc_ptr;
1314 if (v == tc_ptr)
1315 return tb;
1316 else if (tc_ptr < v) {
1317 m_max = m - 1;
1318 } else {
1319 m_min = m + 1;
1320 }
ths5fafdf22007-09-16 21:08:06 +00001321 }
bellarda513fe12003-05-27 23:29:48 +00001322 return &tbs[m_max];
1323}
bellard75012672003-06-21 13:11:07 +00001324
bellardea041c02003-06-25 16:16:50 +00001325static void tb_reset_jump_recursive(TranslationBlock *tb);
1326
1327static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
1328{
1329 TranslationBlock *tb1, *tb_next, **ptb;
1330 unsigned int n1;
1331
1332 tb1 = tb->jmp_next[n];
1333 if (tb1 != NULL) {
1334 /* find head of list */
1335 for(;;) {
1336 n1 = (long)tb1 & 3;
1337 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1338 if (n1 == 2)
1339 break;
1340 tb1 = tb1->jmp_next[n1];
1341 }
1342 /* we are now sure now that tb jumps to tb1 */
1343 tb_next = tb1;
1344
1345 /* remove tb from the jmp_first list */
1346 ptb = &tb_next->jmp_first;
1347 for(;;) {
1348 tb1 = *ptb;
1349 n1 = (long)tb1 & 3;
1350 tb1 = (TranslationBlock *)((long)tb1 & ~3);
1351 if (n1 == n && tb1 == tb)
1352 break;
1353 ptb = &tb1->jmp_next[n1];
1354 }
1355 *ptb = tb->jmp_next[n];
1356 tb->jmp_next[n] = NULL;
ths3b46e622007-09-17 08:09:54 +00001357
bellardea041c02003-06-25 16:16:50 +00001358 /* suppress the jump to next tb in generated code */
1359 tb_reset_jump(tb, n);
1360
bellard01243112004-01-04 15:48:17 +00001361 /* suppress jumps in the tb on which we could have jumped */
bellardea041c02003-06-25 16:16:50 +00001362 tb_reset_jump_recursive(tb_next);
1363 }
1364}
1365
1366static void tb_reset_jump_recursive(TranslationBlock *tb)
1367{
1368 tb_reset_jump_recursive2(tb, 0);
1369 tb_reset_jump_recursive2(tb, 1);
1370}
1371
bellard1fddef42005-04-17 19:16:13 +00001372#if defined(TARGET_HAS_ICE)
Paul Brook94df27f2010-02-28 23:47:45 +00001373#if defined(CONFIG_USER_ONLY)
1374static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1375{
1376 tb_invalidate_phys_page_range(pc, pc + 1, 0);
1377}
1378#else
bellardd720b932004-04-25 17:57:43 +00001379static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1380{
Anthony Liguoric227f092009-10-01 16:12:16 -05001381 target_phys_addr_t addr;
j_mayer9b3c35e2007-04-07 11:21:28 +00001382 target_ulong pd;
Anthony Liguoric227f092009-10-01 16:12:16 -05001383 ram_addr_t ram_addr;
pbrookc2f07f82006-04-08 17:14:56 +00001384 PhysPageDesc *p;
bellardd720b932004-04-25 17:57:43 +00001385
pbrookc2f07f82006-04-08 17:14:56 +00001386 addr = cpu_get_phys_page_debug(env, pc);
1387 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1388 if (!p) {
1389 pd = IO_MEM_UNASSIGNED;
1390 } else {
1391 pd = p->phys_offset;
1392 }
1393 ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
pbrook706cd4b2006-04-08 17:36:21 +00001394 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
bellardd720b932004-04-25 17:57:43 +00001395}
bellardc27004e2005-01-03 23:35:10 +00001396#endif
Paul Brook94df27f2010-02-28 23:47:45 +00001397#endif /* TARGET_HAS_ICE */
bellardd720b932004-04-25 17:57:43 +00001398
Paul Brookc527ee82010-03-01 03:31:14 +00001399#if defined(CONFIG_USER_ONLY)
1400void cpu_watchpoint_remove_all(CPUState *env, int mask)
1401
1402{
1403}
1404
1405int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1406 int flags, CPUWatchpoint **watchpoint)
1407{
1408 return -ENOSYS;
1409}
1410#else
pbrook6658ffb2007-03-16 23:58:11 +00001411/* Add a watchpoint. */
aliguoria1d1bb32008-11-18 20:07:32 +00001412int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1413 int flags, CPUWatchpoint **watchpoint)
pbrook6658ffb2007-03-16 23:58:11 +00001414{
aliguorib4051332008-11-18 20:14:20 +00001415 target_ulong len_mask = ~(len - 1);
aliguoric0ce9982008-11-25 22:13:57 +00001416 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001417
aliguorib4051332008-11-18 20:14:20 +00001418 /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
1419 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1420 fprintf(stderr, "qemu: tried to set invalid watchpoint at "
1421 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1422 return -EINVAL;
1423 }
aliguoria1d1bb32008-11-18 20:07:32 +00001424 wp = qemu_malloc(sizeof(*wp));
pbrook6658ffb2007-03-16 23:58:11 +00001425
aliguoria1d1bb32008-11-18 20:07:32 +00001426 wp->vaddr = addr;
aliguorib4051332008-11-18 20:14:20 +00001427 wp->len_mask = len_mask;
aliguoria1d1bb32008-11-18 20:07:32 +00001428 wp->flags = flags;
1429
aliguori2dc9f412008-11-18 20:56:59 +00001430 /* keep all GDB-injected watchpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001431 if (flags & BP_GDB)
Blue Swirl72cf2d42009-09-12 07:36:22 +00001432 QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
aliguoric0ce9982008-11-25 22:13:57 +00001433 else
Blue Swirl72cf2d42009-09-12 07:36:22 +00001434 QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001435
pbrook6658ffb2007-03-16 23:58:11 +00001436 tlb_flush_page(env, addr);
aliguoria1d1bb32008-11-18 20:07:32 +00001437
1438 if (watchpoint)
1439 *watchpoint = wp;
1440 return 0;
pbrook6658ffb2007-03-16 23:58:11 +00001441}
1442
aliguoria1d1bb32008-11-18 20:07:32 +00001443/* Remove a specific watchpoint. */
1444int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1445 int flags)
pbrook6658ffb2007-03-16 23:58:11 +00001446{
aliguorib4051332008-11-18 20:14:20 +00001447 target_ulong len_mask = ~(len - 1);
aliguoria1d1bb32008-11-18 20:07:32 +00001448 CPUWatchpoint *wp;
pbrook6658ffb2007-03-16 23:58:11 +00001449
Blue Swirl72cf2d42009-09-12 07:36:22 +00001450 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00001451 if (addr == wp->vaddr && len_mask == wp->len_mask
aliguori6e140f22008-11-18 20:37:55 +00001452 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
aliguoria1d1bb32008-11-18 20:07:32 +00001453 cpu_watchpoint_remove_by_ref(env, wp);
pbrook6658ffb2007-03-16 23:58:11 +00001454 return 0;
1455 }
1456 }
aliguoria1d1bb32008-11-18 20:07:32 +00001457 return -ENOENT;
pbrook6658ffb2007-03-16 23:58:11 +00001458}
1459
aliguoria1d1bb32008-11-18 20:07:32 +00001460/* Remove a specific watchpoint by reference. */
1461void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
1462{
Blue Swirl72cf2d42009-09-12 07:36:22 +00001463 QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
edgar_igl7d03f822008-05-17 18:58:29 +00001464
aliguoria1d1bb32008-11-18 20:07:32 +00001465 tlb_flush_page(env, watchpoint->vaddr);
1466
1467 qemu_free(watchpoint);
edgar_igl7d03f822008-05-17 18:58:29 +00001468}
1469
aliguoria1d1bb32008-11-18 20:07:32 +00001470/* Remove all matching watchpoints. */
1471void cpu_watchpoint_remove_all(CPUState *env, int mask)
1472{
aliguoric0ce9982008-11-25 22:13:57 +00001473 CPUWatchpoint *wp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001474
Blue Swirl72cf2d42009-09-12 07:36:22 +00001475 QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001476 if (wp->flags & mask)
1477 cpu_watchpoint_remove_by_ref(env, wp);
aliguoric0ce9982008-11-25 22:13:57 +00001478 }
aliguoria1d1bb32008-11-18 20:07:32 +00001479}
Paul Brookc527ee82010-03-01 03:31:14 +00001480#endif
aliguoria1d1bb32008-11-18 20:07:32 +00001481
1482/* Add a breakpoint. */
1483int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
1484 CPUBreakpoint **breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001485{
bellard1fddef42005-04-17 19:16:13 +00001486#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001487 CPUBreakpoint *bp;
ths3b46e622007-09-17 08:09:54 +00001488
aliguoria1d1bb32008-11-18 20:07:32 +00001489 bp = qemu_malloc(sizeof(*bp));
aliguoria1d1bb32008-11-18 20:07:32 +00001490
1491 bp->pc = pc;
1492 bp->flags = flags;
1493
aliguori2dc9f412008-11-18 20:56:59 +00001494 /* keep all GDB-injected breakpoints in front */
aliguoric0ce9982008-11-25 22:13:57 +00001495 if (flags & BP_GDB)
Blue Swirl72cf2d42009-09-12 07:36:22 +00001496 QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
aliguoric0ce9982008-11-25 22:13:57 +00001497 else
Blue Swirl72cf2d42009-09-12 07:36:22 +00001498 QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
aliguoria1d1bb32008-11-18 20:07:32 +00001499
1500 breakpoint_invalidate(env, pc);
1501
1502 if (breakpoint)
1503 *breakpoint = bp;
1504 return 0;
1505#else
1506 return -ENOSYS;
1507#endif
1508}
1509
1510/* Remove a specific breakpoint. */
1511int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1512{
1513#if defined(TARGET_HAS_ICE)
1514 CPUBreakpoint *bp;
1515
Blue Swirl72cf2d42009-09-12 07:36:22 +00001516 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00001517 if (bp->pc == pc && bp->flags == flags) {
1518 cpu_breakpoint_remove_by_ref(env, bp);
bellard4c3a88a2003-07-26 12:06:08 +00001519 return 0;
aliguoria1d1bb32008-11-18 20:07:32 +00001520 }
bellard4c3a88a2003-07-26 12:06:08 +00001521 }
aliguoria1d1bb32008-11-18 20:07:32 +00001522 return -ENOENT;
bellard4c3a88a2003-07-26 12:06:08 +00001523#else
aliguoria1d1bb32008-11-18 20:07:32 +00001524 return -ENOSYS;
bellard4c3a88a2003-07-26 12:06:08 +00001525#endif
1526}
1527
aliguoria1d1bb32008-11-18 20:07:32 +00001528/* Remove a specific breakpoint by reference. */
1529void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
bellard4c3a88a2003-07-26 12:06:08 +00001530{
bellard1fddef42005-04-17 19:16:13 +00001531#if defined(TARGET_HAS_ICE)
Blue Swirl72cf2d42009-09-12 07:36:22 +00001532 QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
bellardd720b932004-04-25 17:57:43 +00001533
aliguoria1d1bb32008-11-18 20:07:32 +00001534 breakpoint_invalidate(env, breakpoint->pc);
1535
1536 qemu_free(breakpoint);
1537#endif
1538}
1539
1540/* Remove all matching breakpoints. */
1541void cpu_breakpoint_remove_all(CPUState *env, int mask)
1542{
1543#if defined(TARGET_HAS_ICE)
aliguoric0ce9982008-11-25 22:13:57 +00001544 CPUBreakpoint *bp, *next;
aliguoria1d1bb32008-11-18 20:07:32 +00001545
Blue Swirl72cf2d42009-09-12 07:36:22 +00001546 QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
aliguoria1d1bb32008-11-18 20:07:32 +00001547 if (bp->flags & mask)
1548 cpu_breakpoint_remove_by_ref(env, bp);
aliguoric0ce9982008-11-25 22:13:57 +00001549 }
bellard4c3a88a2003-07-26 12:06:08 +00001550#endif
1551}
1552
bellardc33a3462003-07-29 20:50:33 +00001553/* enable or disable single step mode. EXCP_DEBUG is returned by the
1554 CPU loop after each instruction */
1555void cpu_single_step(CPUState *env, int enabled)
1556{
bellard1fddef42005-04-17 19:16:13 +00001557#if defined(TARGET_HAS_ICE)
bellardc33a3462003-07-29 20:50:33 +00001558 if (env->singlestep_enabled != enabled) {
1559 env->singlestep_enabled = enabled;
aliguorie22a25c2009-03-12 20:12:48 +00001560 if (kvm_enabled())
1561 kvm_update_guest_debug(env, 0);
1562 else {
Stuart Bradyccbb4d42009-05-03 12:15:06 +01001563 /* must flush all the translated code to avoid inconsistencies */
aliguorie22a25c2009-03-12 20:12:48 +00001564 /* XXX: only flush what is necessary */
1565 tb_flush(env);
1566 }
bellardc33a3462003-07-29 20:50:33 +00001567 }
1568#endif
1569}
1570
bellard34865132003-10-05 14:28:56 +00001571/* enable or disable low levels log */
1572void cpu_set_log(int log_flags)
1573{
1574 loglevel = log_flags;
1575 if (loglevel && !logfile) {
pbrook11fcfab2007-07-01 18:21:11 +00001576 logfile = fopen(logfilename, log_append ? "a" : "w");
bellard34865132003-10-05 14:28:56 +00001577 if (!logfile) {
1578 perror(logfilename);
1579 _exit(1);
1580 }
bellard9fa3e852004-01-04 18:06:42 +00001581#if !defined(CONFIG_SOFTMMU)
1582 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
1583 {
blueswir1b55266b2008-09-20 08:07:15 +00001584 static char logfile_buf[4096];
bellard9fa3e852004-01-04 18:06:42 +00001585 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
1586 }
Filip Navarabf65f532009-07-27 10:02:04 -05001587#elif !defined(_WIN32)
1588 /* Win32 doesn't support line-buffering and requires size >= 2 */
bellard34865132003-10-05 14:28:56 +00001589 setvbuf(logfile, NULL, _IOLBF, 0);
bellard9fa3e852004-01-04 18:06:42 +00001590#endif
pbrooke735b912007-06-30 13:53:24 +00001591 log_append = 1;
1592 }
1593 if (!loglevel && logfile) {
1594 fclose(logfile);
1595 logfile = NULL;
bellard34865132003-10-05 14:28:56 +00001596 }
1597}
1598
1599void cpu_set_log_filename(const char *filename)
1600{
1601 logfilename = strdup(filename);
pbrooke735b912007-06-30 13:53:24 +00001602 if (logfile) {
1603 fclose(logfile);
1604 logfile = NULL;
1605 }
1606 cpu_set_log(loglevel);
bellard34865132003-10-05 14:28:56 +00001607}
bellardc33a3462003-07-29 20:50:33 +00001608
aurel323098dba2009-03-07 21:28:24 +00001609static void cpu_unlink_tb(CPUState *env)
bellardea041c02003-06-25 16:16:50 +00001610{
pbrookd5975362008-06-07 20:50:51 +00001611 /* FIXME: TB unchaining isn't SMP safe. For now just ignore the
1612 problem and hope the cpu will stop of its own accord. For userspace
1613 emulation this often isn't actually as bad as it sounds. Often
1614 signals are used primarily to interrupt blocking syscalls. */
aurel323098dba2009-03-07 21:28:24 +00001615 TranslationBlock *tb;
Anthony Liguoric227f092009-10-01 16:12:16 -05001616 static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
aurel323098dba2009-03-07 21:28:24 +00001617
Riku Voipiocab1b4b2010-01-20 12:56:27 +02001618 spin_lock(&interrupt_lock);
aurel323098dba2009-03-07 21:28:24 +00001619 tb = env->current_tb;
1620 /* if the cpu is currently executing code, we must unlink it and
1621 all the potentially executing TB */
Riku Voipiof76cfe52009-12-04 15:16:30 +02001622 if (tb) {
aurel323098dba2009-03-07 21:28:24 +00001623 env->current_tb = NULL;
1624 tb_reset_jump_recursive(tb);
aurel323098dba2009-03-07 21:28:24 +00001625 }
Riku Voipiocab1b4b2010-01-20 12:56:27 +02001626 spin_unlock(&interrupt_lock);
aurel323098dba2009-03-07 21:28:24 +00001627}
1628
1629/* mask must never be zero, except for A20 change call */
1630void cpu_interrupt(CPUState *env, int mask)
1631{
1632 int old_mask;
1633
1634 old_mask = env->interrupt_request;
1635 env->interrupt_request |= mask;
1636
aliguori8edac962009-04-24 18:03:45 +00001637#ifndef CONFIG_USER_ONLY
1638 /*
1639 * If called from iothread context, wake the target cpu in
1640 * case its halted.
1641 */
1642 if (!qemu_cpu_self(env)) {
1643 qemu_cpu_kick(env);
1644 return;
1645 }
1646#endif
1647
pbrook2e70f6e2008-06-29 01:03:05 +00001648 if (use_icount) {
pbrook266910c2008-07-09 15:31:50 +00001649 env->icount_decr.u16.high = 0xffff;
pbrook2e70f6e2008-06-29 01:03:05 +00001650#ifndef CONFIG_USER_ONLY
pbrook2e70f6e2008-06-29 01:03:05 +00001651 if (!can_do_io(env)
aurel32be214e62009-03-06 21:48:00 +00001652 && (mask & ~old_mask) != 0) {
pbrook2e70f6e2008-06-29 01:03:05 +00001653 cpu_abort(env, "Raised interrupt while not in I/O function");
1654 }
1655#endif
1656 } else {
aurel323098dba2009-03-07 21:28:24 +00001657 cpu_unlink_tb(env);
bellardea041c02003-06-25 16:16:50 +00001658 }
1659}
1660
bellardb54ad042004-05-20 13:42:52 +00001661void cpu_reset_interrupt(CPUState *env, int mask)
1662{
1663 env->interrupt_request &= ~mask;
1664}
1665
aurel323098dba2009-03-07 21:28:24 +00001666void cpu_exit(CPUState *env)
1667{
1668 env->exit_request = 1;
1669 cpu_unlink_tb(env);
1670}
1671
blueswir1c7cd6a32008-10-02 18:27:46 +00001672const CPULogItem cpu_log_items[] = {
ths5fafdf22007-09-16 21:08:06 +00001673 { CPU_LOG_TB_OUT_ASM, "out_asm",
bellardf193c792004-03-21 17:06:25 +00001674 "show generated host assembly code for each compiled TB" },
1675 { CPU_LOG_TB_IN_ASM, "in_asm",
1676 "show target assembly code for each compiled TB" },
ths5fafdf22007-09-16 21:08:06 +00001677 { CPU_LOG_TB_OP, "op",
bellard57fec1f2008-02-01 10:50:11 +00001678 "show micro ops for each compiled TB" },
bellardf193c792004-03-21 17:06:25 +00001679 { CPU_LOG_TB_OP_OPT, "op_opt",
blueswir1e01a1152008-03-14 17:37:11 +00001680 "show micro ops "
1681#ifdef TARGET_I386
1682 "before eflags optimization and "
bellardf193c792004-03-21 17:06:25 +00001683#endif
blueswir1e01a1152008-03-14 17:37:11 +00001684 "after liveness analysis" },
bellardf193c792004-03-21 17:06:25 +00001685 { CPU_LOG_INT, "int",
1686 "show interrupts/exceptions in short format" },
1687 { CPU_LOG_EXEC, "exec",
1688 "show trace before each executed TB (lots of logs)" },
bellard9fddaa02004-05-21 12:59:32 +00001689 { CPU_LOG_TB_CPU, "cpu",
thse91c8a72007-06-03 13:35:16 +00001690 "show CPU state before block translation" },
bellardf193c792004-03-21 17:06:25 +00001691#ifdef TARGET_I386
1692 { CPU_LOG_PCALL, "pcall",
1693 "show protected mode far calls/returns/exceptions" },
aliguorieca1bdf2009-01-26 19:54:31 +00001694 { CPU_LOG_RESET, "cpu_reset",
1695 "show CPU state before CPU resets" },
bellardf193c792004-03-21 17:06:25 +00001696#endif
bellard8e3a9fd2004-10-09 17:32:58 +00001697#ifdef DEBUG_IOPORT
bellardfd872592004-05-12 19:11:15 +00001698 { CPU_LOG_IOPORT, "ioport",
1699 "show all i/o ports accesses" },
bellard8e3a9fd2004-10-09 17:32:58 +00001700#endif
bellardf193c792004-03-21 17:06:25 +00001701 { 0, NULL, NULL },
1702};
1703
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001704#ifndef CONFIG_USER_ONLY
1705static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list
1706 = QLIST_HEAD_INITIALIZER(memory_client_list);
1707
1708static void cpu_notify_set_memory(target_phys_addr_t start_addr,
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09001709 ram_addr_t size,
1710 ram_addr_t phys_offset)
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001711{
1712 CPUPhysMemoryClient *client;
1713 QLIST_FOREACH(client, &memory_client_list, list) {
1714 client->set_memory(client, start_addr, size, phys_offset);
1715 }
1716}
1717
1718static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start,
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09001719 target_phys_addr_t end)
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001720{
1721 CPUPhysMemoryClient *client;
1722 QLIST_FOREACH(client, &memory_client_list, list) {
1723 int r = client->sync_dirty_bitmap(client, start, end);
1724 if (r < 0)
1725 return r;
1726 }
1727 return 0;
1728}
1729
1730static int cpu_notify_migration_log(int enable)
1731{
1732 CPUPhysMemoryClient *client;
1733 QLIST_FOREACH(client, &memory_client_list, list) {
1734 int r = client->migration_log(client, enable);
1735 if (r < 0)
1736 return r;
1737 }
1738 return 0;
1739}
1740
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001741static void phys_page_for_each_1(CPUPhysMemoryClient *client,
1742 int level, void **lp)
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001743{
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001744 int i;
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001745
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001746 if (*lp == NULL) {
1747 return;
1748 }
1749 if (level == 0) {
1750 PhysPageDesc *pd = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +00001751 for (i = 0; i < L2_SIZE; ++i) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001752 if (pd[i].phys_offset != IO_MEM_UNASSIGNED) {
1753 client->set_memory(client, pd[i].region_offset,
1754 TARGET_PAGE_SIZE, pd[i].phys_offset);
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001755 }
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001756 }
1757 } else {
1758 void **pp = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +00001759 for (i = 0; i < L2_SIZE; ++i) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001760 phys_page_for_each_1(client, level - 1, pp + i);
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001761 }
1762 }
1763}
1764
1765static void phys_page_for_each(CPUPhysMemoryClient *client)
1766{
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08001767 int i;
1768 for (i = 0; i < P_L1_SIZE; ++i) {
1769 phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1,
1770 l1_phys_map + 1);
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001771 }
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02001772}
1773
1774void cpu_register_phys_memory_client(CPUPhysMemoryClient *client)
1775{
1776 QLIST_INSERT_HEAD(&memory_client_list, client, list);
1777 phys_page_for_each(client);
1778}
1779
1780void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client)
1781{
1782 QLIST_REMOVE(client, list);
1783}
1784#endif
1785
bellardf193c792004-03-21 17:06:25 +00001786static int cmp1(const char *s1, int n, const char *s2)
1787{
1788 if (strlen(s2) != n)
1789 return 0;
1790 return memcmp(s1, s2, n) == 0;
1791}
ths3b46e622007-09-17 08:09:54 +00001792
bellardf193c792004-03-21 17:06:25 +00001793/* takes a comma separated list of log masks. Return 0 if error. */
1794int cpu_str_to_log_mask(const char *str)
1795{
blueswir1c7cd6a32008-10-02 18:27:46 +00001796 const CPULogItem *item;
bellardf193c792004-03-21 17:06:25 +00001797 int mask;
1798 const char *p, *p1;
1799
1800 p = str;
1801 mask = 0;
1802 for(;;) {
1803 p1 = strchr(p, ',');
1804 if (!p1)
1805 p1 = p + strlen(p);
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09001806 if(cmp1(p,p1-p,"all")) {
1807 for(item = cpu_log_items; item->mask != 0; item++) {
1808 mask |= item->mask;
1809 }
1810 } else {
1811 for(item = cpu_log_items; item->mask != 0; item++) {
1812 if (cmp1(p, p1 - p, item->name))
1813 goto found;
1814 }
1815 return 0;
bellardf193c792004-03-21 17:06:25 +00001816 }
bellardf193c792004-03-21 17:06:25 +00001817 found:
1818 mask |= item->mask;
1819 if (*p1 != ',')
1820 break;
1821 p = p1 + 1;
1822 }
1823 return mask;
1824}
bellardea041c02003-06-25 16:16:50 +00001825
bellard75012672003-06-21 13:11:07 +00001826void cpu_abort(CPUState *env, const char *fmt, ...)
1827{
1828 va_list ap;
pbrook493ae1f2007-11-23 16:53:59 +00001829 va_list ap2;
bellard75012672003-06-21 13:11:07 +00001830
1831 va_start(ap, fmt);
pbrook493ae1f2007-11-23 16:53:59 +00001832 va_copy(ap2, ap);
bellard75012672003-06-21 13:11:07 +00001833 fprintf(stderr, "qemu: fatal: ");
1834 vfprintf(stderr, fmt, ap);
1835 fprintf(stderr, "\n");
1836#ifdef TARGET_I386
bellard7fe48482004-10-09 18:08:01 +00001837 cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
1838#else
1839 cpu_dump_state(env, stderr, fprintf, 0);
bellard75012672003-06-21 13:11:07 +00001840#endif
aliguori93fcfe32009-01-15 22:34:14 +00001841 if (qemu_log_enabled()) {
1842 qemu_log("qemu: fatal: ");
1843 qemu_log_vprintf(fmt, ap2);
1844 qemu_log("\n");
j_mayerf9373292007-09-29 12:18:20 +00001845#ifdef TARGET_I386
aliguori93fcfe32009-01-15 22:34:14 +00001846 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
j_mayerf9373292007-09-29 12:18:20 +00001847#else
aliguori93fcfe32009-01-15 22:34:14 +00001848 log_cpu_state(env, 0);
j_mayerf9373292007-09-29 12:18:20 +00001849#endif
aliguori31b1a7b2009-01-15 22:35:09 +00001850 qemu_log_flush();
aliguori93fcfe32009-01-15 22:34:14 +00001851 qemu_log_close();
balrog924edca2007-06-10 14:07:13 +00001852 }
pbrook493ae1f2007-11-23 16:53:59 +00001853 va_end(ap2);
j_mayerf9373292007-09-29 12:18:20 +00001854 va_end(ap);
Riku Voipiofd052bf2010-01-25 14:30:49 +02001855#if defined(CONFIG_USER_ONLY)
1856 {
1857 struct sigaction act;
1858 sigfillset(&act.sa_mask);
1859 act.sa_handler = SIG_DFL;
1860 sigaction(SIGABRT, &act, NULL);
1861 }
1862#endif
bellard75012672003-06-21 13:11:07 +00001863 abort();
1864}
1865
thsc5be9f02007-02-28 20:20:53 +00001866CPUState *cpu_copy(CPUState *env)
1867{
ths01ba9812007-12-09 02:22:57 +00001868 CPUState *new_env = cpu_init(env->cpu_model_str);
thsc5be9f02007-02-28 20:20:53 +00001869 CPUState *next_cpu = new_env->next_cpu;
1870 int cpu_index = new_env->cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001871#if defined(TARGET_HAS_ICE)
1872 CPUBreakpoint *bp;
1873 CPUWatchpoint *wp;
1874#endif
1875
thsc5be9f02007-02-28 20:20:53 +00001876 memcpy(new_env, env, sizeof(CPUState));
aliguori5a38f082009-01-15 20:16:51 +00001877
1878 /* Preserve chaining and index. */
thsc5be9f02007-02-28 20:20:53 +00001879 new_env->next_cpu = next_cpu;
1880 new_env->cpu_index = cpu_index;
aliguori5a38f082009-01-15 20:16:51 +00001881
1882 /* Clone all break/watchpoints.
1883 Note: Once we support ptrace with hw-debug register access, make sure
1884 BP_CPU break/watchpoints are handled correctly on clone. */
Blue Swirl72cf2d42009-09-12 07:36:22 +00001885 QTAILQ_INIT(&env->breakpoints);
1886 QTAILQ_INIT(&env->watchpoints);
aliguori5a38f082009-01-15 20:16:51 +00001887#if defined(TARGET_HAS_ICE)
Blue Swirl72cf2d42009-09-12 07:36:22 +00001888 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
aliguori5a38f082009-01-15 20:16:51 +00001889 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
1890 }
Blue Swirl72cf2d42009-09-12 07:36:22 +00001891 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguori5a38f082009-01-15 20:16:51 +00001892 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
1893 wp->flags, NULL);
1894 }
1895#endif
1896
thsc5be9f02007-02-28 20:20:53 +00001897 return new_env;
1898}
1899
bellard01243112004-01-04 15:48:17 +00001900#if !defined(CONFIG_USER_ONLY)
1901
edgar_igl5c751e92008-05-06 08:44:21 +00001902static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1903{
1904 unsigned int i;
1905
1906 /* Discard jump cache entries for any tb which might potentially
1907 overlap the flushed page. */
1908 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1909 memset (&env->tb_jmp_cache[i], 0,
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09001910 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
edgar_igl5c751e92008-05-06 08:44:21 +00001911
1912 i = tb_jmp_cache_hash_page(addr);
1913 memset (&env->tb_jmp_cache[i], 0,
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09001914 TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
edgar_igl5c751e92008-05-06 08:44:21 +00001915}
1916
Igor Kovalenko08738982009-07-12 02:15:40 +04001917static CPUTLBEntry s_cputlb_empty_entry = {
1918 .addr_read = -1,
1919 .addr_write = -1,
1920 .addr_code = -1,
1921 .addend = -1,
1922};
1923
bellardee8b7022004-02-03 23:35:10 +00001924/* NOTE: if flush_global is true, also flush global entries (not
1925 implemented yet) */
1926void tlb_flush(CPUState *env, int flush_global)
bellard33417e72003-08-10 21:47:01 +00001927{
bellard33417e72003-08-10 21:47:01 +00001928 int i;
bellard01243112004-01-04 15:48:17 +00001929
bellard9fa3e852004-01-04 18:06:42 +00001930#if defined(DEBUG_TLB)
1931 printf("tlb_flush:\n");
1932#endif
bellard01243112004-01-04 15:48:17 +00001933 /* must reset current TB so that interrupts cannot modify the
1934 links while we are modifying them */
1935 env->current_tb = NULL;
1936
bellard33417e72003-08-10 21:47:01 +00001937 for(i = 0; i < CPU_TLB_SIZE; i++) {
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09001938 int mmu_idx;
1939 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
Igor Kovalenko08738982009-07-12 02:15:40 +04001940 env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09001941 }
bellard33417e72003-08-10 21:47:01 +00001942 }
bellard9fa3e852004-01-04 18:06:42 +00001943
bellard8a40a182005-11-20 10:35:40 +00001944 memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
bellard9fa3e852004-01-04 18:06:42 +00001945
Paul Brookd4c430a2010-03-17 02:14:28 +00001946 env->tlb_flush_addr = -1;
1947 env->tlb_flush_mask = 0;
bellarde3db7222005-01-26 22:00:47 +00001948 tlb_flush_count++;
bellard33417e72003-08-10 21:47:01 +00001949}
1950
bellard274da6b2004-05-20 21:56:27 +00001951static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
bellard61382a52003-10-27 21:22:23 +00001952{
ths5fafdf22007-09-16 21:08:06 +00001953 if (addr == (tlb_entry->addr_read &
bellard84b7b8e2005-11-28 21:19:04 +00001954 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001955 addr == (tlb_entry->addr_write &
bellard84b7b8e2005-11-28 21:19:04 +00001956 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
ths5fafdf22007-09-16 21:08:06 +00001957 addr == (tlb_entry->addr_code &
bellard84b7b8e2005-11-28 21:19:04 +00001958 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
Igor Kovalenko08738982009-07-12 02:15:40 +04001959 *tlb_entry = s_cputlb_empty_entry;
bellard84b7b8e2005-11-28 21:19:04 +00001960 }
bellard61382a52003-10-27 21:22:23 +00001961}
1962
bellard2e126692004-04-25 21:28:44 +00001963void tlb_flush_page(CPUState *env, target_ulong addr)
bellard33417e72003-08-10 21:47:01 +00001964{
bellard8a40a182005-11-20 10:35:40 +00001965 int i;
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09001966 int mmu_idx;
bellard01243112004-01-04 15:48:17 +00001967
bellard9fa3e852004-01-04 18:06:42 +00001968#if defined(DEBUG_TLB)
bellard108c49b2005-07-24 12:55:09 +00001969 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
bellard9fa3e852004-01-04 18:06:42 +00001970#endif
Paul Brookd4c430a2010-03-17 02:14:28 +00001971 /* Check if we need to flush due to large pages. */
1972 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
1973#if defined(DEBUG_TLB)
1974 printf("tlb_flush_page: forced full flush ("
1975 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
1976 env->tlb_flush_addr, env->tlb_flush_mask);
1977#endif
1978 tlb_flush(env, 1);
1979 return;
1980 }
bellard01243112004-01-04 15:48:17 +00001981 /* must reset current TB so that interrupts cannot modify the
1982 links while we are modifying them */
1983 env->current_tb = NULL;
bellard33417e72003-08-10 21:47:01 +00001984
bellard61382a52003-10-27 21:22:23 +00001985 addr &= TARGET_PAGE_MASK;
bellard33417e72003-08-10 21:47:01 +00001986 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09001987 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
1988 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
bellard01243112004-01-04 15:48:17 +00001989
edgar_igl5c751e92008-05-06 08:44:21 +00001990 tlb_flush_jmp_cache(env, addr);
bellard9fa3e852004-01-04 18:06:42 +00001991}
1992
bellard9fa3e852004-01-04 18:06:42 +00001993/* update the TLBs so that writes to code in the virtual page 'addr'
1994 can be detected */
Anthony Liguoric227f092009-10-01 16:12:16 -05001995static void tlb_protect_code(ram_addr_t ram_addr)
bellard61382a52003-10-27 21:22:23 +00001996{
ths5fafdf22007-09-16 21:08:06 +00001997 cpu_physical_memory_reset_dirty(ram_addr,
bellard6a00d602005-11-21 23:25:50 +00001998 ram_addr + TARGET_PAGE_SIZE,
1999 CODE_DIRTY_FLAG);
bellard9fa3e852004-01-04 18:06:42 +00002000}
2001
bellard9fa3e852004-01-04 18:06:42 +00002002/* update the TLB so that writes in physical page 'phys_addr' are no longer
bellard3a7d9292005-08-21 09:26:42 +00002003 tested for self modifying code */
Anthony Liguoric227f092009-10-01 16:12:16 -05002004static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
bellard3a7d9292005-08-21 09:26:42 +00002005 target_ulong vaddr)
bellard9fa3e852004-01-04 18:06:42 +00002006{
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09002007 cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
bellard1ccde1c2004-02-06 19:46:14 +00002008}
2009
ths5fafdf22007-09-16 21:08:06 +00002010static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
bellard1ccde1c2004-02-06 19:46:14 +00002011 unsigned long start, unsigned long length)
2012{
2013 unsigned long addr;
bellard84b7b8e2005-11-28 21:19:04 +00002014 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
2015 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
bellard1ccde1c2004-02-06 19:46:14 +00002016 if ((addr - start) < length) {
pbrook0f459d12008-06-09 00:20:13 +00002017 tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
bellard1ccde1c2004-02-06 19:46:14 +00002018 }
2019 }
2020}
2021
pbrook5579c7f2009-04-11 14:47:08 +00002022/* Note: start and end must be within the same ram block. */
Anthony Liguoric227f092009-10-01 16:12:16 -05002023void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +00002024 int dirty_flags)
bellard1ccde1c2004-02-06 19:46:14 +00002025{
2026 CPUState *env;
bellard4f2ac232004-04-26 19:44:02 +00002027 unsigned long length, start1;
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09002028 int i;
bellard1ccde1c2004-02-06 19:46:14 +00002029
2030 start &= TARGET_PAGE_MASK;
2031 end = TARGET_PAGE_ALIGN(end);
2032
2033 length = end - start;
2034 if (length == 0)
2035 return;
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09002036 cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
bellardf23db162005-08-21 19:12:28 +00002037
bellard1ccde1c2004-02-06 19:46:14 +00002038 /* we modify the TLB cache so that the dirty bit will be set again
2039 when accessing the range */
pbrook5579c7f2009-04-11 14:47:08 +00002040 start1 = (unsigned long)qemu_get_ram_ptr(start);
2041 /* Chek that we don't span multiple blocks - this breaks the
2042 address comparisons below. */
2043 if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1
2044 != (end - 1) - start) {
2045 abort();
2046 }
2047
bellard6a00d602005-11-21 23:25:50 +00002048 for(env = first_cpu; env != NULL; env = env->next_cpu) {
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09002049 int mmu_idx;
2050 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
2051 for(i = 0; i < CPU_TLB_SIZE; i++)
2052 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
2053 start1, length);
2054 }
bellard6a00d602005-11-21 23:25:50 +00002055 }
bellard1ccde1c2004-02-06 19:46:14 +00002056}
2057
aliguori74576192008-10-06 14:02:03 +00002058int cpu_physical_memory_set_dirty_tracking(int enable)
2059{
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02002060 int ret = 0;
aliguori74576192008-10-06 14:02:03 +00002061 in_migration = enable;
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02002062 ret = cpu_notify_migration_log(!!enable);
2063 return ret;
aliguori74576192008-10-06 14:02:03 +00002064}
2065
2066int cpu_physical_memory_get_dirty_tracking(void)
2067{
2068 return in_migration;
2069}
2070
Anthony Liguoric227f092009-10-01 16:12:16 -05002071int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
2072 target_phys_addr_t end_addr)
aliguori2bec46d2008-11-24 20:21:41 +00002073{
Michael S. Tsirkin7b8f3b72010-01-27 22:07:21 +02002074 int ret;
Jan Kiszka151f7742009-05-01 20:52:47 +02002075
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02002076 ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr);
Jan Kiszka151f7742009-05-01 20:52:47 +02002077 return ret;
aliguori2bec46d2008-11-24 20:21:41 +00002078}
2079
bellard3a7d9292005-08-21 09:26:42 +00002080static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
2081{
Anthony Liguoric227f092009-10-01 16:12:16 -05002082 ram_addr_t ram_addr;
pbrook5579c7f2009-04-11 14:47:08 +00002083 void *p;
bellard3a7d9292005-08-21 09:26:42 +00002084
bellard84b7b8e2005-11-28 21:19:04 +00002085 if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
pbrook5579c7f2009-04-11 14:47:08 +00002086 p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK)
2087 + tlb_entry->addend);
2088 ram_addr = qemu_ram_addr_from_host(p);
bellard3a7d9292005-08-21 09:26:42 +00002089 if (!cpu_physical_memory_is_dirty(ram_addr)) {
pbrook0f459d12008-06-09 00:20:13 +00002090 tlb_entry->addr_write |= TLB_NOTDIRTY;
bellard3a7d9292005-08-21 09:26:42 +00002091 }
2092 }
2093}
2094
2095/* update the TLB according to the current state of the dirty bits */
2096void cpu_tlb_update_dirty(CPUState *env)
2097{
2098 int i;
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09002099 int mmu_idx;
2100 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
2101 for(i = 0; i < CPU_TLB_SIZE; i++)
2102 tlb_update_dirty(&env->tlb_table[mmu_idx][i]);
2103 }
bellard3a7d9292005-08-21 09:26:42 +00002104}
2105
pbrook0f459d12008-06-09 00:20:13 +00002106static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002107{
pbrook0f459d12008-06-09 00:20:13 +00002108 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
2109 tlb_entry->addr_write = vaddr;
bellard1ccde1c2004-02-06 19:46:14 +00002110}
2111
pbrook0f459d12008-06-09 00:20:13 +00002112/* update the TLB corresponding to virtual page vaddr
2113 so that it is no longer dirty */
2114static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002115{
bellard1ccde1c2004-02-06 19:46:14 +00002116 int i;
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09002117 int mmu_idx;
bellard1ccde1c2004-02-06 19:46:14 +00002118
pbrook0f459d12008-06-09 00:20:13 +00002119 vaddr &= TARGET_PAGE_MASK;
bellard1ccde1c2004-02-06 19:46:14 +00002120 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
Isaku Yamahatacfde4bd2009-05-20 11:31:43 +09002121 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
2122 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
bellard9fa3e852004-01-04 18:06:42 +00002123}
2124
Paul Brookd4c430a2010-03-17 02:14:28 +00002125/* Our TLB does not support large pages, so remember the area covered by
2126 large pages and trigger a full TLB flush if these are invalidated. */
2127static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
2128 target_ulong size)
2129{
2130 target_ulong mask = ~(size - 1);
2131
2132 if (env->tlb_flush_addr == (target_ulong)-1) {
2133 env->tlb_flush_addr = vaddr & mask;
2134 env->tlb_flush_mask = mask;
2135 return;
2136 }
2137 /* Extend the existing region to include the new page.
2138 This is a compromise between unnecessary flushes and the cost
2139 of maintaining a full variable size TLB. */
2140 mask &= env->tlb_flush_mask;
2141 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
2142 mask <<= 1;
2143 }
2144 env->tlb_flush_addr &= mask;
2145 env->tlb_flush_mask = mask;
2146}
2147
2148/* Add a new TLB entry. At most one entry for a given virtual address
2149 is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
2150 supplied size is only used by tlb_flush_page. */
2151void tlb_set_page(CPUState *env, target_ulong vaddr,
2152 target_phys_addr_t paddr, int prot,
2153 int mmu_idx, target_ulong size)
bellard9fa3e852004-01-04 18:06:42 +00002154{
bellard92e873b2004-05-21 14:52:29 +00002155 PhysPageDesc *p;
bellard4f2ac232004-04-26 19:44:02 +00002156 unsigned long pd;
bellard9fa3e852004-01-04 18:06:42 +00002157 unsigned int index;
bellard4f2ac232004-04-26 19:44:02 +00002158 target_ulong address;
pbrook0f459d12008-06-09 00:20:13 +00002159 target_ulong code_address;
Paul Brook355b1942010-04-05 00:28:53 +01002160 unsigned long addend;
bellard84b7b8e2005-11-28 21:19:04 +00002161 CPUTLBEntry *te;
aliguoria1d1bb32008-11-18 20:07:32 +00002162 CPUWatchpoint *wp;
Anthony Liguoric227f092009-10-01 16:12:16 -05002163 target_phys_addr_t iotlb;
bellard9fa3e852004-01-04 18:06:42 +00002164
Paul Brookd4c430a2010-03-17 02:14:28 +00002165 assert(size >= TARGET_PAGE_SIZE);
2166 if (size != TARGET_PAGE_SIZE) {
2167 tlb_add_large_page(env, vaddr, size);
2168 }
bellard92e873b2004-05-21 14:52:29 +00002169 p = phys_page_find(paddr >> TARGET_PAGE_BITS);
bellard9fa3e852004-01-04 18:06:42 +00002170 if (!p) {
2171 pd = IO_MEM_UNASSIGNED;
bellard9fa3e852004-01-04 18:06:42 +00002172 } else {
2173 pd = p->phys_offset;
bellard9fa3e852004-01-04 18:06:42 +00002174 }
2175#if defined(DEBUG_TLB)
j_mayer6ebbf392007-10-14 07:07:08 +00002176 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
2177 vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
bellard9fa3e852004-01-04 18:06:42 +00002178#endif
2179
pbrook0f459d12008-06-09 00:20:13 +00002180 address = vaddr;
2181 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
2182 /* IO memory case (romd handled later) */
2183 address |= TLB_MMIO;
2184 }
pbrook5579c7f2009-04-11 14:47:08 +00002185 addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
pbrook0f459d12008-06-09 00:20:13 +00002186 if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
2187 /* Normal RAM. */
2188 iotlb = pd & TARGET_PAGE_MASK;
2189 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
2190 iotlb |= IO_MEM_NOTDIRTY;
2191 else
2192 iotlb |= IO_MEM_ROM;
2193 } else {
Stuart Bradyccbb4d42009-05-03 12:15:06 +01002194 /* IO handlers are currently passed a physical address.
pbrook0f459d12008-06-09 00:20:13 +00002195 It would be nice to pass an offset from the base address
2196 of that region. This would avoid having to special case RAM,
2197 and avoid full address decoding in every device.
2198 We can't use the high bits of pd for this because
2199 IO_MEM_ROMD uses these as a ram address. */
pbrook8da3ff12008-12-01 18:59:50 +00002200 iotlb = (pd & ~TARGET_PAGE_MASK);
2201 if (p) {
pbrook8da3ff12008-12-01 18:59:50 +00002202 iotlb += p->region_offset;
2203 } else {
2204 iotlb += paddr;
2205 }
pbrook0f459d12008-06-09 00:20:13 +00002206 }
pbrook6658ffb2007-03-16 23:58:11 +00002207
pbrook0f459d12008-06-09 00:20:13 +00002208 code_address = address;
2209 /* Make accesses to pages with watchpoints go via the
2210 watchpoint trap routines. */
Blue Swirl72cf2d42009-09-12 07:36:22 +00002211 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00002212 if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
Jun Koibf298f82010-05-06 14:36:59 +09002213 /* Avoid trapping reads of pages with a write breakpoint. */
2214 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
2215 iotlb = io_mem_watch + paddr;
2216 address |= TLB_MMIO;
2217 break;
2218 }
pbrook6658ffb2007-03-16 23:58:11 +00002219 }
pbrook0f459d12008-06-09 00:20:13 +00002220 }
balrogd79acba2007-06-26 20:01:13 +00002221
pbrook0f459d12008-06-09 00:20:13 +00002222 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
2223 env->iotlb[mmu_idx][index] = iotlb - vaddr;
2224 te = &env->tlb_table[mmu_idx][index];
2225 te->addend = addend - vaddr;
2226 if (prot & PAGE_READ) {
2227 te->addr_read = address;
2228 } else {
2229 te->addr_read = -1;
2230 }
edgar_igl5c751e92008-05-06 08:44:21 +00002231
pbrook0f459d12008-06-09 00:20:13 +00002232 if (prot & PAGE_EXEC) {
2233 te->addr_code = code_address;
2234 } else {
2235 te->addr_code = -1;
2236 }
2237 if (prot & PAGE_WRITE) {
2238 if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
2239 (pd & IO_MEM_ROMD)) {
2240 /* Write access calls the I/O callback. */
2241 te->addr_write = address | TLB_MMIO;
2242 } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
2243 !cpu_physical_memory_is_dirty(pd)) {
2244 te->addr_write = address | TLB_NOTDIRTY;
bellard84b7b8e2005-11-28 21:19:04 +00002245 } else {
pbrook0f459d12008-06-09 00:20:13 +00002246 te->addr_write = address;
bellard9fa3e852004-01-04 18:06:42 +00002247 }
pbrook0f459d12008-06-09 00:20:13 +00002248 } else {
2249 te->addr_write = -1;
bellard9fa3e852004-01-04 18:06:42 +00002250 }
bellard9fa3e852004-01-04 18:06:42 +00002251}
2252
bellard01243112004-01-04 15:48:17 +00002253#else
2254
bellardee8b7022004-02-03 23:35:10 +00002255void tlb_flush(CPUState *env, int flush_global)
bellard01243112004-01-04 15:48:17 +00002256{
2257}
2258
bellard2e126692004-04-25 21:28:44 +00002259void tlb_flush_page(CPUState *env, target_ulong addr)
bellard01243112004-01-04 15:48:17 +00002260{
2261}
2262
Mika Westerbergedf8e2a2009-04-07 09:57:11 +03002263/*
2264 * Walks guest process memory "regions" one by one
2265 * and calls callback function 'fn' for each region.
2266 */
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002267
2268struct walk_memory_regions_data
bellard9fa3e852004-01-04 18:06:42 +00002269{
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002270 walk_memory_regions_fn fn;
2271 void *priv;
2272 unsigned long start;
2273 int prot;
2274};
bellard9fa3e852004-01-04 18:06:42 +00002275
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002276static int walk_memory_regions_end(struct walk_memory_regions_data *data,
Paul Brookb480d9b2010-03-12 23:23:29 +00002277 abi_ulong end, int new_prot)
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002278{
2279 if (data->start != -1ul) {
2280 int rc = data->fn(data->priv, data->start, end, data->prot);
2281 if (rc != 0) {
2282 return rc;
bellard9fa3e852004-01-04 18:06:42 +00002283 }
bellard33417e72003-08-10 21:47:01 +00002284 }
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002285
2286 data->start = (new_prot ? end : -1ul);
2287 data->prot = new_prot;
2288
2289 return 0;
2290}
2291
2292static int walk_memory_regions_1(struct walk_memory_regions_data *data,
Paul Brookb480d9b2010-03-12 23:23:29 +00002293 abi_ulong base, int level, void **lp)
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002294{
Paul Brookb480d9b2010-03-12 23:23:29 +00002295 abi_ulong pa;
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002296 int i, rc;
2297
2298 if (*lp == NULL) {
2299 return walk_memory_regions_end(data, base, 0);
2300 }
2301
2302 if (level == 0) {
2303 PageDesc *pd = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +00002304 for (i = 0; i < L2_SIZE; ++i) {
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002305 int prot = pd[i].flags;
2306
2307 pa = base | (i << TARGET_PAGE_BITS);
2308 if (prot != data->prot) {
2309 rc = walk_memory_regions_end(data, pa, prot);
2310 if (rc != 0) {
2311 return rc;
2312 }
2313 }
2314 }
2315 } else {
2316 void **pp = *lp;
Paul Brook7296aba2010-03-14 14:58:46 +00002317 for (i = 0; i < L2_SIZE; ++i) {
Paul Brookb480d9b2010-03-12 23:23:29 +00002318 pa = base | ((abi_ulong)i <<
2319 (TARGET_PAGE_BITS + L2_BITS * level));
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002320 rc = walk_memory_regions_1(data, pa, level - 1, pp + i);
2321 if (rc != 0) {
2322 return rc;
2323 }
2324 }
2325 }
2326
2327 return 0;
2328}
2329
2330int walk_memory_regions(void *priv, walk_memory_regions_fn fn)
2331{
2332 struct walk_memory_regions_data data;
2333 unsigned long i;
2334
2335 data.fn = fn;
2336 data.priv = priv;
2337 data.start = -1ul;
2338 data.prot = 0;
2339
2340 for (i = 0; i < V_L1_SIZE; i++) {
Paul Brookb480d9b2010-03-12 23:23:29 +00002341 int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT,
Richard Henderson5cd2c5b2010-03-10 15:53:37 -08002342 V_L1_SHIFT / L2_BITS - 1, l1_map + i);
2343 if (rc != 0) {
2344 return rc;
2345 }
2346 }
2347
2348 return walk_memory_regions_end(&data, 0, 0);
Mika Westerbergedf8e2a2009-04-07 09:57:11 +03002349}
2350
Paul Brookb480d9b2010-03-12 23:23:29 +00002351static int dump_region(void *priv, abi_ulong start,
2352 abi_ulong end, unsigned long prot)
Mika Westerbergedf8e2a2009-04-07 09:57:11 +03002353{
2354 FILE *f = (FILE *)priv;
2355
Paul Brookb480d9b2010-03-12 23:23:29 +00002356 (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx
2357 " "TARGET_ABI_FMT_lx" %c%c%c\n",
Mika Westerbergedf8e2a2009-04-07 09:57:11 +03002358 start, end, end - start,
2359 ((prot & PAGE_READ) ? 'r' : '-'),
2360 ((prot & PAGE_WRITE) ? 'w' : '-'),
2361 ((prot & PAGE_EXEC) ? 'x' : '-'));
2362
2363 return (0);
2364}
2365
2366/* dump memory mappings */
2367void page_dump(FILE *f)
2368{
2369 (void) fprintf(f, "%-8s %-8s %-8s %s\n",
2370 "start", "end", "size", "prot");
2371 walk_memory_regions(f, dump_region);
bellard33417e72003-08-10 21:47:01 +00002372}
2373
pbrook53a59602006-03-25 19:31:22 +00002374int page_get_flags(target_ulong address)
bellard33417e72003-08-10 21:47:01 +00002375{
bellard9fa3e852004-01-04 18:06:42 +00002376 PageDesc *p;
2377
2378 p = page_find(address >> TARGET_PAGE_BITS);
bellard33417e72003-08-10 21:47:01 +00002379 if (!p)
bellard9fa3e852004-01-04 18:06:42 +00002380 return 0;
2381 return p->flags;
bellard33417e72003-08-10 21:47:01 +00002382}
2383
Richard Henderson376a7902010-03-10 15:57:04 -08002384/* Modify the flags of a page and invalidate the code if necessary.
2385 The flag PAGE_WRITE_ORG is positioned automatically depending
2386 on PAGE_WRITE. The mmap_lock should already be held. */
pbrook53a59602006-03-25 19:31:22 +00002387void page_set_flags(target_ulong start, target_ulong end, int flags)
bellard9fa3e852004-01-04 18:06:42 +00002388{
Richard Henderson376a7902010-03-10 15:57:04 -08002389 target_ulong addr, len;
bellard9fa3e852004-01-04 18:06:42 +00002390
Richard Henderson376a7902010-03-10 15:57:04 -08002391 /* This function should never be called with addresses outside the
2392 guest address space. If this assert fires, it probably indicates
2393 a missing call to h2g_valid. */
Paul Brookb480d9b2010-03-12 23:23:29 +00002394#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
2395 assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
Richard Henderson376a7902010-03-10 15:57:04 -08002396#endif
2397 assert(start < end);
2398
bellard9fa3e852004-01-04 18:06:42 +00002399 start = start & TARGET_PAGE_MASK;
2400 end = TARGET_PAGE_ALIGN(end);
Richard Henderson376a7902010-03-10 15:57:04 -08002401
2402 if (flags & PAGE_WRITE) {
bellard9fa3e852004-01-04 18:06:42 +00002403 flags |= PAGE_WRITE_ORG;
Richard Henderson376a7902010-03-10 15:57:04 -08002404 }
2405
2406 for (addr = start, len = end - start;
2407 len != 0;
2408 len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
2409 PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2410
2411 /* If the write protection bit is set, then we invalidate
2412 the code inside. */
ths5fafdf22007-09-16 21:08:06 +00002413 if (!(p->flags & PAGE_WRITE) &&
bellard9fa3e852004-01-04 18:06:42 +00002414 (flags & PAGE_WRITE) &&
2415 p->first_tb) {
bellardd720b932004-04-25 17:57:43 +00002416 tb_invalidate_phys_page(addr, 0, NULL);
bellard9fa3e852004-01-04 18:06:42 +00002417 }
2418 p->flags = flags;
2419 }
bellard9fa3e852004-01-04 18:06:42 +00002420}
2421
ths3d97b402007-11-02 19:02:07 +00002422int page_check_range(target_ulong start, target_ulong len, int flags)
2423{
2424 PageDesc *p;
2425 target_ulong end;
2426 target_ulong addr;
2427
Richard Henderson376a7902010-03-10 15:57:04 -08002428 /* This function should never be called with addresses outside the
2429 guest address space. If this assert fires, it probably indicates
2430 a missing call to h2g_valid. */
Blue Swirl338e9e62010-03-13 09:48:08 +00002431#if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
2432 assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS));
Richard Henderson376a7902010-03-10 15:57:04 -08002433#endif
2434
Richard Henderson3e0650a2010-03-29 10:54:42 -07002435 if (len == 0) {
2436 return 0;
2437 }
Richard Henderson376a7902010-03-10 15:57:04 -08002438 if (start + len - 1 < start) {
2439 /* We've wrapped around. */
balrog55f280c2008-10-28 10:24:11 +00002440 return -1;
Richard Henderson376a7902010-03-10 15:57:04 -08002441 }
balrog55f280c2008-10-28 10:24:11 +00002442
ths3d97b402007-11-02 19:02:07 +00002443 end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
2444 start = start & TARGET_PAGE_MASK;
2445
Richard Henderson376a7902010-03-10 15:57:04 -08002446 for (addr = start, len = end - start;
2447 len != 0;
2448 len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
ths3d97b402007-11-02 19:02:07 +00002449 p = page_find(addr >> TARGET_PAGE_BITS);
2450 if( !p )
2451 return -1;
2452 if( !(p->flags & PAGE_VALID) )
2453 return -1;
2454
bellarddae32702007-11-14 10:51:00 +00002455 if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
ths3d97b402007-11-02 19:02:07 +00002456 return -1;
bellarddae32702007-11-14 10:51:00 +00002457 if (flags & PAGE_WRITE) {
2458 if (!(p->flags & PAGE_WRITE_ORG))
2459 return -1;
2460 /* unprotect the page if it was put read-only because it
2461 contains translated code */
2462 if (!(p->flags & PAGE_WRITE)) {
2463 if (!page_unprotect(addr, 0, NULL))
2464 return -1;
2465 }
2466 return 0;
2467 }
ths3d97b402007-11-02 19:02:07 +00002468 }
2469 return 0;
2470}
2471
bellard9fa3e852004-01-04 18:06:42 +00002472/* called from signal handler: invalidate the code and unprotect the
Stuart Bradyccbb4d42009-05-03 12:15:06 +01002473 page. Return TRUE if the fault was successfully handled. */
pbrook53a59602006-03-25 19:31:22 +00002474int page_unprotect(target_ulong address, unsigned long pc, void *puc)
bellard9fa3e852004-01-04 18:06:42 +00002475{
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002476 unsigned int prot;
2477 PageDesc *p;
pbrook53a59602006-03-25 19:31:22 +00002478 target_ulong host_start, host_end, addr;
bellard9fa3e852004-01-04 18:06:42 +00002479
pbrookc8a706f2008-06-02 16:16:42 +00002480 /* Technically this isn't safe inside a signal handler. However we
2481 know this only ever happens in a synchronous SEGV handler, so in
2482 practice it seems to be ok. */
2483 mmap_lock();
2484
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002485 p = page_find(address >> TARGET_PAGE_BITS);
2486 if (!p) {
pbrookc8a706f2008-06-02 16:16:42 +00002487 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002488 return 0;
pbrookc8a706f2008-06-02 16:16:42 +00002489 }
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002490
bellard9fa3e852004-01-04 18:06:42 +00002491 /* if the page was really writable, then we change its
2492 protection back to writable */
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002493 if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) {
2494 host_start = address & qemu_host_page_mask;
2495 host_end = host_start + qemu_host_page_size;
2496
2497 prot = 0;
2498 for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) {
2499 p = page_find(addr >> TARGET_PAGE_BITS);
2500 p->flags |= PAGE_WRITE;
2501 prot |= p->flags;
2502
bellard9fa3e852004-01-04 18:06:42 +00002503 /* and since the content will be modified, we must invalidate
2504 the corresponding translated code. */
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002505 tb_invalidate_phys_page(addr, pc, puc);
bellard9fa3e852004-01-04 18:06:42 +00002506#ifdef DEBUG_TB_CHECK
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002507 tb_invalidate_check(addr);
bellard9fa3e852004-01-04 18:06:42 +00002508#endif
bellard9fa3e852004-01-04 18:06:42 +00002509 }
Aurelien Jarno45d679d2010-03-29 02:12:51 +02002510 mprotect((void *)g2h(host_start), qemu_host_page_size,
2511 prot & PAGE_BITS);
2512
2513 mmap_unlock();
2514 return 1;
bellard9fa3e852004-01-04 18:06:42 +00002515 }
pbrookc8a706f2008-06-02 16:16:42 +00002516 mmap_unlock();
bellard9fa3e852004-01-04 18:06:42 +00002517 return 0;
2518}
2519
bellard6a00d602005-11-21 23:25:50 +00002520static inline void tlb_set_dirty(CPUState *env,
2521 unsigned long addr, target_ulong vaddr)
bellard1ccde1c2004-02-06 19:46:14 +00002522{
2523}
bellard9fa3e852004-01-04 18:06:42 +00002524#endif /* defined(CONFIG_USER_ONLY) */
2525
pbrooke2eef172008-06-08 01:09:01 +00002526#if !defined(CONFIG_USER_ONLY)
pbrook8da3ff12008-12-01 18:59:50 +00002527
Paul Brookc04b2b72010-03-01 03:31:14 +00002528#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
2529typedef struct subpage_t {
2530 target_phys_addr_t base;
Richard Hendersonf6405242010-04-22 16:47:31 -07002531 ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
2532 ram_addr_t region_offset[TARGET_PAGE_SIZE];
Paul Brookc04b2b72010-03-01 03:31:14 +00002533} subpage_t;
2534
Anthony Liguoric227f092009-10-01 16:12:16 -05002535static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2536 ram_addr_t memory, ram_addr_t region_offset);
Richard Hendersonf6405242010-04-22 16:47:31 -07002537static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
2538 ram_addr_t orig_memory,
2539 ram_addr_t region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002540#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2541 need_subpage) \
2542 do { \
2543 if (addr > start_addr) \
2544 start_addr2 = 0; \
2545 else { \
2546 start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
2547 if (start_addr2 > 0) \
2548 need_subpage = 1; \
2549 } \
2550 \
blueswir149e9fba2007-05-30 17:25:06 +00002551 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
blueswir1db7b5422007-05-26 17:36:03 +00002552 end_addr2 = TARGET_PAGE_SIZE - 1; \
2553 else { \
2554 end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
2555 if (end_addr2 < TARGET_PAGE_SIZE - 1) \
2556 need_subpage = 1; \
2557 } \
2558 } while (0)
2559
Michael S. Tsirkin8f2498f2009-09-29 18:53:16 +02002560/* register physical memory.
2561 For RAM, 'size' must be a multiple of the target page size.
2562 If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
pbrook8da3ff12008-12-01 18:59:50 +00002563 io memory page. The address used when calling the IO function is
2564 the offset from the start of the region, plus region_offset. Both
Stuart Bradyccbb4d42009-05-03 12:15:06 +01002565 start_addr and region_offset are rounded down to a page boundary
pbrook8da3ff12008-12-01 18:59:50 +00002566 before calculating this offset. This should not be a problem unless
2567 the low bits of start_addr and region_offset differ. */
Anthony Liguoric227f092009-10-01 16:12:16 -05002568void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
2569 ram_addr_t size,
2570 ram_addr_t phys_offset,
2571 ram_addr_t region_offset)
bellard33417e72003-08-10 21:47:01 +00002572{
Anthony Liguoric227f092009-10-01 16:12:16 -05002573 target_phys_addr_t addr, end_addr;
bellard92e873b2004-05-21 14:52:29 +00002574 PhysPageDesc *p;
bellard9d420372006-06-25 22:25:22 +00002575 CPUState *env;
Anthony Liguoric227f092009-10-01 16:12:16 -05002576 ram_addr_t orig_size = size;
Richard Hendersonf6405242010-04-22 16:47:31 -07002577 subpage_t *subpage;
bellard33417e72003-08-10 21:47:01 +00002578
Michael S. Tsirkinf6f3fbc2010-01-27 22:06:57 +02002579 cpu_notify_set_memory(start_addr, size, phys_offset);
2580
pbrook67c4d232009-02-23 13:16:07 +00002581 if (phys_offset == IO_MEM_UNASSIGNED) {
2582 region_offset = start_addr;
2583 }
pbrook8da3ff12008-12-01 18:59:50 +00002584 region_offset &= TARGET_PAGE_MASK;
bellard5fd386f2004-05-23 21:11:22 +00002585 size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
Anthony Liguoric227f092009-10-01 16:12:16 -05002586 end_addr = start_addr + (target_phys_addr_t)size;
blueswir149e9fba2007-05-30 17:25:06 +00002587 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
blueswir1db7b5422007-05-26 17:36:03 +00002588 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2589 if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
Anthony Liguoric227f092009-10-01 16:12:16 -05002590 ram_addr_t orig_memory = p->phys_offset;
2591 target_phys_addr_t start_addr2, end_addr2;
blueswir1db7b5422007-05-26 17:36:03 +00002592 int need_subpage = 0;
2593
2594 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2595 need_subpage);
Richard Hendersonf6405242010-04-22 16:47:31 -07002596 if (need_subpage) {
blueswir1db7b5422007-05-26 17:36:03 +00002597 if (!(orig_memory & IO_MEM_SUBPAGE)) {
2598 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002599 &p->phys_offset, orig_memory,
2600 p->region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00002601 } else {
2602 subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
2603 >> IO_MEM_SHIFT];
2604 }
pbrook8da3ff12008-12-01 18:59:50 +00002605 subpage_register(subpage, start_addr2, end_addr2, phys_offset,
2606 region_offset);
2607 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002608 } else {
2609 p->phys_offset = phys_offset;
2610 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
2611 (phys_offset & IO_MEM_ROMD))
2612 phys_offset += TARGET_PAGE_SIZE;
2613 }
2614 } else {
2615 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2616 p->phys_offset = phys_offset;
pbrook8da3ff12008-12-01 18:59:50 +00002617 p->region_offset = region_offset;
blueswir1db7b5422007-05-26 17:36:03 +00002618 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
pbrook8da3ff12008-12-01 18:59:50 +00002619 (phys_offset & IO_MEM_ROMD)) {
blueswir1db7b5422007-05-26 17:36:03 +00002620 phys_offset += TARGET_PAGE_SIZE;
pbrook0e8f0962008-12-02 09:02:15 +00002621 } else {
Anthony Liguoric227f092009-10-01 16:12:16 -05002622 target_phys_addr_t start_addr2, end_addr2;
blueswir1db7b5422007-05-26 17:36:03 +00002623 int need_subpage = 0;
2624
2625 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2626 end_addr2, need_subpage);
2627
Richard Hendersonf6405242010-04-22 16:47:31 -07002628 if (need_subpage) {
blueswir1db7b5422007-05-26 17:36:03 +00002629 subpage = subpage_init((addr & TARGET_PAGE_MASK),
pbrook8da3ff12008-12-01 18:59:50 +00002630 &p->phys_offset, IO_MEM_UNASSIGNED,
pbrook67c4d232009-02-23 13:16:07 +00002631 addr & TARGET_PAGE_MASK);
blueswir1db7b5422007-05-26 17:36:03 +00002632 subpage_register(subpage, start_addr2, end_addr2,
pbrook8da3ff12008-12-01 18:59:50 +00002633 phys_offset, region_offset);
2634 p->region_offset = 0;
blueswir1db7b5422007-05-26 17:36:03 +00002635 }
2636 }
2637 }
pbrook8da3ff12008-12-01 18:59:50 +00002638 region_offset += TARGET_PAGE_SIZE;
bellard33417e72003-08-10 21:47:01 +00002639 }
ths3b46e622007-09-17 08:09:54 +00002640
bellard9d420372006-06-25 22:25:22 +00002641 /* since each CPU stores ram addresses in its TLB cache, we must
2642 reset the modified entries */
2643 /* XXX: slow ! */
2644 for(env = first_cpu; env != NULL; env = env->next_cpu) {
2645 tlb_flush(env, 1);
2646 }
bellard33417e72003-08-10 21:47:01 +00002647}
2648
bellardba863452006-09-24 18:41:10 +00002649/* XXX: temporary until new memory mapping API */
Anthony Liguoric227f092009-10-01 16:12:16 -05002650ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
bellardba863452006-09-24 18:41:10 +00002651{
2652 PhysPageDesc *p;
2653
2654 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2655 if (!p)
2656 return IO_MEM_UNASSIGNED;
2657 return p->phys_offset;
2658}
2659
Anthony Liguoric227f092009-10-01 16:12:16 -05002660void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
aliguorif65ed4c2008-12-09 20:09:57 +00002661{
2662 if (kvm_enabled())
2663 kvm_coalesce_mmio_region(addr, size);
2664}
2665
Anthony Liguoric227f092009-10-01 16:12:16 -05002666void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
aliguorif65ed4c2008-12-09 20:09:57 +00002667{
2668 if (kvm_enabled())
2669 kvm_uncoalesce_mmio_region(addr, size);
2670}
2671
Sheng Yang62a27442010-01-26 19:21:16 +08002672void qemu_flush_coalesced_mmio_buffer(void)
2673{
2674 if (kvm_enabled())
2675 kvm_flush_coalesced_mmio_buffer();
2676}
2677
Marcelo Tosattic9027602010-03-01 20:25:08 -03002678#if defined(__linux__) && !defined(TARGET_S390X)
2679
2680#include <sys/vfs.h>
2681
2682#define HUGETLBFS_MAGIC 0x958458f6
2683
2684static long gethugepagesize(const char *path)
2685{
2686 struct statfs fs;
2687 int ret;
2688
2689 do {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002690 ret = statfs(path, &fs);
Marcelo Tosattic9027602010-03-01 20:25:08 -03002691 } while (ret != 0 && errno == EINTR);
2692
2693 if (ret != 0) {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002694 perror(path);
2695 return 0;
Marcelo Tosattic9027602010-03-01 20:25:08 -03002696 }
2697
2698 if (fs.f_type != HUGETLBFS_MAGIC)
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002699 fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
Marcelo Tosattic9027602010-03-01 20:25:08 -03002700
2701 return fs.f_bsize;
2702}
2703
Alex Williamson04b16652010-07-02 11:13:17 -06002704static void *file_ram_alloc(RAMBlock *block,
2705 ram_addr_t memory,
2706 const char *path)
Marcelo Tosattic9027602010-03-01 20:25:08 -03002707{
2708 char *filename;
2709 void *area;
2710 int fd;
2711#ifdef MAP_POPULATE
2712 int flags;
2713#endif
2714 unsigned long hpagesize;
2715
2716 hpagesize = gethugepagesize(path);
2717 if (!hpagesize) {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002718 return NULL;
Marcelo Tosattic9027602010-03-01 20:25:08 -03002719 }
2720
2721 if (memory < hpagesize) {
2722 return NULL;
2723 }
2724
2725 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2726 fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
2727 return NULL;
2728 }
2729
2730 if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002731 return NULL;
Marcelo Tosattic9027602010-03-01 20:25:08 -03002732 }
2733
2734 fd = mkstemp(filename);
2735 if (fd < 0) {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002736 perror("unable to create backing store for hugepages");
2737 free(filename);
2738 return NULL;
Marcelo Tosattic9027602010-03-01 20:25:08 -03002739 }
2740 unlink(filename);
2741 free(filename);
2742
2743 memory = (memory+hpagesize-1) & ~(hpagesize-1);
2744
2745 /*
2746 * ftruncate is not supported by hugetlbfs in older
2747 * hosts, so don't bother bailing out on errors.
2748 * If anything goes wrong with it under other filesystems,
2749 * mmap will fail.
2750 */
2751 if (ftruncate(fd, memory))
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002752 perror("ftruncate");
Marcelo Tosattic9027602010-03-01 20:25:08 -03002753
2754#ifdef MAP_POPULATE
2755 /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
2756 * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED
2757 * to sidestep this quirk.
2758 */
2759 flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
2760 area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
2761#else
2762 area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
2763#endif
2764 if (area == MAP_FAILED) {
Yoshiaki Tamura9742bf22010-08-18 13:30:13 +09002765 perror("file_ram_alloc: can't mmap RAM pages");
2766 close(fd);
2767 return (NULL);
Marcelo Tosattic9027602010-03-01 20:25:08 -03002768 }
Alex Williamson04b16652010-07-02 11:13:17 -06002769 block->fd = fd;
Marcelo Tosattic9027602010-03-01 20:25:08 -03002770 return area;
2771}
2772#endif
2773
Alex Williamsond17b5282010-06-25 11:08:38 -06002774static ram_addr_t find_ram_offset(ram_addr_t size)
2775{
Alex Williamson04b16652010-07-02 11:13:17 -06002776 RAMBlock *block, *next_block;
Blue Swirl09d7ae92010-07-07 19:37:53 +00002777 ram_addr_t offset = 0, mingap = ULONG_MAX;
Alex Williamson04b16652010-07-02 11:13:17 -06002778
2779 if (QLIST_EMPTY(&ram_list.blocks))
2780 return 0;
2781
2782 QLIST_FOREACH(block, &ram_list.blocks, next) {
2783 ram_addr_t end, next = ULONG_MAX;
2784
2785 end = block->offset + block->length;
2786
2787 QLIST_FOREACH(next_block, &ram_list.blocks, next) {
2788 if (next_block->offset >= end) {
2789 next = MIN(next, next_block->offset);
2790 }
2791 }
2792 if (next - end >= size && next - end < mingap) {
2793 offset = end;
2794 mingap = next - end;
2795 }
2796 }
2797 return offset;
2798}
2799
2800static ram_addr_t last_ram_offset(void)
2801{
Alex Williamsond17b5282010-06-25 11:08:38 -06002802 RAMBlock *block;
2803 ram_addr_t last = 0;
2804
2805 QLIST_FOREACH(block, &ram_list.blocks, next)
2806 last = MAX(last, block->offset + block->length);
2807
2808 return last;
2809}
2810
Cam Macdonell84b89d72010-07-26 18:10:57 -06002811ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
Yoshiaki Tamura6977dfe2010-08-18 15:41:49 +09002812 ram_addr_t size, void *host)
Cam Macdonell84b89d72010-07-26 18:10:57 -06002813{
2814 RAMBlock *new_block, *block;
2815
2816 size = TARGET_PAGE_ALIGN(size);
2817 new_block = qemu_mallocz(sizeof(*new_block));
2818
2819 if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) {
2820 char *id = dev->parent_bus->info->get_dev_path(dev);
2821 if (id) {
2822 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
2823 qemu_free(id);
2824 }
2825 }
2826 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
2827
2828 QLIST_FOREACH(block, &ram_list.blocks, next) {
2829 if (!strcmp(block->idstr, new_block->idstr)) {
2830 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
2831 new_block->idstr);
2832 abort();
2833 }
2834 }
2835
Yoshiaki Tamura6977dfe2010-08-18 15:41:49 +09002836 if (host) {
2837 new_block->host = host;
2838 } else {
2839 if (mem_path) {
2840#if defined (__linux__) && !defined(TARGET_S390X)
2841 new_block->host = file_ram_alloc(new_block, size, mem_path);
2842 if (!new_block->host) {
2843 new_block->host = qemu_vmalloc(size);
Andreas Färbere78815a2010-09-25 11:26:05 +00002844 qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE);
Yoshiaki Tamura6977dfe2010-08-18 15:41:49 +09002845 }
2846#else
2847 fprintf(stderr, "-mem-path option unsupported\n");
2848 exit(1);
2849#endif
2850 } else {
2851#if defined(TARGET_S390X) && defined(CONFIG_KVM)
2852 /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */
2853 new_block->host = mmap((void*)0x1000000, size,
2854 PROT_EXEC|PROT_READ|PROT_WRITE,
2855 MAP_SHARED | MAP_ANONYMOUS, -1, 0);
2856#else
2857 new_block->host = qemu_vmalloc(size);
2858#endif
Andreas Färbere78815a2010-09-25 11:26:05 +00002859 qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE);
Yoshiaki Tamura6977dfe2010-08-18 15:41:49 +09002860 }
2861 }
Cam Macdonell84b89d72010-07-26 18:10:57 -06002862
2863 new_block->offset = find_ram_offset(size);
2864 new_block->length = size;
2865
2866 QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next);
2867
2868 ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty,
2869 last_ram_offset() >> TARGET_PAGE_BITS);
2870 memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
2871 0xff, size >> TARGET_PAGE_BITS);
2872
2873 if (kvm_enabled())
2874 kvm_setup_guest_memory(new_block->host, size);
2875
2876 return new_block->offset;
2877}
2878
Alex Williamson1724f042010-06-25 11:09:35 -06002879ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size)
pbrook94a6b542009-04-11 17:15:54 +00002880{
Yoshiaki Tamura6977dfe2010-08-18 15:41:49 +09002881 return qemu_ram_alloc_from_ptr(dev, name, size, NULL);
pbrook94a6b542009-04-11 17:15:54 +00002882}
bellarde9a1ab12007-02-08 23:08:38 +00002883
Anthony Liguoric227f092009-10-01 16:12:16 -05002884void qemu_ram_free(ram_addr_t addr)
bellarde9a1ab12007-02-08 23:08:38 +00002885{
Alex Williamson04b16652010-07-02 11:13:17 -06002886 RAMBlock *block;
2887
2888 QLIST_FOREACH(block, &ram_list.blocks, next) {
2889 if (addr == block->offset) {
2890 QLIST_REMOVE(block, next);
2891 if (mem_path) {
2892#if defined (__linux__) && !defined(TARGET_S390X)
2893 if (block->fd) {
2894 munmap(block->host, block->length);
2895 close(block->fd);
2896 } else {
2897 qemu_vfree(block->host);
2898 }
2899#endif
2900 } else {
2901#if defined(TARGET_S390X) && defined(CONFIG_KVM)
2902 munmap(block->host, block->length);
2903#else
2904 qemu_vfree(block->host);
2905#endif
2906 }
2907 qemu_free(block);
2908 return;
2909 }
2910 }
2911
bellarde9a1ab12007-02-08 23:08:38 +00002912}
2913
pbrookdc828ca2009-04-09 22:21:07 +00002914/* Return a host pointer to ram allocated with qemu_ram_alloc.
pbrook5579c7f2009-04-11 14:47:08 +00002915 With the exception of the softmmu code in this file, this should
2916 only be used for local memory (e.g. video ram) that the device owns,
2917 and knows it isn't going to access beyond the end of the block.
2918
2919 It should not be used for general purpose DMA.
2920 Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
2921 */
Anthony Liguoric227f092009-10-01 16:12:16 -05002922void *qemu_get_ram_ptr(ram_addr_t addr)
pbrookdc828ca2009-04-09 22:21:07 +00002923{
pbrook94a6b542009-04-11 17:15:54 +00002924 RAMBlock *block;
2925
Alex Williamsonf471a172010-06-11 11:11:42 -06002926 QLIST_FOREACH(block, &ram_list.blocks, next) {
2927 if (addr - block->offset < block->length) {
2928 QLIST_REMOVE(block, next);
2929 QLIST_INSERT_HEAD(&ram_list.blocks, block, next);
2930 return block->host + (addr - block->offset);
2931 }
pbrook94a6b542009-04-11 17:15:54 +00002932 }
Alex Williamsonf471a172010-06-11 11:11:42 -06002933
2934 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
2935 abort();
2936
2937 return NULL;
pbrookdc828ca2009-04-09 22:21:07 +00002938}
2939
pbrook5579c7f2009-04-11 14:47:08 +00002940/* Some of the softmmu routines need to translate from a host pointer
2941 (typically a TLB entry) back to a ram offset. */
Anthony Liguoric227f092009-10-01 16:12:16 -05002942ram_addr_t qemu_ram_addr_from_host(void *ptr)
pbrook5579c7f2009-04-11 14:47:08 +00002943{
pbrook94a6b542009-04-11 17:15:54 +00002944 RAMBlock *block;
2945 uint8_t *host = ptr;
2946
Alex Williamsonf471a172010-06-11 11:11:42 -06002947 QLIST_FOREACH(block, &ram_list.blocks, next) {
2948 if (host - block->host < block->length) {
2949 return block->offset + (host - block->host);
2950 }
pbrook94a6b542009-04-11 17:15:54 +00002951 }
Alex Williamsonf471a172010-06-11 11:11:42 -06002952
2953 fprintf(stderr, "Bad ram pointer %p\n", ptr);
2954 abort();
2955
2956 return 0;
pbrook5579c7f2009-04-11 14:47:08 +00002957}
2958
Anthony Liguoric227f092009-10-01 16:12:16 -05002959static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
bellard33417e72003-08-10 21:47:01 +00002960{
pbrook67d3b952006-12-18 05:03:52 +00002961#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002962 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
pbrook67d3b952006-12-18 05:03:52 +00002963#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02002964#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00002965 do_unassigned_access(addr, 0, 0, 0, 1);
2966#endif
2967 return 0;
2968}
2969
Anthony Liguoric227f092009-10-01 16:12:16 -05002970static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
blueswir1e18231a2008-10-06 18:46:28 +00002971{
2972#ifdef DEBUG_UNASSIGNED
2973 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2974#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02002975#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00002976 do_unassigned_access(addr, 0, 0, 0, 2);
2977#endif
2978 return 0;
2979}
2980
Anthony Liguoric227f092009-10-01 16:12:16 -05002981static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
blueswir1e18231a2008-10-06 18:46:28 +00002982{
2983#ifdef DEBUG_UNASSIGNED
2984 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2985#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02002986#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00002987 do_unassigned_access(addr, 0, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00002988#endif
bellard33417e72003-08-10 21:47:01 +00002989 return 0;
2990}
2991
Anthony Liguoric227f092009-10-01 16:12:16 -05002992static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard33417e72003-08-10 21:47:01 +00002993{
pbrook67d3b952006-12-18 05:03:52 +00002994#ifdef DEBUG_UNASSIGNED
blueswir1ab3d1722007-11-04 07:31:40 +00002995 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
pbrook67d3b952006-12-18 05:03:52 +00002996#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02002997#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00002998 do_unassigned_access(addr, 1, 0, 0, 1);
2999#endif
3000}
3001
Anthony Liguoric227f092009-10-01 16:12:16 -05003002static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
blueswir1e18231a2008-10-06 18:46:28 +00003003{
3004#ifdef DEBUG_UNASSIGNED
3005 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
3006#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02003007#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00003008 do_unassigned_access(addr, 1, 0, 0, 2);
3009#endif
3010}
3011
Anthony Liguoric227f092009-10-01 16:12:16 -05003012static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
blueswir1e18231a2008-10-06 18:46:28 +00003013{
3014#ifdef DEBUG_UNASSIGNED
3015 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
3016#endif
Edgar E. Iglesiasfaed1c22009-09-03 13:25:09 +02003017#if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
blueswir1e18231a2008-10-06 18:46:28 +00003018 do_unassigned_access(addr, 1, 0, 0, 4);
blueswir1b4f0a312007-05-06 17:59:24 +00003019#endif
bellard33417e72003-08-10 21:47:01 +00003020}
3021
Blue Swirld60efc62009-08-25 18:29:31 +00003022static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
bellard33417e72003-08-10 21:47:01 +00003023 unassigned_mem_readb,
blueswir1e18231a2008-10-06 18:46:28 +00003024 unassigned_mem_readw,
3025 unassigned_mem_readl,
bellard33417e72003-08-10 21:47:01 +00003026};
3027
Blue Swirld60efc62009-08-25 18:29:31 +00003028static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
bellard33417e72003-08-10 21:47:01 +00003029 unassigned_mem_writeb,
blueswir1e18231a2008-10-06 18:46:28 +00003030 unassigned_mem_writew,
3031 unassigned_mem_writel,
bellard33417e72003-08-10 21:47:01 +00003032};
3033
Anthony Liguoric227f092009-10-01 16:12:16 -05003034static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
pbrook0f459d12008-06-09 00:20:13 +00003035 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00003036{
bellard3a7d9292005-08-21 09:26:42 +00003037 int dirty_flags;
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003038 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003039 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
3040#if !defined(CONFIG_USER_ONLY)
3041 tb_invalidate_phys_page_fast(ram_addr, 1);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003042 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003043#endif
3044 }
pbrook5579c7f2009-04-11 14:47:08 +00003045 stb_p(qemu_get_ram_ptr(ram_addr), val);
bellardf23db162005-08-21 19:12:28 +00003046 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003047 cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
bellardf23db162005-08-21 19:12:28 +00003048 /* we remove the notdirty callback only if the code has been
3049 flushed */
3050 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00003051 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00003052}
3053
Anthony Liguoric227f092009-10-01 16:12:16 -05003054static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
pbrook0f459d12008-06-09 00:20:13 +00003055 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00003056{
bellard3a7d9292005-08-21 09:26:42 +00003057 int dirty_flags;
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003058 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003059 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
3060#if !defined(CONFIG_USER_ONLY)
3061 tb_invalidate_phys_page_fast(ram_addr, 2);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003062 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003063#endif
3064 }
pbrook5579c7f2009-04-11 14:47:08 +00003065 stw_p(qemu_get_ram_ptr(ram_addr), val);
bellardf23db162005-08-21 19:12:28 +00003066 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003067 cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
bellardf23db162005-08-21 19:12:28 +00003068 /* we remove the notdirty callback only if the code has been
3069 flushed */
3070 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00003071 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00003072}
3073
Anthony Liguoric227f092009-10-01 16:12:16 -05003074static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
pbrook0f459d12008-06-09 00:20:13 +00003075 uint32_t val)
bellard1ccde1c2004-02-06 19:46:14 +00003076{
bellard3a7d9292005-08-21 09:26:42 +00003077 int dirty_flags;
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003078 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003079 if (!(dirty_flags & CODE_DIRTY_FLAG)) {
3080#if !defined(CONFIG_USER_ONLY)
3081 tb_invalidate_phys_page_fast(ram_addr, 4);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003082 dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
bellard3a7d9292005-08-21 09:26:42 +00003083#endif
3084 }
pbrook5579c7f2009-04-11 14:47:08 +00003085 stl_p(qemu_get_ram_ptr(ram_addr), val);
bellardf23db162005-08-21 19:12:28 +00003086 dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003087 cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
bellardf23db162005-08-21 19:12:28 +00003088 /* we remove the notdirty callback only if the code has been
3089 flushed */
3090 if (dirty_flags == 0xff)
pbrook2e70f6e2008-06-29 01:03:05 +00003091 tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
bellard1ccde1c2004-02-06 19:46:14 +00003092}
3093
Blue Swirld60efc62009-08-25 18:29:31 +00003094static CPUReadMemoryFunc * const error_mem_read[3] = {
bellard3a7d9292005-08-21 09:26:42 +00003095 NULL, /* never used */
3096 NULL, /* never used */
3097 NULL, /* never used */
3098};
3099
Blue Swirld60efc62009-08-25 18:29:31 +00003100static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
bellard1ccde1c2004-02-06 19:46:14 +00003101 notdirty_mem_writeb,
3102 notdirty_mem_writew,
3103 notdirty_mem_writel,
3104};
3105
pbrook0f459d12008-06-09 00:20:13 +00003106/* Generate a debug exception if a watchpoint has been hit. */
aliguorib4051332008-11-18 20:14:20 +00003107static void check_watchpoint(int offset, int len_mask, int flags)
pbrook0f459d12008-06-09 00:20:13 +00003108{
3109 CPUState *env = cpu_single_env;
aliguori06d55cc2008-11-18 20:24:06 +00003110 target_ulong pc, cs_base;
3111 TranslationBlock *tb;
pbrook0f459d12008-06-09 00:20:13 +00003112 target_ulong vaddr;
aliguoria1d1bb32008-11-18 20:07:32 +00003113 CPUWatchpoint *wp;
aliguori06d55cc2008-11-18 20:24:06 +00003114 int cpu_flags;
pbrook0f459d12008-06-09 00:20:13 +00003115
aliguori06d55cc2008-11-18 20:24:06 +00003116 if (env->watchpoint_hit) {
3117 /* We re-entered the check after replacing the TB. Now raise
3118 * the debug interrupt so that is will trigger after the
3119 * current instruction. */
3120 cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
3121 return;
3122 }
pbrook2e70f6e2008-06-29 01:03:05 +00003123 vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
Blue Swirl72cf2d42009-09-12 07:36:22 +00003124 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
aliguorib4051332008-11-18 20:14:20 +00003125 if ((vaddr == (wp->vaddr & len_mask) ||
3126 (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
aliguori6e140f22008-11-18 20:37:55 +00003127 wp->flags |= BP_WATCHPOINT_HIT;
3128 if (!env->watchpoint_hit) {
3129 env->watchpoint_hit = wp;
3130 tb = tb_find_pc(env->mem_io_pc);
3131 if (!tb) {
3132 cpu_abort(env, "check_watchpoint: could not find TB for "
3133 "pc=%p", (void *)env->mem_io_pc);
3134 }
3135 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
3136 tb_phys_invalidate(tb, -1);
3137 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
3138 env->exception_index = EXCP_DEBUG;
3139 } else {
3140 cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
3141 tb_gen_code(env, pc, cs_base, cpu_flags, 1);
3142 }
3143 cpu_resume_from_signal(env, NULL);
aliguori06d55cc2008-11-18 20:24:06 +00003144 }
aliguori6e140f22008-11-18 20:37:55 +00003145 } else {
3146 wp->flags &= ~BP_WATCHPOINT_HIT;
pbrook0f459d12008-06-09 00:20:13 +00003147 }
3148 }
3149}
3150
pbrook6658ffb2007-03-16 23:58:11 +00003151/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
3152 so these check for a hit then pass through to the normal out-of-line
3153 phys routines. */
Anthony Liguoric227f092009-10-01 16:12:16 -05003154static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
pbrook6658ffb2007-03-16 23:58:11 +00003155{
aliguorib4051332008-11-18 20:14:20 +00003156 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00003157 return ldub_phys(addr);
3158}
3159
Anthony Liguoric227f092009-10-01 16:12:16 -05003160static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
pbrook6658ffb2007-03-16 23:58:11 +00003161{
aliguorib4051332008-11-18 20:14:20 +00003162 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00003163 return lduw_phys(addr);
3164}
3165
Anthony Liguoric227f092009-10-01 16:12:16 -05003166static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
pbrook6658ffb2007-03-16 23:58:11 +00003167{
aliguorib4051332008-11-18 20:14:20 +00003168 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
pbrook6658ffb2007-03-16 23:58:11 +00003169 return ldl_phys(addr);
3170}
3171
Anthony Liguoric227f092009-10-01 16:12:16 -05003172static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
pbrook6658ffb2007-03-16 23:58:11 +00003173 uint32_t val)
3174{
aliguorib4051332008-11-18 20:14:20 +00003175 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00003176 stb_phys(addr, val);
3177}
3178
Anthony Liguoric227f092009-10-01 16:12:16 -05003179static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
pbrook6658ffb2007-03-16 23:58:11 +00003180 uint32_t val)
3181{
aliguorib4051332008-11-18 20:14:20 +00003182 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00003183 stw_phys(addr, val);
3184}
3185
Anthony Liguoric227f092009-10-01 16:12:16 -05003186static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
pbrook6658ffb2007-03-16 23:58:11 +00003187 uint32_t val)
3188{
aliguorib4051332008-11-18 20:14:20 +00003189 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
pbrook6658ffb2007-03-16 23:58:11 +00003190 stl_phys(addr, val);
3191}
3192
Blue Swirld60efc62009-08-25 18:29:31 +00003193static CPUReadMemoryFunc * const watch_mem_read[3] = {
pbrook6658ffb2007-03-16 23:58:11 +00003194 watch_mem_readb,
3195 watch_mem_readw,
3196 watch_mem_readl,
3197};
3198
Blue Swirld60efc62009-08-25 18:29:31 +00003199static CPUWriteMemoryFunc * const watch_mem_write[3] = {
pbrook6658ffb2007-03-16 23:58:11 +00003200 watch_mem_writeb,
3201 watch_mem_writew,
3202 watch_mem_writel,
3203};
pbrook6658ffb2007-03-16 23:58:11 +00003204
Richard Hendersonf6405242010-04-22 16:47:31 -07003205static inline uint32_t subpage_readlen (subpage_t *mmio,
3206 target_phys_addr_t addr,
3207 unsigned int len)
blueswir1db7b5422007-05-26 17:36:03 +00003208{
Richard Hendersonf6405242010-04-22 16:47:31 -07003209 unsigned int idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00003210#if defined(DEBUG_SUBPAGE)
3211 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
3212 mmio, len, addr, idx);
3213#endif
blueswir1db7b5422007-05-26 17:36:03 +00003214
Richard Hendersonf6405242010-04-22 16:47:31 -07003215 addr += mmio->region_offset[idx];
3216 idx = mmio->sub_io_index[idx];
3217 return io_mem_read[idx][len](io_mem_opaque[idx], addr);
blueswir1db7b5422007-05-26 17:36:03 +00003218}
3219
Anthony Liguoric227f092009-10-01 16:12:16 -05003220static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
Richard Hendersonf6405242010-04-22 16:47:31 -07003221 uint32_t value, unsigned int len)
blueswir1db7b5422007-05-26 17:36:03 +00003222{
Richard Hendersonf6405242010-04-22 16:47:31 -07003223 unsigned int idx = SUBPAGE_IDX(addr);
blueswir1db7b5422007-05-26 17:36:03 +00003224#if defined(DEBUG_SUBPAGE)
Richard Hendersonf6405242010-04-22 16:47:31 -07003225 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n",
3226 __func__, mmio, len, addr, idx, value);
blueswir1db7b5422007-05-26 17:36:03 +00003227#endif
Richard Hendersonf6405242010-04-22 16:47:31 -07003228
3229 addr += mmio->region_offset[idx];
3230 idx = mmio->sub_io_index[idx];
3231 io_mem_write[idx][len](io_mem_opaque[idx], addr, value);
blueswir1db7b5422007-05-26 17:36:03 +00003232}
3233
Anthony Liguoric227f092009-10-01 16:12:16 -05003234static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
blueswir1db7b5422007-05-26 17:36:03 +00003235{
blueswir1db7b5422007-05-26 17:36:03 +00003236 return subpage_readlen(opaque, addr, 0);
3237}
3238
Anthony Liguoric227f092009-10-01 16:12:16 -05003239static void subpage_writeb (void *opaque, target_phys_addr_t addr,
blueswir1db7b5422007-05-26 17:36:03 +00003240 uint32_t value)
3241{
blueswir1db7b5422007-05-26 17:36:03 +00003242 subpage_writelen(opaque, addr, value, 0);
3243}
3244
Anthony Liguoric227f092009-10-01 16:12:16 -05003245static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
blueswir1db7b5422007-05-26 17:36:03 +00003246{
blueswir1db7b5422007-05-26 17:36:03 +00003247 return subpage_readlen(opaque, addr, 1);
3248}
3249
Anthony Liguoric227f092009-10-01 16:12:16 -05003250static void subpage_writew (void *opaque, target_phys_addr_t addr,
blueswir1db7b5422007-05-26 17:36:03 +00003251 uint32_t value)
3252{
blueswir1db7b5422007-05-26 17:36:03 +00003253 subpage_writelen(opaque, addr, value, 1);
3254}
3255
Anthony Liguoric227f092009-10-01 16:12:16 -05003256static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
blueswir1db7b5422007-05-26 17:36:03 +00003257{
blueswir1db7b5422007-05-26 17:36:03 +00003258 return subpage_readlen(opaque, addr, 2);
3259}
3260
Richard Hendersonf6405242010-04-22 16:47:31 -07003261static void subpage_writel (void *opaque, target_phys_addr_t addr,
3262 uint32_t value)
blueswir1db7b5422007-05-26 17:36:03 +00003263{
blueswir1db7b5422007-05-26 17:36:03 +00003264 subpage_writelen(opaque, addr, value, 2);
3265}
3266
Blue Swirld60efc62009-08-25 18:29:31 +00003267static CPUReadMemoryFunc * const subpage_read[] = {
blueswir1db7b5422007-05-26 17:36:03 +00003268 &subpage_readb,
3269 &subpage_readw,
3270 &subpage_readl,
3271};
3272
Blue Swirld60efc62009-08-25 18:29:31 +00003273static CPUWriteMemoryFunc * const subpage_write[] = {
blueswir1db7b5422007-05-26 17:36:03 +00003274 &subpage_writeb,
3275 &subpage_writew,
3276 &subpage_writel,
3277};
3278
Anthony Liguoric227f092009-10-01 16:12:16 -05003279static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
3280 ram_addr_t memory, ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00003281{
3282 int idx, eidx;
3283
3284 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
3285 return -1;
3286 idx = SUBPAGE_IDX(start);
3287 eidx = SUBPAGE_IDX(end);
3288#if defined(DEBUG_SUBPAGE)
Blue Swirl0bf9e312009-07-20 17:19:25 +00003289 printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
blueswir1db7b5422007-05-26 17:36:03 +00003290 mmio, start, end, idx, eidx, memory);
3291#endif
Gleb Natapov95c318f2010-07-29 10:41:45 +03003292 if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
3293 memory = IO_MEM_UNASSIGNED;
Richard Hendersonf6405242010-04-22 16:47:31 -07003294 memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
blueswir1db7b5422007-05-26 17:36:03 +00003295 for (; idx <= eidx; idx++) {
Richard Hendersonf6405242010-04-22 16:47:31 -07003296 mmio->sub_io_index[idx] = memory;
3297 mmio->region_offset[idx] = region_offset;
blueswir1db7b5422007-05-26 17:36:03 +00003298 }
3299
3300 return 0;
3301}
3302
Richard Hendersonf6405242010-04-22 16:47:31 -07003303static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
3304 ram_addr_t orig_memory,
3305 ram_addr_t region_offset)
blueswir1db7b5422007-05-26 17:36:03 +00003306{
Anthony Liguoric227f092009-10-01 16:12:16 -05003307 subpage_t *mmio;
blueswir1db7b5422007-05-26 17:36:03 +00003308 int subpage_memory;
3309
Anthony Liguoric227f092009-10-01 16:12:16 -05003310 mmio = qemu_mallocz(sizeof(subpage_t));
aliguori1eec6142009-02-05 22:06:18 +00003311
3312 mmio->base = base;
Avi Kivity1eed09c2009-06-14 11:38:51 +03003313 subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
blueswir1db7b5422007-05-26 17:36:03 +00003314#if defined(DEBUG_SUBPAGE)
aliguori1eec6142009-02-05 22:06:18 +00003315 printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
3316 mmio, base, TARGET_PAGE_SIZE, subpage_memory);
blueswir1db7b5422007-05-26 17:36:03 +00003317#endif
aliguori1eec6142009-02-05 22:06:18 +00003318 *phys = subpage_memory | IO_MEM_SUBPAGE;
Richard Hendersonf6405242010-04-22 16:47:31 -07003319 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset);
blueswir1db7b5422007-05-26 17:36:03 +00003320
3321 return mmio;
3322}
3323
aliguori88715652009-02-11 15:20:58 +00003324static int get_free_io_mem_idx(void)
3325{
3326 int i;
3327
3328 for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
3329 if (!io_mem_used[i]) {
3330 io_mem_used[i] = 1;
3331 return i;
3332 }
Riku Voipioc6703b42009-12-03 15:56:05 +02003333 fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES);
aliguori88715652009-02-11 15:20:58 +00003334 return -1;
3335}
3336
bellard33417e72003-08-10 21:47:01 +00003337/* mem_read and mem_write are arrays of functions containing the
3338 function to access byte (index 0), word (index 1) and dword (index
Paul Brook0b4e6e32009-04-30 18:37:55 +01003339 2). Functions can be omitted with a NULL function pointer.
blueswir13ee89922008-01-02 19:45:26 +00003340 If io_index is non zero, the corresponding io zone is
blueswir14254fab2008-01-01 16:57:19 +00003341 modified. If it is zero, a new io zone is allocated. The return
3342 value can be used with cpu_register_physical_memory(). (-1) is
3343 returned if error. */
Avi Kivity1eed09c2009-06-14 11:38:51 +03003344static int cpu_register_io_memory_fixed(int io_index,
Blue Swirld60efc62009-08-25 18:29:31 +00003345 CPUReadMemoryFunc * const *mem_read,
3346 CPUWriteMemoryFunc * const *mem_write,
Avi Kivity1eed09c2009-06-14 11:38:51 +03003347 void *opaque)
bellard33417e72003-08-10 21:47:01 +00003348{
Richard Henderson3cab7212010-05-07 09:52:51 -07003349 int i;
3350
bellard33417e72003-08-10 21:47:01 +00003351 if (io_index <= 0) {
aliguori88715652009-02-11 15:20:58 +00003352 io_index = get_free_io_mem_idx();
3353 if (io_index == -1)
3354 return io_index;
bellard33417e72003-08-10 21:47:01 +00003355 } else {
Avi Kivity1eed09c2009-06-14 11:38:51 +03003356 io_index >>= IO_MEM_SHIFT;
bellard33417e72003-08-10 21:47:01 +00003357 if (io_index >= IO_MEM_NB_ENTRIES)
3358 return -1;
3359 }
bellardb5ff1b32005-11-26 10:38:39 +00003360
Richard Henderson3cab7212010-05-07 09:52:51 -07003361 for (i = 0; i < 3; ++i) {
3362 io_mem_read[io_index][i]
3363 = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]);
3364 }
3365 for (i = 0; i < 3; ++i) {
3366 io_mem_write[io_index][i]
3367 = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]);
3368 }
bellarda4193c82004-06-03 14:01:43 +00003369 io_mem_opaque[io_index] = opaque;
Richard Hendersonf6405242010-04-22 16:47:31 -07003370
3371 return (io_index << IO_MEM_SHIFT);
bellard33417e72003-08-10 21:47:01 +00003372}
bellard61382a52003-10-27 21:22:23 +00003373
Blue Swirld60efc62009-08-25 18:29:31 +00003374int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
3375 CPUWriteMemoryFunc * const *mem_write,
Avi Kivity1eed09c2009-06-14 11:38:51 +03003376 void *opaque)
3377{
3378 return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
3379}
3380
aliguori88715652009-02-11 15:20:58 +00003381void cpu_unregister_io_memory(int io_table_address)
3382{
3383 int i;
3384 int io_index = io_table_address >> IO_MEM_SHIFT;
3385
3386 for (i=0;i < 3; i++) {
3387 io_mem_read[io_index][i] = unassigned_mem_read[i];
3388 io_mem_write[io_index][i] = unassigned_mem_write[i];
3389 }
3390 io_mem_opaque[io_index] = NULL;
3391 io_mem_used[io_index] = 0;
3392}
3393
Avi Kivitye9179ce2009-06-14 11:38:52 +03003394static void io_mem_init(void)
3395{
3396 int i;
3397
3398 cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
3399 cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
3400 cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
3401 for (i=0; i<5; i++)
3402 io_mem_used[i] = 1;
3403
3404 io_mem_watch = cpu_register_io_memory(watch_mem_read,
3405 watch_mem_write, NULL);
Avi Kivitye9179ce2009-06-14 11:38:52 +03003406}
3407
pbrooke2eef172008-06-08 01:09:01 +00003408#endif /* !defined(CONFIG_USER_ONLY) */
3409
bellard13eb76e2004-01-24 15:23:36 +00003410/* physical memory access (slow version, mainly for debug) */
3411#if defined(CONFIG_USER_ONLY)
Paul Brooka68fe892010-03-01 00:08:59 +00003412int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3413 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00003414{
3415 int l, flags;
3416 target_ulong page;
pbrook53a59602006-03-25 19:31:22 +00003417 void * p;
bellard13eb76e2004-01-24 15:23:36 +00003418
3419 while (len > 0) {
3420 page = addr & TARGET_PAGE_MASK;
3421 l = (page + TARGET_PAGE_SIZE) - addr;
3422 if (l > len)
3423 l = len;
3424 flags = page_get_flags(page);
3425 if (!(flags & PAGE_VALID))
Paul Brooka68fe892010-03-01 00:08:59 +00003426 return -1;
bellard13eb76e2004-01-24 15:23:36 +00003427 if (is_write) {
3428 if (!(flags & PAGE_WRITE))
Paul Brooka68fe892010-03-01 00:08:59 +00003429 return -1;
bellard579a97f2007-11-11 14:26:47 +00003430 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00003431 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
Paul Brooka68fe892010-03-01 00:08:59 +00003432 return -1;
aurel3272fb7da2008-04-27 23:53:45 +00003433 memcpy(p, buf, l);
3434 unlock_user(p, addr, l);
bellard13eb76e2004-01-24 15:23:36 +00003435 } else {
3436 if (!(flags & PAGE_READ))
Paul Brooka68fe892010-03-01 00:08:59 +00003437 return -1;
bellard579a97f2007-11-11 14:26:47 +00003438 /* XXX: this code should not depend on lock_user */
aurel3272fb7da2008-04-27 23:53:45 +00003439 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
Paul Brooka68fe892010-03-01 00:08:59 +00003440 return -1;
aurel3272fb7da2008-04-27 23:53:45 +00003441 memcpy(buf, p, l);
aurel325b257572008-04-28 08:54:59 +00003442 unlock_user(p, addr, 0);
bellard13eb76e2004-01-24 15:23:36 +00003443 }
3444 len -= l;
3445 buf += l;
3446 addr += l;
3447 }
Paul Brooka68fe892010-03-01 00:08:59 +00003448 return 0;
bellard13eb76e2004-01-24 15:23:36 +00003449}
bellard8df1cd02005-01-28 22:37:22 +00003450
bellard13eb76e2004-01-24 15:23:36 +00003451#else
Anthony Liguoric227f092009-10-01 16:12:16 -05003452void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +00003453 int len, int is_write)
3454{
3455 int l, io_index;
3456 uint8_t *ptr;
3457 uint32_t val;
Anthony Liguoric227f092009-10-01 16:12:16 -05003458 target_phys_addr_t page;
bellard2e126692004-04-25 21:28:44 +00003459 unsigned long pd;
bellard92e873b2004-05-21 14:52:29 +00003460 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00003461
bellard13eb76e2004-01-24 15:23:36 +00003462 while (len > 0) {
3463 page = addr & TARGET_PAGE_MASK;
3464 l = (page + TARGET_PAGE_SIZE) - addr;
3465 if (l > len)
3466 l = len;
bellard92e873b2004-05-21 14:52:29 +00003467 p = phys_page_find(page >> TARGET_PAGE_BITS);
bellard13eb76e2004-01-24 15:23:36 +00003468 if (!p) {
3469 pd = IO_MEM_UNASSIGNED;
3470 } else {
3471 pd = p->phys_offset;
3472 }
ths3b46e622007-09-17 08:09:54 +00003473
bellard13eb76e2004-01-24 15:23:36 +00003474 if (is_write) {
bellard3a7d9292005-08-21 09:26:42 +00003475 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
Anthony Liguoric227f092009-10-01 16:12:16 -05003476 target_phys_addr_t addr1 = addr;
bellard13eb76e2004-01-24 15:23:36 +00003477 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003478 if (p)
aurel326c2934d2009-02-18 21:37:17 +00003479 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard6a00d602005-11-21 23:25:50 +00003480 /* XXX: could force cpu_single_env to NULL to avoid
3481 potential bugs */
aurel326c2934d2009-02-18 21:37:17 +00003482 if (l >= 4 && ((addr1 & 3) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00003483 /* 32 bit write access */
bellardc27004e2005-01-03 23:35:10 +00003484 val = ldl_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00003485 io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00003486 l = 4;
aurel326c2934d2009-02-18 21:37:17 +00003487 } else if (l >= 2 && ((addr1 & 1) == 0)) {
bellard1c213d12005-09-03 10:49:04 +00003488 /* 16 bit write access */
bellardc27004e2005-01-03 23:35:10 +00003489 val = lduw_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00003490 io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00003491 l = 2;
3492 } else {
bellard1c213d12005-09-03 10:49:04 +00003493 /* 8 bit write access */
bellardc27004e2005-01-03 23:35:10 +00003494 val = ldub_p(buf);
aurel326c2934d2009-02-18 21:37:17 +00003495 io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
bellard13eb76e2004-01-24 15:23:36 +00003496 l = 1;
3497 }
3498 } else {
bellardb448f2f2004-02-25 23:24:04 +00003499 unsigned long addr1;
3500 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
bellard13eb76e2004-01-24 15:23:36 +00003501 /* RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003502 ptr = qemu_get_ram_ptr(addr1);
bellard13eb76e2004-01-24 15:23:36 +00003503 memcpy(ptr, buf, l);
bellard3a7d9292005-08-21 09:26:42 +00003504 if (!cpu_physical_memory_is_dirty(addr1)) {
3505 /* invalidate code */
3506 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3507 /* set dirty bit */
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003508 cpu_physical_memory_set_dirty_flags(
3509 addr1, (0xff & ~CODE_DIRTY_FLAG));
bellard3a7d9292005-08-21 09:26:42 +00003510 }
bellard13eb76e2004-01-24 15:23:36 +00003511 }
3512 } else {
ths5fafdf22007-09-16 21:08:06 +00003513 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00003514 !(pd & IO_MEM_ROMD)) {
Anthony Liguoric227f092009-10-01 16:12:16 -05003515 target_phys_addr_t addr1 = addr;
bellard13eb76e2004-01-24 15:23:36 +00003516 /* I/O case */
3517 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003518 if (p)
aurel326c2934d2009-02-18 21:37:17 +00003519 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3520 if (l >= 4 && ((addr1 & 3) == 0)) {
bellard13eb76e2004-01-24 15:23:36 +00003521 /* 32 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003522 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003523 stl_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003524 l = 4;
aurel326c2934d2009-02-18 21:37:17 +00003525 } else if (l >= 2 && ((addr1 & 1) == 0)) {
bellard13eb76e2004-01-24 15:23:36 +00003526 /* 16 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003527 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003528 stw_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003529 l = 2;
3530 } else {
bellard1c213d12005-09-03 10:49:04 +00003531 /* 8 bit read access */
aurel326c2934d2009-02-18 21:37:17 +00003532 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
bellardc27004e2005-01-03 23:35:10 +00003533 stb_p(buf, val);
bellard13eb76e2004-01-24 15:23:36 +00003534 l = 1;
3535 }
3536 } else {
3537 /* RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003538 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
bellard13eb76e2004-01-24 15:23:36 +00003539 (addr & ~TARGET_PAGE_MASK);
3540 memcpy(buf, ptr, l);
3541 }
3542 }
3543 len -= l;
3544 buf += l;
3545 addr += l;
3546 }
3547}
bellard8df1cd02005-01-28 22:37:22 +00003548
bellardd0ecd2a2006-04-23 17:14:48 +00003549/* used for ROM loading : can write in RAM and ROM */
Anthony Liguoric227f092009-10-01 16:12:16 -05003550void cpu_physical_memory_write_rom(target_phys_addr_t addr,
bellardd0ecd2a2006-04-23 17:14:48 +00003551 const uint8_t *buf, int len)
3552{
3553 int l;
3554 uint8_t *ptr;
Anthony Liguoric227f092009-10-01 16:12:16 -05003555 target_phys_addr_t page;
bellardd0ecd2a2006-04-23 17:14:48 +00003556 unsigned long pd;
3557 PhysPageDesc *p;
ths3b46e622007-09-17 08:09:54 +00003558
bellardd0ecd2a2006-04-23 17:14:48 +00003559 while (len > 0) {
3560 page = addr & TARGET_PAGE_MASK;
3561 l = (page + TARGET_PAGE_SIZE) - addr;
3562 if (l > len)
3563 l = len;
3564 p = phys_page_find(page >> TARGET_PAGE_BITS);
3565 if (!p) {
3566 pd = IO_MEM_UNASSIGNED;
3567 } else {
3568 pd = p->phys_offset;
3569 }
ths3b46e622007-09-17 08:09:54 +00003570
bellardd0ecd2a2006-04-23 17:14:48 +00003571 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
bellard2a4188a2006-06-25 21:54:59 +00003572 (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
3573 !(pd & IO_MEM_ROMD)) {
bellardd0ecd2a2006-04-23 17:14:48 +00003574 /* do nothing */
3575 } else {
3576 unsigned long addr1;
3577 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3578 /* ROM/RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003579 ptr = qemu_get_ram_ptr(addr1);
bellardd0ecd2a2006-04-23 17:14:48 +00003580 memcpy(ptr, buf, l);
3581 }
3582 len -= l;
3583 buf += l;
3584 addr += l;
3585 }
3586}
3587
aliguori6d16c2f2009-01-22 16:59:11 +00003588typedef struct {
3589 void *buffer;
Anthony Liguoric227f092009-10-01 16:12:16 -05003590 target_phys_addr_t addr;
3591 target_phys_addr_t len;
aliguori6d16c2f2009-01-22 16:59:11 +00003592} BounceBuffer;
3593
3594static BounceBuffer bounce;
3595
aliguoriba223c22009-01-22 16:59:16 +00003596typedef struct MapClient {
3597 void *opaque;
3598 void (*callback)(void *opaque);
Blue Swirl72cf2d42009-09-12 07:36:22 +00003599 QLIST_ENTRY(MapClient) link;
aliguoriba223c22009-01-22 16:59:16 +00003600} MapClient;
3601
Blue Swirl72cf2d42009-09-12 07:36:22 +00003602static QLIST_HEAD(map_client_list, MapClient) map_client_list
3603 = QLIST_HEAD_INITIALIZER(map_client_list);
aliguoriba223c22009-01-22 16:59:16 +00003604
3605void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
3606{
3607 MapClient *client = qemu_malloc(sizeof(*client));
3608
3609 client->opaque = opaque;
3610 client->callback = callback;
Blue Swirl72cf2d42009-09-12 07:36:22 +00003611 QLIST_INSERT_HEAD(&map_client_list, client, link);
aliguoriba223c22009-01-22 16:59:16 +00003612 return client;
3613}
3614
3615void cpu_unregister_map_client(void *_client)
3616{
3617 MapClient *client = (MapClient *)_client;
3618
Blue Swirl72cf2d42009-09-12 07:36:22 +00003619 QLIST_REMOVE(client, link);
Isaku Yamahata34d5e942009-06-26 18:57:18 +09003620 qemu_free(client);
aliguoriba223c22009-01-22 16:59:16 +00003621}
3622
3623static void cpu_notify_map_clients(void)
3624{
3625 MapClient *client;
3626
Blue Swirl72cf2d42009-09-12 07:36:22 +00003627 while (!QLIST_EMPTY(&map_client_list)) {
3628 client = QLIST_FIRST(&map_client_list);
aliguoriba223c22009-01-22 16:59:16 +00003629 client->callback(client->opaque);
Isaku Yamahata34d5e942009-06-26 18:57:18 +09003630 cpu_unregister_map_client(client);
aliguoriba223c22009-01-22 16:59:16 +00003631 }
3632}
3633
aliguori6d16c2f2009-01-22 16:59:11 +00003634/* Map a physical memory region into a host virtual address.
3635 * May map a subset of the requested range, given by and returned in *plen.
3636 * May return NULL if resources needed to perform the mapping are exhausted.
3637 * Use only for reads OR writes - not for read-modify-write operations.
aliguoriba223c22009-01-22 16:59:16 +00003638 * Use cpu_register_map_client() to know when retrying the map operation is
3639 * likely to succeed.
aliguori6d16c2f2009-01-22 16:59:11 +00003640 */
Anthony Liguoric227f092009-10-01 16:12:16 -05003641void *cpu_physical_memory_map(target_phys_addr_t addr,
3642 target_phys_addr_t *plen,
aliguori6d16c2f2009-01-22 16:59:11 +00003643 int is_write)
3644{
Anthony Liguoric227f092009-10-01 16:12:16 -05003645 target_phys_addr_t len = *plen;
3646 target_phys_addr_t done = 0;
aliguori6d16c2f2009-01-22 16:59:11 +00003647 int l;
3648 uint8_t *ret = NULL;
3649 uint8_t *ptr;
Anthony Liguoric227f092009-10-01 16:12:16 -05003650 target_phys_addr_t page;
aliguori6d16c2f2009-01-22 16:59:11 +00003651 unsigned long pd;
3652 PhysPageDesc *p;
3653 unsigned long addr1;
3654
3655 while (len > 0) {
3656 page = addr & TARGET_PAGE_MASK;
3657 l = (page + TARGET_PAGE_SIZE) - addr;
3658 if (l > len)
3659 l = len;
3660 p = phys_page_find(page >> TARGET_PAGE_BITS);
3661 if (!p) {
3662 pd = IO_MEM_UNASSIGNED;
3663 } else {
3664 pd = p->phys_offset;
3665 }
3666
3667 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3668 if (done || bounce.buffer) {
3669 break;
3670 }
3671 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
3672 bounce.addr = addr;
3673 bounce.len = l;
3674 if (!is_write) {
3675 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3676 }
3677 ptr = bounce.buffer;
3678 } else {
3679 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
pbrook5579c7f2009-04-11 14:47:08 +00003680 ptr = qemu_get_ram_ptr(addr1);
aliguori6d16c2f2009-01-22 16:59:11 +00003681 }
3682 if (!done) {
3683 ret = ptr;
3684 } else if (ret + done != ptr) {
3685 break;
3686 }
3687
3688 len -= l;
3689 addr += l;
3690 done += l;
3691 }
3692 *plen = done;
3693 return ret;
3694}
3695
3696/* Unmaps a memory region previously mapped by cpu_physical_memory_map().
3697 * Will also mark the memory as dirty if is_write == 1. access_len gives
3698 * the amount of memory that was actually read or written by the caller.
3699 */
Anthony Liguoric227f092009-10-01 16:12:16 -05003700void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
3701 int is_write, target_phys_addr_t access_len)
aliguori6d16c2f2009-01-22 16:59:11 +00003702{
3703 if (buffer != bounce.buffer) {
3704 if (is_write) {
Anthony Liguoric227f092009-10-01 16:12:16 -05003705 ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
aliguori6d16c2f2009-01-22 16:59:11 +00003706 while (access_len) {
3707 unsigned l;
3708 l = TARGET_PAGE_SIZE;
3709 if (l > access_len)
3710 l = access_len;
3711 if (!cpu_physical_memory_is_dirty(addr1)) {
3712 /* invalidate code */
3713 tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
3714 /* set dirty bit */
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003715 cpu_physical_memory_set_dirty_flags(
3716 addr1, (0xff & ~CODE_DIRTY_FLAG));
aliguori6d16c2f2009-01-22 16:59:11 +00003717 }
3718 addr1 += l;
3719 access_len -= l;
3720 }
3721 }
3722 return;
3723 }
3724 if (is_write) {
3725 cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3726 }
Herve Poussineauf8a83242010-01-24 21:23:56 +00003727 qemu_vfree(bounce.buffer);
aliguori6d16c2f2009-01-22 16:59:11 +00003728 bounce.buffer = NULL;
aliguoriba223c22009-01-22 16:59:16 +00003729 cpu_notify_map_clients();
aliguori6d16c2f2009-01-22 16:59:11 +00003730}
bellardd0ecd2a2006-04-23 17:14:48 +00003731
bellard8df1cd02005-01-28 22:37:22 +00003732/* warning: addr must be aligned */
Anthony Liguoric227f092009-10-01 16:12:16 -05003733uint32_t ldl_phys(target_phys_addr_t addr)
bellard8df1cd02005-01-28 22:37:22 +00003734{
3735 int io_index;
3736 uint8_t *ptr;
3737 uint32_t val;
3738 unsigned long pd;
3739 PhysPageDesc *p;
3740
3741 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3742 if (!p) {
3743 pd = IO_MEM_UNASSIGNED;
3744 } else {
3745 pd = p->phys_offset;
3746 }
ths3b46e622007-09-17 08:09:54 +00003747
ths5fafdf22007-09-16 21:08:06 +00003748 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
bellard2a4188a2006-06-25 21:54:59 +00003749 !(pd & IO_MEM_ROMD)) {
bellard8df1cd02005-01-28 22:37:22 +00003750 /* I/O case */
3751 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003752 if (p)
3753 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003754 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3755 } else {
3756 /* RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003757 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
bellard8df1cd02005-01-28 22:37:22 +00003758 (addr & ~TARGET_PAGE_MASK);
3759 val = ldl_p(ptr);
3760 }
3761 return val;
3762}
3763
bellard84b7b8e2005-11-28 21:19:04 +00003764/* warning: addr must be aligned */
Anthony Liguoric227f092009-10-01 16:12:16 -05003765uint64_t ldq_phys(target_phys_addr_t addr)
bellard84b7b8e2005-11-28 21:19:04 +00003766{
3767 int io_index;
3768 uint8_t *ptr;
3769 uint64_t val;
3770 unsigned long pd;
3771 PhysPageDesc *p;
3772
3773 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3774 if (!p) {
3775 pd = IO_MEM_UNASSIGNED;
3776 } else {
3777 pd = p->phys_offset;
3778 }
ths3b46e622007-09-17 08:09:54 +00003779
bellard2a4188a2006-06-25 21:54:59 +00003780 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3781 !(pd & IO_MEM_ROMD)) {
bellard84b7b8e2005-11-28 21:19:04 +00003782 /* I/O case */
3783 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003784 if (p)
3785 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard84b7b8e2005-11-28 21:19:04 +00003786#ifdef TARGET_WORDS_BIGENDIAN
3787 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3788 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3789#else
3790 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3791 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3792#endif
3793 } else {
3794 /* RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003795 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
bellard84b7b8e2005-11-28 21:19:04 +00003796 (addr & ~TARGET_PAGE_MASK);
3797 val = ldq_p(ptr);
3798 }
3799 return val;
3800}
3801
bellardaab33092005-10-30 20:48:42 +00003802/* XXX: optimize */
Anthony Liguoric227f092009-10-01 16:12:16 -05003803uint32_t ldub_phys(target_phys_addr_t addr)
bellardaab33092005-10-30 20:48:42 +00003804{
3805 uint8_t val;
3806 cpu_physical_memory_read(addr, &val, 1);
3807 return val;
3808}
3809
Michael S. Tsirkin733f0b02010-04-06 14:18:19 +03003810/* warning: addr must be aligned */
Anthony Liguoric227f092009-10-01 16:12:16 -05003811uint32_t lduw_phys(target_phys_addr_t addr)
bellardaab33092005-10-30 20:48:42 +00003812{
Michael S. Tsirkin733f0b02010-04-06 14:18:19 +03003813 int io_index;
3814 uint8_t *ptr;
3815 uint64_t val;
3816 unsigned long pd;
3817 PhysPageDesc *p;
3818
3819 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3820 if (!p) {
3821 pd = IO_MEM_UNASSIGNED;
3822 } else {
3823 pd = p->phys_offset;
3824 }
3825
3826 if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
3827 !(pd & IO_MEM_ROMD)) {
3828 /* I/O case */
3829 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3830 if (p)
3831 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3832 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
3833 } else {
3834 /* RAM case */
3835 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
3836 (addr & ~TARGET_PAGE_MASK);
3837 val = lduw_p(ptr);
3838 }
3839 return val;
bellardaab33092005-10-30 20:48:42 +00003840}
3841
bellard8df1cd02005-01-28 22:37:22 +00003842/* warning: addr must be aligned. The ram page is not masked as dirty
3843 and the code inside is not invalidated. It is useful if the dirty
3844 bits are used to track modified PTEs */
Anthony Liguoric227f092009-10-01 16:12:16 -05003845void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
bellard8df1cd02005-01-28 22:37:22 +00003846{
3847 int io_index;
3848 uint8_t *ptr;
3849 unsigned long pd;
3850 PhysPageDesc *p;
3851
3852 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3853 if (!p) {
3854 pd = IO_MEM_UNASSIGNED;
3855 } else {
3856 pd = p->phys_offset;
3857 }
ths3b46e622007-09-17 08:09:54 +00003858
bellard3a7d9292005-08-21 09:26:42 +00003859 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003860 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003861 if (p)
3862 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003863 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3864 } else {
aliguori74576192008-10-06 14:02:03 +00003865 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
pbrook5579c7f2009-04-11 14:47:08 +00003866 ptr = qemu_get_ram_ptr(addr1);
bellard8df1cd02005-01-28 22:37:22 +00003867 stl_p(ptr, val);
aliguori74576192008-10-06 14:02:03 +00003868
3869 if (unlikely(in_migration)) {
3870 if (!cpu_physical_memory_is_dirty(addr1)) {
3871 /* invalidate code */
3872 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3873 /* set dirty bit */
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003874 cpu_physical_memory_set_dirty_flags(
3875 addr1, (0xff & ~CODE_DIRTY_FLAG));
aliguori74576192008-10-06 14:02:03 +00003876 }
3877 }
bellard8df1cd02005-01-28 22:37:22 +00003878 }
3879}
3880
Anthony Liguoric227f092009-10-01 16:12:16 -05003881void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
j_mayerbc98a7e2007-04-04 07:55:12 +00003882{
3883 int io_index;
3884 uint8_t *ptr;
3885 unsigned long pd;
3886 PhysPageDesc *p;
3887
3888 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3889 if (!p) {
3890 pd = IO_MEM_UNASSIGNED;
3891 } else {
3892 pd = p->phys_offset;
3893 }
ths3b46e622007-09-17 08:09:54 +00003894
j_mayerbc98a7e2007-04-04 07:55:12 +00003895 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3896 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003897 if (p)
3898 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
j_mayerbc98a7e2007-04-04 07:55:12 +00003899#ifdef TARGET_WORDS_BIGENDIAN
3900 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3901 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3902#else
3903 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3904 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3905#endif
3906 } else {
pbrook5579c7f2009-04-11 14:47:08 +00003907 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
j_mayerbc98a7e2007-04-04 07:55:12 +00003908 (addr & ~TARGET_PAGE_MASK);
3909 stq_p(ptr, val);
3910 }
3911}
3912
bellard8df1cd02005-01-28 22:37:22 +00003913/* warning: addr must be aligned */
Anthony Liguoric227f092009-10-01 16:12:16 -05003914void stl_phys(target_phys_addr_t addr, uint32_t val)
bellard8df1cd02005-01-28 22:37:22 +00003915{
3916 int io_index;
3917 uint8_t *ptr;
3918 unsigned long pd;
3919 PhysPageDesc *p;
3920
3921 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3922 if (!p) {
3923 pd = IO_MEM_UNASSIGNED;
3924 } else {
3925 pd = p->phys_offset;
3926 }
ths3b46e622007-09-17 08:09:54 +00003927
bellard3a7d9292005-08-21 09:26:42 +00003928 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
bellard8df1cd02005-01-28 22:37:22 +00003929 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
pbrook8da3ff12008-12-01 18:59:50 +00003930 if (p)
3931 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
bellard8df1cd02005-01-28 22:37:22 +00003932 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3933 } else {
3934 unsigned long addr1;
3935 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3936 /* RAM case */
pbrook5579c7f2009-04-11 14:47:08 +00003937 ptr = qemu_get_ram_ptr(addr1);
bellard8df1cd02005-01-28 22:37:22 +00003938 stl_p(ptr, val);
bellard3a7d9292005-08-21 09:26:42 +00003939 if (!cpu_physical_memory_is_dirty(addr1)) {
3940 /* invalidate code */
3941 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
3942 /* set dirty bit */
Yoshiaki Tamuraf7c11b52010-03-23 16:39:53 +09003943 cpu_physical_memory_set_dirty_flags(addr1,
3944 (0xff & ~CODE_DIRTY_FLAG));
bellard3a7d9292005-08-21 09:26:42 +00003945 }
bellard8df1cd02005-01-28 22:37:22 +00003946 }
3947}
3948
bellardaab33092005-10-30 20:48:42 +00003949/* XXX: optimize */
Anthony Liguoric227f092009-10-01 16:12:16 -05003950void stb_phys(target_phys_addr_t addr, uint32_t val)
bellardaab33092005-10-30 20:48:42 +00003951{
3952 uint8_t v = val;
3953 cpu_physical_memory_write(addr, &v, 1);
3954}
3955
Michael S. Tsirkin733f0b02010-04-06 14:18:19 +03003956/* warning: addr must be aligned */
Anthony Liguoric227f092009-10-01 16:12:16 -05003957void stw_phys(target_phys_addr_t addr, uint32_t val)
bellardaab33092005-10-30 20:48:42 +00003958{
Michael S. Tsirkin733f0b02010-04-06 14:18:19 +03003959 int io_index;
3960 uint8_t *ptr;
3961 unsigned long pd;
3962 PhysPageDesc *p;
3963
3964 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3965 if (!p) {
3966 pd = IO_MEM_UNASSIGNED;
3967 } else {
3968 pd = p->phys_offset;
3969 }
3970
3971 if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
3972 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
3973 if (p)
3974 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3975 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
3976 } else {
3977 unsigned long addr1;
3978 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3979 /* RAM case */
3980 ptr = qemu_get_ram_ptr(addr1);
3981 stw_p(ptr, val);
3982 if (!cpu_physical_memory_is_dirty(addr1)) {
3983 /* invalidate code */
3984 tb_invalidate_phys_page_range(addr1, addr1 + 2, 0);
3985 /* set dirty bit */
3986 cpu_physical_memory_set_dirty_flags(addr1,
3987 (0xff & ~CODE_DIRTY_FLAG));
3988 }
3989 }
bellardaab33092005-10-30 20:48:42 +00003990}
3991
3992/* XXX: optimize */
Anthony Liguoric227f092009-10-01 16:12:16 -05003993void stq_phys(target_phys_addr_t addr, uint64_t val)
bellardaab33092005-10-30 20:48:42 +00003994{
3995 val = tswap64(val);
3996 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3997}
3998
aliguori5e2972f2009-03-28 17:51:36 +00003999/* virtual memory access for debug (includes writing to ROM) */
ths5fafdf22007-09-16 21:08:06 +00004000int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
bellardb448f2f2004-02-25 23:24:04 +00004001 uint8_t *buf, int len, int is_write)
bellard13eb76e2004-01-24 15:23:36 +00004002{
4003 int l;
Anthony Liguoric227f092009-10-01 16:12:16 -05004004 target_phys_addr_t phys_addr;
j_mayer9b3c35e2007-04-07 11:21:28 +00004005 target_ulong page;
bellard13eb76e2004-01-24 15:23:36 +00004006
4007 while (len > 0) {
4008 page = addr & TARGET_PAGE_MASK;
4009 phys_addr = cpu_get_phys_page_debug(env, page);
4010 /* if no physical page mapped, return an error */
4011 if (phys_addr == -1)
4012 return -1;
4013 l = (page + TARGET_PAGE_SIZE) - addr;
4014 if (l > len)
4015 l = len;
aliguori5e2972f2009-03-28 17:51:36 +00004016 phys_addr += (addr & ~TARGET_PAGE_MASK);
aliguori5e2972f2009-03-28 17:51:36 +00004017 if (is_write)
4018 cpu_physical_memory_write_rom(phys_addr, buf, l);
4019 else
aliguori5e2972f2009-03-28 17:51:36 +00004020 cpu_physical_memory_rw(phys_addr, buf, l, is_write);
bellard13eb76e2004-01-24 15:23:36 +00004021 len -= l;
4022 buf += l;
4023 addr += l;
4024 }
4025 return 0;
4026}
Paul Brooka68fe892010-03-01 00:08:59 +00004027#endif
bellard13eb76e2004-01-24 15:23:36 +00004028
pbrook2e70f6e2008-06-29 01:03:05 +00004029/* in deterministic execution mode, instructions doing device I/Os
4030 must be at the end of the TB */
4031void cpu_io_recompile(CPUState *env, void *retaddr)
4032{
4033 TranslationBlock *tb;
4034 uint32_t n, cflags;
4035 target_ulong pc, cs_base;
4036 uint64_t flags;
4037
4038 tb = tb_find_pc((unsigned long)retaddr);
4039 if (!tb) {
4040 cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
4041 retaddr);
4042 }
4043 n = env->icount_decr.u16.low + tb->icount;
4044 cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
4045 /* Calculate how many instructions had been executed before the fault
thsbf20dc02008-06-30 17:22:19 +00004046 occurred. */
pbrook2e70f6e2008-06-29 01:03:05 +00004047 n = n - env->icount_decr.u16.low;
4048 /* Generate a new TB ending on the I/O insn. */
4049 n++;
4050 /* On MIPS and SH, delay slot instructions can only be restarted if
4051 they were already the first instruction in the TB. If this is not
thsbf20dc02008-06-30 17:22:19 +00004052 the first instruction in a TB then re-execute the preceding
pbrook2e70f6e2008-06-29 01:03:05 +00004053 branch. */
4054#if defined(TARGET_MIPS)
4055 if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
4056 env->active_tc.PC -= 4;
4057 env->icount_decr.u16.low++;
4058 env->hflags &= ~MIPS_HFLAG_BMASK;
4059 }
4060#elif defined(TARGET_SH4)
4061 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
4062 && n > 1) {
4063 env->pc -= 2;
4064 env->icount_decr.u16.low++;
4065 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
4066 }
4067#endif
4068 /* This should never happen. */
4069 if (n > CF_COUNT_MASK)
4070 cpu_abort(env, "TB too big during recompile");
4071
4072 cflags = n | CF_LAST_IO;
4073 pc = tb->pc;
4074 cs_base = tb->cs_base;
4075 flags = tb->flags;
4076 tb_phys_invalidate(tb, -1);
4077 /* FIXME: In theory this could raise an exception. In practice
4078 we have already translated the block once so it's probably ok. */
4079 tb_gen_code(env, pc, cs_base, flags, cflags);
thsbf20dc02008-06-30 17:22:19 +00004080 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
pbrook2e70f6e2008-06-29 01:03:05 +00004081 the first in the TB) then we end up generating a whole new TB and
4082 repeating the fault, which is horribly inefficient.
4083 Better would be to execute just this insn uncached, or generate a
4084 second new TB. */
4085 cpu_resume_from_signal(env, NULL);
4086}
4087
Paul Brookb3755a92010-03-12 16:54:58 +00004088#if !defined(CONFIG_USER_ONLY)
4089
bellarde3db7222005-01-26 22:00:47 +00004090void dump_exec_info(FILE *f,
4091 int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4092{
4093 int i, target_code_size, max_target_code_size;
4094 int direct_jmp_count, direct_jmp2_count, cross_page;
4095 TranslationBlock *tb;
ths3b46e622007-09-17 08:09:54 +00004096
bellarde3db7222005-01-26 22:00:47 +00004097 target_code_size = 0;
4098 max_target_code_size = 0;
4099 cross_page = 0;
4100 direct_jmp_count = 0;
4101 direct_jmp2_count = 0;
4102 for(i = 0; i < nb_tbs; i++) {
4103 tb = &tbs[i];
4104 target_code_size += tb->size;
4105 if (tb->size > max_target_code_size)
4106 max_target_code_size = tb->size;
4107 if (tb->page_addr[1] != -1)
4108 cross_page++;
4109 if (tb->tb_next_offset[0] != 0xffff) {
4110 direct_jmp_count++;
4111 if (tb->tb_next_offset[1] != 0xffff) {
4112 direct_jmp2_count++;
4113 }
4114 }
4115 }
4116 /* XXX: avoid using doubles ? */
bellard57fec1f2008-02-01 10:50:11 +00004117 cpu_fprintf(f, "Translation buffer state:\n");
bellard26a5f132008-05-28 12:30:31 +00004118 cpu_fprintf(f, "gen code size %ld/%ld\n",
4119 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
4120 cpu_fprintf(f, "TB count %d/%d\n",
4121 nb_tbs, code_gen_max_blocks);
ths5fafdf22007-09-16 21:08:06 +00004122 cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
bellarde3db7222005-01-26 22:00:47 +00004123 nb_tbs ? target_code_size / nb_tbs : 0,
4124 max_target_code_size);
ths5fafdf22007-09-16 21:08:06 +00004125 cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
bellarde3db7222005-01-26 22:00:47 +00004126 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
4127 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
ths5fafdf22007-09-16 21:08:06 +00004128 cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
4129 cross_page,
bellarde3db7222005-01-26 22:00:47 +00004130 nb_tbs ? (cross_page * 100) / nb_tbs : 0);
4131 cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
ths5fafdf22007-09-16 21:08:06 +00004132 direct_jmp_count,
bellarde3db7222005-01-26 22:00:47 +00004133 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
4134 direct_jmp2_count,
4135 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
bellard57fec1f2008-02-01 10:50:11 +00004136 cpu_fprintf(f, "\nStatistics:\n");
bellarde3db7222005-01-26 22:00:47 +00004137 cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
4138 cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
4139 cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
bellardb67d9a52008-05-23 09:57:34 +00004140 tcg_dump_info(f, cpu_fprintf);
bellarde3db7222005-01-26 22:00:47 +00004141}
4142
bellard61382a52003-10-27 21:22:23 +00004143#define MMUSUFFIX _cmmu
4144#define GETPC() NULL
4145#define env cpu_single_env
bellardb769d8f2004-10-03 15:07:13 +00004146#define SOFTMMU_CODE_ACCESS
bellard61382a52003-10-27 21:22:23 +00004147
4148#define SHIFT 0
4149#include "softmmu_template.h"
4150
4151#define SHIFT 1
4152#include "softmmu_template.h"
4153
4154#define SHIFT 2
4155#include "softmmu_template.h"
4156
4157#define SHIFT 3
4158#include "softmmu_template.h"
4159
4160#undef env
4161
4162#endif