bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 2 | * virtual page mapping and translated block handling |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 18 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 20 | #ifdef _WIN32 |
| 21 | #include <windows.h> |
| 22 | #else |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 23 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 24 | #include <sys/mman.h> |
| 25 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 26 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 27 | #include "qemu-common.h" |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 28 | #include "cpu.h" |
| 29 | #include "exec-all.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 30 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 31 | #include "hw/hw.h" |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 32 | #include "hw/qdev.h" |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 33 | #include "osdep.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 34 | #include "kvm.h" |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 35 | #include "hw/xen.h" |
Blue Swirl | 29e922b | 2010-03-29 19:24:00 +0000 | [diff] [blame] | 36 | #include "qemu-timer.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 37 | #if defined(CONFIG_USER_ONLY) |
| 38 | #include <qemu.h> |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 39 | #include <signal.h> |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 40 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 41 | #include <sys/param.h> |
| 42 | #if __FreeBSD_version >= 700104 |
| 43 | #define HAVE_KINFO_GETVMMAP |
| 44 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ |
| 45 | #include <sys/time.h> |
| 46 | #include <sys/proc.h> |
| 47 | #include <machine/profile.h> |
| 48 | #define _KERNEL |
| 49 | #include <sys/user.h> |
| 50 | #undef _KERNEL |
| 51 | #undef sigqueue |
| 52 | #include <libutil.h> |
| 53 | #endif |
| 54 | #endif |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 55 | #else /* !CONFIG_USER_ONLY */ |
| 56 | #include "xen-mapcache.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 57 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 58 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 59 | //#define DEBUG_TB_INVALIDATE |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 60 | //#define DEBUG_FLUSH |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 61 | //#define DEBUG_TLB |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 62 | //#define DEBUG_UNASSIGNED |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 63 | |
| 64 | /* make various TB consistency checks */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 65 | //#define DEBUG_TB_CHECK |
| 66 | //#define DEBUG_TLB_CHECK |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 67 | |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 68 | //#define DEBUG_IOPORT |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 69 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 70 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 71 | #if !defined(CONFIG_USER_ONLY) |
| 72 | /* TB consistency checks only implemented for usermode emulation. */ |
| 73 | #undef DEBUG_TB_CHECK |
| 74 | #endif |
| 75 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 76 | #define SMC_BITMAP_USE_THRESHOLD 10 |
| 77 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 78 | static TranslationBlock *tbs; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 79 | static int code_gen_max_blocks; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 80 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 81 | static int nb_tbs; |
bellard | eb51d10 | 2003-05-14 21:51:13 +0000 | [diff] [blame] | 82 | /* any access to the tbs or the page table must use this lock */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 83 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 84 | |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 85 | #if defined(__arm__) || defined(__sparc_v9__) |
| 86 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 |
| 87 | have limited branch ranges (possibly also PPC) so place it in a |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 88 | section close to code segment. */ |
| 89 | #define code_gen_section \ |
| 90 | __attribute__((__section__(".gen_code"))) \ |
| 91 | __attribute__((aligned (32))) |
Stefan Weil | f8e2af1 | 2009-06-18 23:04:48 +0200 | [diff] [blame] | 92 | #elif defined(_WIN32) |
| 93 | /* Maximum alignment for Win32 is 16. */ |
| 94 | #define code_gen_section \ |
| 95 | __attribute__((aligned (16))) |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 96 | #else |
| 97 | #define code_gen_section \ |
| 98 | __attribute__((aligned (32))) |
| 99 | #endif |
| 100 | |
| 101 | uint8_t code_gen_prologue[1024] code_gen_section; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 102 | static uint8_t *code_gen_buffer; |
| 103 | static unsigned long code_gen_buffer_size; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 104 | /* threshold to flush the translated code buffer */ |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 105 | static unsigned long code_gen_buffer_max_size; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 106 | static uint8_t *code_gen_ptr; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 107 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 108 | #if !defined(CONFIG_USER_ONLY) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 109 | int phys_ram_fd; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 110 | static int in_migration; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 111 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 112 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list) }; |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 113 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 114 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 115 | CPUState *first_cpu; |
| 116 | /* current CPU in the current thread. It is only valid inside |
| 117 | cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 118 | CPUState *cpu_single_env; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 119 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 120 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 121 | 2 = Adaptive rate instruction counting. */ |
| 122 | int use_icount = 0; |
| 123 | /* Current instruction counter. While executing translated code this may |
| 124 | include some instructions that have not yet been executed. */ |
| 125 | int64_t qemu_icount; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 126 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 127 | typedef struct PageDesc { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 128 | /* list of TBs intersecting this ram page */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 129 | TranslationBlock *first_tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 130 | /* in order to optimize self modifying code, we count the number |
| 131 | of lookups we do to a given page to use a bitmap */ |
| 132 | unsigned int code_write_count; |
| 133 | uint8_t *code_bitmap; |
| 134 | #if defined(CONFIG_USER_ONLY) |
| 135 | unsigned long flags; |
| 136 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 137 | } PageDesc; |
| 138 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 139 | /* In system mode we want L1_MAP to be based on ram offsets, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 140 | while in user mode we want it to be based on virtual addresses. */ |
| 141 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 142 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
| 143 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS |
| 144 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 145 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 146 | #endif |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 147 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 148 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 149 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 150 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 151 | /* Size of the L2 (and L3, etc) page tables. */ |
| 152 | #define L2_BITS 10 |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 153 | #define L2_SIZE (1 << L2_BITS) |
| 154 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 155 | /* The bits remaining after N lower levels of page tables. */ |
| 156 | #define P_L1_BITS_REM \ |
| 157 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 158 | #define V_L1_BITS_REM \ |
| 159 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 160 | |
| 161 | /* Size of the L1 page table. Avoid silly small sizes. */ |
| 162 | #if P_L1_BITS_REM < 4 |
| 163 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) |
| 164 | #else |
| 165 | #define P_L1_BITS P_L1_BITS_REM |
| 166 | #endif |
| 167 | |
| 168 | #if V_L1_BITS_REM < 4 |
| 169 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) |
| 170 | #else |
| 171 | #define V_L1_BITS V_L1_BITS_REM |
| 172 | #endif |
| 173 | |
| 174 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) |
| 175 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) |
| 176 | |
| 177 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) |
| 178 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) |
| 179 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 180 | unsigned long qemu_real_host_page_size; |
| 181 | unsigned long qemu_host_page_bits; |
| 182 | unsigned long qemu_host_page_size; |
| 183 | unsigned long qemu_host_page_mask; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 184 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 185 | /* This is a multi-level map on the virtual address space. |
| 186 | The bottom level has pointers to PageDesc. */ |
| 187 | static void *l1_map[V_L1_SIZE]; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 188 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 189 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 190 | typedef struct PhysPageDesc { |
| 191 | /* offset in host memory of the page + io_index in the low bits */ |
| 192 | ram_addr_t phys_offset; |
| 193 | ram_addr_t region_offset; |
| 194 | } PhysPageDesc; |
| 195 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 196 | /* This is a multi-level map on the physical address space. |
| 197 | The bottom level has pointers to PhysPageDesc. */ |
| 198 | static void *l1_phys_map[P_L1_SIZE]; |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 199 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 200 | static void io_mem_init(void); |
| 201 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 202 | /* io memory support */ |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 203 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 204 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 205 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
blueswir1 | 511d2b1 | 2009-03-07 15:32:56 +0000 | [diff] [blame] | 206 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 207 | static int io_mem_watch; |
| 208 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 209 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 210 | /* log support */ |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 211 | #ifdef WIN32 |
| 212 | static const char *logfilename = "qemu.log"; |
| 213 | #else |
blueswir1 | d9b630f | 2008-10-05 09:57:08 +0000 | [diff] [blame] | 214 | static const char *logfilename = "/tmp/qemu.log"; |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 215 | #endif |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 216 | FILE *logfile; |
| 217 | int loglevel; |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 218 | static int log_append = 0; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 219 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 220 | /* statistics */ |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 221 | #if !defined(CONFIG_USER_ONLY) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 222 | static int tlb_flush_count; |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 223 | #endif |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 224 | static int tb_flush_count; |
| 225 | static int tb_phys_invalidate_count; |
| 226 | |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 227 | #ifdef _WIN32 |
| 228 | static void map_exec(void *addr, long size) |
| 229 | { |
| 230 | DWORD old_protect; |
| 231 | VirtualProtect(addr, size, |
| 232 | PAGE_EXECUTE_READWRITE, &old_protect); |
| 233 | |
| 234 | } |
| 235 | #else |
| 236 | static void map_exec(void *addr, long size) |
| 237 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 238 | unsigned long start, end, page_size; |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 239 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 240 | page_size = getpagesize(); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 241 | start = (unsigned long)addr; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 242 | start &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 243 | |
| 244 | end = (unsigned long)addr + size; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 245 | end += page_size - 1; |
| 246 | end &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 247 | |
| 248 | mprotect((void *)start, end - start, |
| 249 | PROT_READ | PROT_WRITE | PROT_EXEC); |
| 250 | } |
| 251 | #endif |
| 252 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 253 | static void page_init(void) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 254 | { |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 255 | /* NOTE: we can always suppose that qemu_host_page_size >= |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 256 | TARGET_PAGE_SIZE */ |
aliguori | c2b48b6 | 2008-11-11 22:06:42 +0000 | [diff] [blame] | 257 | #ifdef _WIN32 |
| 258 | { |
| 259 | SYSTEM_INFO system_info; |
| 260 | |
| 261 | GetSystemInfo(&system_info); |
| 262 | qemu_real_host_page_size = system_info.dwPageSize; |
| 263 | } |
| 264 | #else |
| 265 | qemu_real_host_page_size = getpagesize(); |
| 266 | #endif |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 267 | if (qemu_host_page_size == 0) |
| 268 | qemu_host_page_size = qemu_real_host_page_size; |
| 269 | if (qemu_host_page_size < TARGET_PAGE_SIZE) |
| 270 | qemu_host_page_size = TARGET_PAGE_SIZE; |
| 271 | qemu_host_page_bits = 0; |
| 272 | while ((1 << qemu_host_page_bits) < qemu_host_page_size) |
| 273 | qemu_host_page_bits++; |
| 274 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 275 | |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 276 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 277 | { |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 278 | #ifdef HAVE_KINFO_GETVMMAP |
| 279 | struct kinfo_vmentry *freep; |
| 280 | int i, cnt; |
| 281 | |
| 282 | freep = kinfo_getvmmap(getpid(), &cnt); |
| 283 | if (freep) { |
| 284 | mmap_lock(); |
| 285 | for (i = 0; i < cnt; i++) { |
| 286 | unsigned long startaddr, endaddr; |
| 287 | |
| 288 | startaddr = freep[i].kve_start; |
| 289 | endaddr = freep[i].kve_end; |
| 290 | if (h2g_valid(startaddr)) { |
| 291 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 292 | |
| 293 | if (h2g_valid(endaddr)) { |
| 294 | endaddr = h2g(endaddr); |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 295 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 296 | } else { |
| 297 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS |
| 298 | endaddr = ~0ul; |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 299 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 300 | #endif |
| 301 | } |
| 302 | } |
| 303 | } |
| 304 | free(freep); |
| 305 | mmap_unlock(); |
| 306 | } |
| 307 | #else |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 308 | FILE *f; |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 309 | |
pbrook | 0776590 | 2008-05-31 16:33:53 +0000 | [diff] [blame] | 310 | last_brk = (unsigned long)sbrk(0); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 311 | |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 312 | f = fopen("/compat/linux/proc/self/maps", "r"); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 313 | if (f) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 314 | mmap_lock(); |
| 315 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 316 | do { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 317 | unsigned long startaddr, endaddr; |
| 318 | int n; |
| 319 | |
| 320 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); |
| 321 | |
| 322 | if (n == 2 && h2g_valid(startaddr)) { |
| 323 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 324 | |
| 325 | if (h2g_valid(endaddr)) { |
| 326 | endaddr = h2g(endaddr); |
| 327 | } else { |
| 328 | endaddr = ~0ul; |
| 329 | } |
| 330 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 331 | } |
| 332 | } while (!feof(f)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 333 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 334 | fclose(f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 335 | mmap_unlock(); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 336 | } |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 337 | #endif |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 338 | } |
| 339 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 340 | } |
| 341 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 342 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 343 | { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 344 | PageDesc *pd; |
| 345 | void **lp; |
| 346 | int i; |
| 347 | |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 348 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 349 | /* We can't use qemu_malloc because it may recurse into a locked mutex. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 350 | # define ALLOC(P, SIZE) \ |
| 351 | do { \ |
| 352 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ |
| 353 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 354 | } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 355 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 356 | # define ALLOC(P, SIZE) \ |
| 357 | do { P = qemu_mallocz(SIZE); } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 358 | #endif |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 359 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 360 | /* Level 1. Always allocated. */ |
| 361 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); |
| 362 | |
| 363 | /* Level 2..N-1. */ |
| 364 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 365 | void **p = *lp; |
| 366 | |
| 367 | if (p == NULL) { |
| 368 | if (!alloc) { |
| 369 | return NULL; |
| 370 | } |
| 371 | ALLOC(p, sizeof(void *) * L2_SIZE); |
| 372 | *lp = p; |
| 373 | } |
| 374 | |
| 375 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 376 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 377 | |
| 378 | pd = *lp; |
| 379 | if (pd == NULL) { |
| 380 | if (!alloc) { |
| 381 | return NULL; |
| 382 | } |
| 383 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); |
| 384 | *lp = pd; |
| 385 | } |
| 386 | |
| 387 | #undef ALLOC |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 388 | |
| 389 | return pd + (index & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 390 | } |
| 391 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 392 | static inline PageDesc *page_find(tb_page_addr_t index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 393 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 394 | return page_find_alloc(index, 0); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 395 | } |
| 396 | |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 397 | #if !defined(CONFIG_USER_ONLY) |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 398 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 399 | { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 400 | PhysPageDesc *pd; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 401 | void **lp; |
| 402 | int i; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 403 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 404 | /* Level 1. Always allocated. */ |
| 405 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 406 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 407 | /* Level 2..N-1. */ |
| 408 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 409 | void **p = *lp; |
| 410 | if (p == NULL) { |
| 411 | if (!alloc) { |
| 412 | return NULL; |
| 413 | } |
| 414 | *lp = p = qemu_mallocz(sizeof(void *) * L2_SIZE); |
| 415 | } |
| 416 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 417 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 418 | |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 419 | pd = *lp; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 420 | if (pd == NULL) { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 421 | int i; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 422 | |
| 423 | if (!alloc) { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 424 | return NULL; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 425 | } |
| 426 | |
| 427 | *lp = pd = qemu_malloc(sizeof(PhysPageDesc) * L2_SIZE); |
| 428 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 429 | for (i = 0; i < L2_SIZE; i++) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 430 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
| 431 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 432 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 433 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 434 | |
| 435 | return pd + (index & (L2_SIZE - 1)); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 436 | } |
| 437 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 438 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 439 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 440 | return phys_page_find_alloc(index, 0); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 441 | } |
| 442 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 443 | static void tlb_protect_code(ram_addr_t ram_addr); |
| 444 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 445 | target_ulong vaddr); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 446 | #define mmap_lock() do { } while(0) |
| 447 | #define mmap_unlock() do { } while(0) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 448 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 449 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 450 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
| 451 | |
| 452 | #if defined(CONFIG_USER_ONLY) |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 453 | /* Currently it is not recommended to allocate big chunks of data in |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 454 | user mode. It will change when a dedicated libc will be used */ |
| 455 | #define USE_STATIC_CODE_GEN_BUFFER |
| 456 | #endif |
| 457 | |
| 458 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
Aurelien Jarno | ebf50fb | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 459 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
| 460 | __attribute__((aligned (CODE_GEN_ALIGN))); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 461 | #endif |
| 462 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 463 | static void code_gen_alloc(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 464 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 465 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 466 | code_gen_buffer = static_code_gen_buffer; |
| 467 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 468 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 469 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 470 | code_gen_buffer_size = tb_size; |
| 471 | if (code_gen_buffer_size == 0) { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 472 | #if defined(CONFIG_USER_ONLY) |
| 473 | /* in user mode, phys_ram_size is not meaningful */ |
| 474 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 475 | #else |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 476 | /* XXX: needs adjustments */ |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 477 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 478 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 479 | } |
| 480 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) |
| 481 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; |
| 482 | /* The code gen buffer location may have constraints depending on |
| 483 | the host cpu and OS */ |
| 484 | #if defined(__linux__) |
| 485 | { |
| 486 | int flags; |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 487 | void *start = NULL; |
| 488 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 489 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 490 | #if defined(__x86_64__) |
| 491 | flags |= MAP_32BIT; |
| 492 | /* Cannot map more than that */ |
| 493 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 494 | code_gen_buffer_size = (800 * 1024 * 1024); |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 495 | #elif defined(__sparc_v9__) |
| 496 | // Map the buffer below 2G, so we can use direct calls and branches |
| 497 | flags |= MAP_FIXED; |
| 498 | start = (void *) 0x60000000UL; |
| 499 | if (code_gen_buffer_size > (512 * 1024 * 1024)) |
| 500 | code_gen_buffer_size = (512 * 1024 * 1024); |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 501 | #elif defined(__arm__) |
balrog | 63d4124 | 2008-12-01 02:19:41 +0000 | [diff] [blame] | 502 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 503 | flags |= MAP_FIXED; |
| 504 | start = (void *) 0x01000000UL; |
| 505 | if (code_gen_buffer_size > 16 * 1024 * 1024) |
| 506 | code_gen_buffer_size = 16 * 1024 * 1024; |
Richard Henderson | eba0b89 | 2010-06-04 12:14:14 -0700 | [diff] [blame] | 507 | #elif defined(__s390x__) |
| 508 | /* Map the buffer so that we can use direct calls and branches. */ |
| 509 | /* We have a +- 4GB range on the branches; leave some slop. */ |
| 510 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { |
| 511 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; |
| 512 | } |
| 513 | start = (void *)0x90000000UL; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 514 | #endif |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 515 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
| 516 | PROT_WRITE | PROT_READ | PROT_EXEC, |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 517 | flags, -1, 0); |
| 518 | if (code_gen_buffer == MAP_FAILED) { |
| 519 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 520 | exit(1); |
| 521 | } |
| 522 | } |
Brad | cbb608a | 2010-12-20 21:25:40 -0500 | [diff] [blame] | 523 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
| 524 | || defined(__DragonFly__) || defined(__OpenBSD__) |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 525 | { |
| 526 | int flags; |
| 527 | void *addr = NULL; |
| 528 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 529 | #if defined(__x86_64__) |
| 530 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume |
| 531 | * 0x40000000 is free */ |
| 532 | flags |= MAP_FIXED; |
| 533 | addr = (void *)0x40000000; |
| 534 | /* Cannot map more than that */ |
| 535 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 536 | code_gen_buffer_size = (800 * 1024 * 1024); |
Blue Swirl | 4cd31ad | 2011-01-16 08:32:27 +0000 | [diff] [blame] | 537 | #elif defined(__sparc_v9__) |
| 538 | // Map the buffer below 2G, so we can use direct calls and branches |
| 539 | flags |= MAP_FIXED; |
| 540 | addr = (void *) 0x60000000UL; |
| 541 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { |
| 542 | code_gen_buffer_size = (512 * 1024 * 1024); |
| 543 | } |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 544 | #endif |
| 545 | code_gen_buffer = mmap(addr, code_gen_buffer_size, |
| 546 | PROT_WRITE | PROT_READ | PROT_EXEC, |
| 547 | flags, -1, 0); |
| 548 | if (code_gen_buffer == MAP_FAILED) { |
| 549 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 550 | exit(1); |
| 551 | } |
| 552 | } |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 553 | #else |
| 554 | code_gen_buffer = qemu_malloc(code_gen_buffer_size); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 555 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 556 | #endif |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 557 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 558 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
| 559 | code_gen_buffer_max_size = code_gen_buffer_size - |
Aurelien Jarno | 239fda3 | 2010-06-03 19:29:31 +0200 | [diff] [blame] | 560 | (TCG_MAX_OP_SIZE * OPC_MAX_SIZE); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 561 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
| 562 | tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
| 563 | } |
| 564 | |
| 565 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
| 566 | (in bytes) allocated to the translation buffer. Zero means default |
| 567 | size. */ |
| 568 | void cpu_exec_init_all(unsigned long tb_size) |
| 569 | { |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 570 | cpu_gen_init(); |
| 571 | code_gen_alloc(tb_size); |
| 572 | code_gen_ptr = code_gen_buffer; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 573 | page_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 574 | #if !defined(CONFIG_USER_ONLY) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 575 | io_mem_init(); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 576 | #endif |
Richard Henderson | 9002ec7 | 2010-05-06 08:50:41 -0700 | [diff] [blame] | 577 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
| 578 | /* There's no guest base to take into account, so go ahead and |
| 579 | initialize the prologue now. */ |
| 580 | tcg_prologue_init(&tcg_ctx); |
| 581 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 582 | } |
| 583 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 584 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
| 585 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 586 | static int cpu_common_post_load(void *opaque, int version_id) |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 587 | { |
| 588 | CPUState *env = opaque; |
| 589 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 590 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
| 591 | version_id is increased. */ |
| 592 | env->interrupt_request &= ~0x01; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 593 | tlb_flush(env, 1); |
| 594 | |
| 595 | return 0; |
| 596 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 597 | |
| 598 | static const VMStateDescription vmstate_cpu_common = { |
| 599 | .name = "cpu_common", |
| 600 | .version_id = 1, |
| 601 | .minimum_version_id = 1, |
| 602 | .minimum_version_id_old = 1, |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 603 | .post_load = cpu_common_post_load, |
| 604 | .fields = (VMStateField []) { |
| 605 | VMSTATE_UINT32(halted, CPUState), |
| 606 | VMSTATE_UINT32(interrupt_request, CPUState), |
| 607 | VMSTATE_END_OF_LIST() |
| 608 | } |
| 609 | }; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 610 | #endif |
| 611 | |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 612 | CPUState *qemu_get_cpu(int cpu) |
| 613 | { |
| 614 | CPUState *env = first_cpu; |
| 615 | |
| 616 | while (env) { |
| 617 | if (env->cpu_index == cpu) |
| 618 | break; |
| 619 | env = env->next_cpu; |
| 620 | } |
| 621 | |
| 622 | return env; |
| 623 | } |
| 624 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 625 | void cpu_exec_init(CPUState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 626 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 627 | CPUState **penv; |
| 628 | int cpu_index; |
| 629 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 630 | #if defined(CONFIG_USER_ONLY) |
| 631 | cpu_list_lock(); |
| 632 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 633 | env->next_cpu = NULL; |
| 634 | penv = &first_cpu; |
| 635 | cpu_index = 0; |
| 636 | while (*penv != NULL) { |
Nathan Froyd | 1e9fa73 | 2009-06-03 11:33:08 -0700 | [diff] [blame] | 637 | penv = &(*penv)->next_cpu; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 638 | cpu_index++; |
| 639 | } |
| 640 | env->cpu_index = cpu_index; |
aliguori | 268a362 | 2009-04-21 22:30:27 +0000 | [diff] [blame] | 641 | env->numa_node = 0; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 642 | QTAILQ_INIT(&env->breakpoints); |
| 643 | QTAILQ_INIT(&env->watchpoints); |
Jan Kiszka | dc7a09c | 2011-03-15 12:26:31 +0100 | [diff] [blame] | 644 | #ifndef CONFIG_USER_ONLY |
| 645 | env->thread_id = qemu_get_thread_id(); |
| 646 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 647 | *penv = env; |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 648 | #if defined(CONFIG_USER_ONLY) |
| 649 | cpu_list_unlock(); |
| 650 | #endif |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 651 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
Alex Williamson | 0be71e3 | 2010-06-25 11:09:07 -0600 | [diff] [blame] | 652 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
| 653 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 654 | cpu_save, cpu_load, env); |
| 655 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 656 | } |
| 657 | |
Tristan Gingold | d1a1eb7 | 2011-02-10 10:04:57 +0100 | [diff] [blame] | 658 | /* Allocate a new translation block. Flush the translation buffer if |
| 659 | too many translation blocks or too much generated code. */ |
| 660 | static TranslationBlock *tb_alloc(target_ulong pc) |
| 661 | { |
| 662 | TranslationBlock *tb; |
| 663 | |
| 664 | if (nb_tbs >= code_gen_max_blocks || |
| 665 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) |
| 666 | return NULL; |
| 667 | tb = &tbs[nb_tbs++]; |
| 668 | tb->pc = pc; |
| 669 | tb->cflags = 0; |
| 670 | return tb; |
| 671 | } |
| 672 | |
| 673 | void tb_free(TranslationBlock *tb) |
| 674 | { |
| 675 | /* In practice this is mostly used for single use temporary TB |
| 676 | Ignore the hard cases and just back up if this TB happens to |
| 677 | be the last one generated. */ |
| 678 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { |
| 679 | code_gen_ptr = tb->tc_ptr; |
| 680 | nb_tbs--; |
| 681 | } |
| 682 | } |
| 683 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 684 | static inline void invalidate_page_bitmap(PageDesc *p) |
| 685 | { |
| 686 | if (p->code_bitmap) { |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 687 | qemu_free(p->code_bitmap); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 688 | p->code_bitmap = NULL; |
| 689 | } |
| 690 | p->code_write_count = 0; |
| 691 | } |
| 692 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 693 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
| 694 | |
| 695 | static void page_flush_tb_1 (int level, void **lp) |
| 696 | { |
| 697 | int i; |
| 698 | |
| 699 | if (*lp == NULL) { |
| 700 | return; |
| 701 | } |
| 702 | if (level == 0) { |
| 703 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 704 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 705 | pd[i].first_tb = NULL; |
| 706 | invalidate_page_bitmap(pd + i); |
| 707 | } |
| 708 | } else { |
| 709 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 710 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 711 | page_flush_tb_1 (level - 1, pp + i); |
| 712 | } |
| 713 | } |
| 714 | } |
| 715 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 716 | static void page_flush_tb(void) |
| 717 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 718 | int i; |
| 719 | for (i = 0; i < V_L1_SIZE; i++) { |
| 720 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 721 | } |
| 722 | } |
| 723 | |
| 724 | /* flush all the translation blocks */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 725 | /* XXX: tb_flush is currently not thread safe */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 726 | void tb_flush(CPUState *env1) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 727 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 728 | CPUState *env; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 729 | #if defined(DEBUG_FLUSH) |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 730 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
| 731 | (unsigned long)(code_gen_ptr - code_gen_buffer), |
| 732 | nb_tbs, nb_tbs > 0 ? |
| 733 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 734 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 735 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 736 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
| 737 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 738 | nb_tbs = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 739 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 740 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 741 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
| 742 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 743 | |
bellard | 8a8a608 | 2004-10-03 13:36:49 +0000 | [diff] [blame] | 744 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 745 | page_flush_tb(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 746 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 747 | code_gen_ptr = code_gen_buffer; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 748 | /* XXX: flush processor icache at this point if cache flush is |
| 749 | expensive */ |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 750 | tb_flush_count++; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | #ifdef DEBUG_TB_CHECK |
| 754 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 755 | static void tb_invalidate_check(target_ulong address) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 756 | { |
| 757 | TranslationBlock *tb; |
| 758 | int i; |
| 759 | address &= TARGET_PAGE_MASK; |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 760 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 761 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 762 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
| 763 | address >= tb->pc + tb->size)) { |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 764 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
| 765 | " PC=%08lx size=%04x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 766 | address, (long)tb->pc, tb->size); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 767 | } |
| 768 | } |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | /* verify that all the pages have correct rights for code */ |
| 773 | static void tb_page_check(void) |
| 774 | { |
| 775 | TranslationBlock *tb; |
| 776 | int i, flags1, flags2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 777 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 778 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 779 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 780 | flags1 = page_get_flags(tb->pc); |
| 781 | flags2 = page_get_flags(tb->pc + tb->size - 1); |
| 782 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { |
| 783 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 784 | (long)tb->pc, tb->size, flags1, flags2); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 785 | } |
| 786 | } |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | #endif |
| 791 | |
| 792 | /* invalidate one TB */ |
| 793 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, |
| 794 | int next_offset) |
| 795 | { |
| 796 | TranslationBlock *tb1; |
| 797 | for(;;) { |
| 798 | tb1 = *ptb; |
| 799 | if (tb1 == tb) { |
| 800 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); |
| 801 | break; |
| 802 | } |
| 803 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); |
| 804 | } |
| 805 | } |
| 806 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 807 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
| 808 | { |
| 809 | TranslationBlock *tb1; |
| 810 | unsigned int n1; |
| 811 | |
| 812 | for(;;) { |
| 813 | tb1 = *ptb; |
| 814 | n1 = (long)tb1 & 3; |
| 815 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 816 | if (tb1 == tb) { |
| 817 | *ptb = tb1->page_next[n1]; |
| 818 | break; |
| 819 | } |
| 820 | ptb = &tb1->page_next[n1]; |
| 821 | } |
| 822 | } |
| 823 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 824 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
| 825 | { |
| 826 | TranslationBlock *tb1, **ptb; |
| 827 | unsigned int n1; |
| 828 | |
| 829 | ptb = &tb->jmp_next[n]; |
| 830 | tb1 = *ptb; |
| 831 | if (tb1) { |
| 832 | /* find tb(n) in circular list */ |
| 833 | for(;;) { |
| 834 | tb1 = *ptb; |
| 835 | n1 = (long)tb1 & 3; |
| 836 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 837 | if (n1 == n && tb1 == tb) |
| 838 | break; |
| 839 | if (n1 == 2) { |
| 840 | ptb = &tb1->jmp_first; |
| 841 | } else { |
| 842 | ptb = &tb1->jmp_next[n1]; |
| 843 | } |
| 844 | } |
| 845 | /* now we can suppress tb(n) from the list */ |
| 846 | *ptb = tb->jmp_next[n]; |
| 847 | |
| 848 | tb->jmp_next[n] = NULL; |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | /* reset the jump entry 'n' of a TB so that it is not chained to |
| 853 | another TB */ |
| 854 | static inline void tb_reset_jump(TranslationBlock *tb, int n) |
| 855 | { |
| 856 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); |
| 857 | } |
| 858 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 859 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 860 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 861 | CPUState *env; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 862 | PageDesc *p; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 863 | unsigned int h, n1; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 864 | tb_page_addr_t phys_pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 865 | TranslationBlock *tb1, *tb2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 866 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 867 | /* remove the TB from the hash list */ |
| 868 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 869 | h = tb_phys_hash_func(phys_pc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 870 | tb_remove(&tb_phys_hash[h], tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 871 | offsetof(TranslationBlock, phys_hash_next)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 872 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 873 | /* remove the TB from the page list */ |
| 874 | if (tb->page_addr[0] != page_addr) { |
| 875 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); |
| 876 | tb_page_remove(&p->first_tb, tb); |
| 877 | invalidate_page_bitmap(p); |
| 878 | } |
| 879 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { |
| 880 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); |
| 881 | tb_page_remove(&p->first_tb, tb); |
| 882 | invalidate_page_bitmap(p); |
| 883 | } |
| 884 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 885 | tb_invalidated_flag = 1; |
| 886 | |
| 887 | /* remove the TB from the hash list */ |
| 888 | h = tb_jmp_cache_hash_func(tb->pc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 889 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 890 | if (env->tb_jmp_cache[h] == tb) |
| 891 | env->tb_jmp_cache[h] = NULL; |
| 892 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 893 | |
| 894 | /* suppress this TB from the two jump lists */ |
| 895 | tb_jmp_remove(tb, 0); |
| 896 | tb_jmp_remove(tb, 1); |
| 897 | |
| 898 | /* suppress any remaining jumps to this TB */ |
| 899 | tb1 = tb->jmp_first; |
| 900 | for(;;) { |
| 901 | n1 = (long)tb1 & 3; |
| 902 | if (n1 == 2) |
| 903 | break; |
| 904 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 905 | tb2 = tb1->jmp_next[n1]; |
| 906 | tb_reset_jump(tb1, n1); |
| 907 | tb1->jmp_next[n1] = NULL; |
| 908 | tb1 = tb2; |
| 909 | } |
| 910 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ |
| 911 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 912 | tb_phys_invalidate_count++; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 913 | } |
| 914 | |
| 915 | static inline void set_bits(uint8_t *tab, int start, int len) |
| 916 | { |
| 917 | int end, mask, end1; |
| 918 | |
| 919 | end = start + len; |
| 920 | tab += start >> 3; |
| 921 | mask = 0xff << (start & 7); |
| 922 | if ((start & ~7) == (end & ~7)) { |
| 923 | if (start < end) { |
| 924 | mask &= ~(0xff << (end & 7)); |
| 925 | *tab |= mask; |
| 926 | } |
| 927 | } else { |
| 928 | *tab++ |= mask; |
| 929 | start = (start + 8) & ~7; |
| 930 | end1 = end & ~7; |
| 931 | while (start < end1) { |
| 932 | *tab++ = 0xff; |
| 933 | start += 8; |
| 934 | } |
| 935 | if (start < end) { |
| 936 | mask = ~(0xff << (end & 7)); |
| 937 | *tab |= mask; |
| 938 | } |
| 939 | } |
| 940 | } |
| 941 | |
| 942 | static void build_page_bitmap(PageDesc *p) |
| 943 | { |
| 944 | int n, tb_start, tb_end; |
| 945 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 946 | |
pbrook | b2a7081 | 2008-06-09 13:57:23 +0000 | [diff] [blame] | 947 | p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 948 | |
| 949 | tb = p->first_tb; |
| 950 | while (tb != NULL) { |
| 951 | n = (long)tb & 3; |
| 952 | tb = (TranslationBlock *)((long)tb & ~3); |
| 953 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 954 | if (n == 0) { |
| 955 | /* NOTE: tb_end may be after the end of the page, but |
| 956 | it is not a problem */ |
| 957 | tb_start = tb->pc & ~TARGET_PAGE_MASK; |
| 958 | tb_end = tb_start + tb->size; |
| 959 | if (tb_end > TARGET_PAGE_SIZE) |
| 960 | tb_end = TARGET_PAGE_SIZE; |
| 961 | } else { |
| 962 | tb_start = 0; |
| 963 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 964 | } |
| 965 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); |
| 966 | tb = tb->page_next[n]; |
| 967 | } |
| 968 | } |
| 969 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 970 | TranslationBlock *tb_gen_code(CPUState *env, |
| 971 | target_ulong pc, target_ulong cs_base, |
| 972 | int flags, int cflags) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 973 | { |
| 974 | TranslationBlock *tb; |
| 975 | uint8_t *tc_ptr; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 976 | tb_page_addr_t phys_pc, phys_page2; |
| 977 | target_ulong virt_page2; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 978 | int code_gen_size; |
| 979 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 980 | phys_pc = get_page_addr_code(env, pc); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 981 | tb = tb_alloc(pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 982 | if (!tb) { |
| 983 | /* flush must be done */ |
| 984 | tb_flush(env); |
| 985 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 986 | tb = tb_alloc(pc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 987 | /* Don't forget to invalidate previous TB info. */ |
| 988 | tb_invalidated_flag = 1; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 989 | } |
| 990 | tc_ptr = code_gen_ptr; |
| 991 | tb->tc_ptr = tc_ptr; |
| 992 | tb->cs_base = cs_base; |
| 993 | tb->flags = flags; |
| 994 | tb->cflags = cflags; |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 995 | cpu_gen_code(env, tb, &code_gen_size); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 996 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 997 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 998 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 999 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1000 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1001 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1002 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1003 | } |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1004 | tb_link_page(tb, phys_pc, phys_page2); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1005 | return tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1006 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1007 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1008 | /* invalidate all TBs which intersect with the target physical page |
| 1009 | starting in range [start;end[. NOTE: start and end must refer to |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1010 | the same physical page. 'is_cpu_write_access' should be true if called |
| 1011 | from a real cpu write access: the virtual CPU will exit the current |
| 1012 | TB if code is modified inside this TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1013 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1014 | int is_cpu_write_access) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1015 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1016 | TranslationBlock *tb, *tb_next, *saved_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1017 | CPUState *env = cpu_single_env; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1018 | tb_page_addr_t tb_start, tb_end; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1019 | PageDesc *p; |
| 1020 | int n; |
| 1021 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1022 | int current_tb_not_found = is_cpu_write_access; |
| 1023 | TranslationBlock *current_tb = NULL; |
| 1024 | int current_tb_modified = 0; |
| 1025 | target_ulong current_pc = 0; |
| 1026 | target_ulong current_cs_base = 0; |
| 1027 | int current_flags = 0; |
| 1028 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1029 | |
| 1030 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1031 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1032 | return; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1033 | if (!p->code_bitmap && |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1034 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
| 1035 | is_cpu_write_access) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1036 | /* build code bitmap */ |
| 1037 | build_page_bitmap(p); |
| 1038 | } |
| 1039 | |
| 1040 | /* we remove all the TBs in the range [start, end[ */ |
| 1041 | /* XXX: see if in some cases it could be faster to invalidate all the code */ |
| 1042 | tb = p->first_tb; |
| 1043 | while (tb != NULL) { |
| 1044 | n = (long)tb & 3; |
| 1045 | tb = (TranslationBlock *)((long)tb & ~3); |
| 1046 | tb_next = tb->page_next[n]; |
| 1047 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 1048 | if (n == 0) { |
| 1049 | /* NOTE: tb_end may be after the end of the page, but |
| 1050 | it is not a problem */ |
| 1051 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 1052 | tb_end = tb_start + tb->size; |
| 1053 | } else { |
| 1054 | tb_start = tb->page_addr[1]; |
| 1055 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 1056 | } |
| 1057 | if (!(tb_end <= start || tb_start >= end)) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1058 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1059 | if (current_tb_not_found) { |
| 1060 | current_tb_not_found = 0; |
| 1061 | current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1062 | if (env->mem_io_pc) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1063 | /* now we have a real cpu fault */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1064 | current_tb = tb_find_pc(env->mem_io_pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1065 | } |
| 1066 | } |
| 1067 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1068 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1069 | /* If we are modifying the current TB, we must stop |
| 1070 | its execution. We could be more precise by checking |
| 1071 | that the modification is after the current PC, but it |
| 1072 | would require a specialized function to partially |
| 1073 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1074 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1075 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1076 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1077 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1078 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1079 | } |
| 1080 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1081 | /* we need to do that to handle the case where a signal |
| 1082 | occurs while doing tb_phys_invalidate() */ |
| 1083 | saved_tb = NULL; |
| 1084 | if (env) { |
| 1085 | saved_tb = env->current_tb; |
| 1086 | env->current_tb = NULL; |
| 1087 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1088 | tb_phys_invalidate(tb, -1); |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1089 | if (env) { |
| 1090 | env->current_tb = saved_tb; |
| 1091 | if (env->interrupt_request && env->current_tb) |
| 1092 | cpu_interrupt(env, env->interrupt_request); |
| 1093 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1094 | } |
| 1095 | tb = tb_next; |
| 1096 | } |
| 1097 | #if !defined(CONFIG_USER_ONLY) |
| 1098 | /* if no code remaining, no need to continue to use slow writes */ |
| 1099 | if (!p->first_tb) { |
| 1100 | invalidate_page_bitmap(p); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1101 | if (is_cpu_write_access) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1102 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1103 | } |
| 1104 | } |
| 1105 | #endif |
| 1106 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1107 | if (current_tb_modified) { |
| 1108 | /* we generate a block containing just the instruction |
| 1109 | modifying the memory. It will ensure that it cannot modify |
| 1110 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1111 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1112 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1113 | cpu_resume_from_signal(env, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1114 | } |
| 1115 | #endif |
| 1116 | } |
| 1117 | |
| 1118 | /* len must be <= 8 and start must be a multiple of len */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1119 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1120 | { |
| 1121 | PageDesc *p; |
| 1122 | int offset, b; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1123 | #if 0 |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 1124 | if (1) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1125 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
| 1126 | cpu_single_env->mem_io_vaddr, len, |
| 1127 | cpu_single_env->eip, |
| 1128 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1129 | } |
| 1130 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1131 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1132 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1133 | return; |
| 1134 | if (p->code_bitmap) { |
| 1135 | offset = start & ~TARGET_PAGE_MASK; |
| 1136 | b = p->code_bitmap[offset >> 3] >> (offset & 7); |
| 1137 | if (b & ((1 << len) - 1)) |
| 1138 | goto do_invalidate; |
| 1139 | } else { |
| 1140 | do_invalidate: |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1141 | tb_invalidate_phys_page_range(start, start + len, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1142 | } |
| 1143 | } |
| 1144 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1145 | #if !defined(CONFIG_SOFTMMU) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1146 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1147 | unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1148 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1149 | TranslationBlock *tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1150 | PageDesc *p; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1151 | int n; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1152 | #ifdef TARGET_HAS_PRECISE_SMC |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1153 | TranslationBlock *current_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1154 | CPUState *env = cpu_single_env; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1155 | int current_tb_modified = 0; |
| 1156 | target_ulong current_pc = 0; |
| 1157 | target_ulong current_cs_base = 0; |
| 1158 | int current_flags = 0; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1159 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1160 | |
| 1161 | addr &= TARGET_PAGE_MASK; |
| 1162 | p = page_find(addr >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1163 | if (!p) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1164 | return; |
| 1165 | tb = p->first_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1166 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1167 | if (tb && pc != 0) { |
| 1168 | current_tb = tb_find_pc(pc); |
| 1169 | } |
| 1170 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1171 | while (tb != NULL) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1172 | n = (long)tb & 3; |
| 1173 | tb = (TranslationBlock *)((long)tb & ~3); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1174 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1175 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1176 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1177 | /* If we are modifying the current TB, we must stop |
| 1178 | its execution. We could be more precise by checking |
| 1179 | that the modification is after the current PC, but it |
| 1180 | would require a specialized function to partially |
| 1181 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1182 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1183 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1184 | cpu_restore_state(current_tb, env, pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1185 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1186 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1187 | } |
| 1188 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1189 | tb_phys_invalidate(tb, addr); |
| 1190 | tb = tb->page_next[n]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1191 | } |
| 1192 | p->first_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1193 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1194 | if (current_tb_modified) { |
| 1195 | /* we generate a block containing just the instruction |
| 1196 | modifying the memory. It will ensure that it cannot modify |
| 1197 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1198 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1199 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1200 | cpu_resume_from_signal(env, puc); |
| 1201 | } |
| 1202 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1203 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1204 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1205 | |
| 1206 | /* add the tb in the target page and protect it if necessary */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1207 | static inline void tb_alloc_page(TranslationBlock *tb, |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1208 | unsigned int n, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1209 | { |
| 1210 | PageDesc *p; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1211 | TranslationBlock *last_first_tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1212 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1213 | tb->page_addr[n] = page_addr; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1214 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1215 | tb->page_next[n] = p->first_tb; |
| 1216 | last_first_tb = p->first_tb; |
| 1217 | p->first_tb = (TranslationBlock *)((long)tb | n); |
| 1218 | invalidate_page_bitmap(p); |
| 1219 | |
bellard | 107db44 | 2004-06-22 18:48:46 +0000 | [diff] [blame] | 1220 | #if defined(TARGET_HAS_SMC) || 1 |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1221 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1222 | #if defined(CONFIG_USER_ONLY) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1223 | if (p->flags & PAGE_WRITE) { |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1224 | target_ulong addr; |
| 1225 | PageDesc *p2; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1226 | int prot; |
| 1227 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1228 | /* force the host page as non writable (writes will have a |
| 1229 | page fault + mprotect overhead) */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1230 | page_addr &= qemu_host_page_mask; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1231 | prot = 0; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1232 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
| 1233 | addr += TARGET_PAGE_SIZE) { |
| 1234 | |
| 1235 | p2 = page_find (addr >> TARGET_PAGE_BITS); |
| 1236 | if (!p2) |
| 1237 | continue; |
| 1238 | prot |= p2->flags; |
| 1239 | p2->flags &= ~PAGE_WRITE; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1240 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1241 | mprotect(g2h(page_addr), qemu_host_page_size, |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1242 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
| 1243 | #ifdef DEBUG_TB_INVALIDATE |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 1244 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1245 | page_addr); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1246 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1247 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1248 | #else |
| 1249 | /* if some code is already present, then the pages are already |
| 1250 | protected. So we handle the case where only the first TB is |
| 1251 | allocated in a physical page */ |
| 1252 | if (!last_first_tb) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1253 | tlb_protect_code(page_addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1254 | } |
| 1255 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1256 | |
| 1257 | #endif /* TARGET_HAS_SMC */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1258 | } |
| 1259 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1260 | /* add a new TB and link it to the physical page tables. phys_page2 is |
| 1261 | (-1) to indicate that only one page contains the TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1262 | void tb_link_page(TranslationBlock *tb, |
| 1263 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1264 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1265 | unsigned int h; |
| 1266 | TranslationBlock **ptb; |
| 1267 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1268 | /* Grab the mmap lock to stop another thread invalidating this TB |
| 1269 | before we are done. */ |
| 1270 | mmap_lock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1271 | /* add in the physical hash table */ |
| 1272 | h = tb_phys_hash_func(phys_pc); |
| 1273 | ptb = &tb_phys_hash[h]; |
| 1274 | tb->phys_hash_next = *ptb; |
| 1275 | *ptb = tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1276 | |
| 1277 | /* add in the page list */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1278 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
| 1279 | if (phys_page2 != -1) |
| 1280 | tb_alloc_page(tb, 1, phys_page2); |
| 1281 | else |
| 1282 | tb->page_addr[1] = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1283 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1284 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
| 1285 | tb->jmp_next[0] = NULL; |
| 1286 | tb->jmp_next[1] = NULL; |
| 1287 | |
| 1288 | /* init original jump addresses */ |
| 1289 | if (tb->tb_next_offset[0] != 0xffff) |
| 1290 | tb_reset_jump(tb, 0); |
| 1291 | if (tb->tb_next_offset[1] != 0xffff) |
| 1292 | tb_reset_jump(tb, 1); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1293 | |
| 1294 | #ifdef DEBUG_TB_CHECK |
| 1295 | tb_page_check(); |
| 1296 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1297 | mmap_unlock(); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1298 | } |
| 1299 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1300 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
| 1301 | tb[1].tc_ptr. Return NULL if not found */ |
| 1302 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) |
| 1303 | { |
| 1304 | int m_min, m_max, m; |
| 1305 | unsigned long v; |
| 1306 | TranslationBlock *tb; |
| 1307 | |
| 1308 | if (nb_tbs <= 0) |
| 1309 | return NULL; |
| 1310 | if (tc_ptr < (unsigned long)code_gen_buffer || |
| 1311 | tc_ptr >= (unsigned long)code_gen_ptr) |
| 1312 | return NULL; |
| 1313 | /* binary search (cf Knuth) */ |
| 1314 | m_min = 0; |
| 1315 | m_max = nb_tbs - 1; |
| 1316 | while (m_min <= m_max) { |
| 1317 | m = (m_min + m_max) >> 1; |
| 1318 | tb = &tbs[m]; |
| 1319 | v = (unsigned long)tb->tc_ptr; |
| 1320 | if (v == tc_ptr) |
| 1321 | return tb; |
| 1322 | else if (tc_ptr < v) { |
| 1323 | m_max = m - 1; |
| 1324 | } else { |
| 1325 | m_min = m + 1; |
| 1326 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1327 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1328 | return &tbs[m_max]; |
| 1329 | } |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1330 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1331 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
| 1332 | |
| 1333 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) |
| 1334 | { |
| 1335 | TranslationBlock *tb1, *tb_next, **ptb; |
| 1336 | unsigned int n1; |
| 1337 | |
| 1338 | tb1 = tb->jmp_next[n]; |
| 1339 | if (tb1 != NULL) { |
| 1340 | /* find head of list */ |
| 1341 | for(;;) { |
| 1342 | n1 = (long)tb1 & 3; |
| 1343 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1344 | if (n1 == 2) |
| 1345 | break; |
| 1346 | tb1 = tb1->jmp_next[n1]; |
| 1347 | } |
| 1348 | /* we are now sure now that tb jumps to tb1 */ |
| 1349 | tb_next = tb1; |
| 1350 | |
| 1351 | /* remove tb from the jmp_first list */ |
| 1352 | ptb = &tb_next->jmp_first; |
| 1353 | for(;;) { |
| 1354 | tb1 = *ptb; |
| 1355 | n1 = (long)tb1 & 3; |
| 1356 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1357 | if (n1 == n && tb1 == tb) |
| 1358 | break; |
| 1359 | ptb = &tb1->jmp_next[n1]; |
| 1360 | } |
| 1361 | *ptb = tb->jmp_next[n]; |
| 1362 | tb->jmp_next[n] = NULL; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1363 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1364 | /* suppress the jump to next tb in generated code */ |
| 1365 | tb_reset_jump(tb, n); |
| 1366 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1367 | /* suppress jumps in the tb on which we could have jumped */ |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1368 | tb_reset_jump_recursive(tb_next); |
| 1369 | } |
| 1370 | } |
| 1371 | |
| 1372 | static void tb_reset_jump_recursive(TranslationBlock *tb) |
| 1373 | { |
| 1374 | tb_reset_jump_recursive2(tb, 0); |
| 1375 | tb_reset_jump_recursive2(tb, 1); |
| 1376 | } |
| 1377 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1378 | #if defined(TARGET_HAS_ICE) |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1379 | #if defined(CONFIG_USER_ONLY) |
| 1380 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1381 | { |
| 1382 | tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 1383 | } |
| 1384 | #else |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1385 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1386 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1387 | target_phys_addr_t addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 1388 | target_ulong pd; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1389 | ram_addr_t ram_addr; |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1390 | PhysPageDesc *p; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1391 | |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1392 | addr = cpu_get_phys_page_debug(env, pc); |
| 1393 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 1394 | if (!p) { |
| 1395 | pd = IO_MEM_UNASSIGNED; |
| 1396 | } else { |
| 1397 | pd = p->phys_offset; |
| 1398 | } |
| 1399 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); |
pbrook | 706cd4b | 2006-04-08 17:36:21 +0000 | [diff] [blame] | 1400 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1401 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1402 | #endif |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1403 | #endif /* TARGET_HAS_ICE */ |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1404 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1405 | #if defined(CONFIG_USER_ONLY) |
| 1406 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1407 | |
| 1408 | { |
| 1409 | } |
| 1410 | |
| 1411 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1412 | int flags, CPUWatchpoint **watchpoint) |
| 1413 | { |
| 1414 | return -ENOSYS; |
| 1415 | } |
| 1416 | #else |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1417 | /* Add a watchpoint. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1418 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1419 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1420 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1421 | target_ulong len_mask = ~(len - 1); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1422 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1423 | |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1424 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
| 1425 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { |
| 1426 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
| 1427 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 1428 | return -EINVAL; |
| 1429 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1430 | wp = qemu_malloc(sizeof(*wp)); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1431 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1432 | wp->vaddr = addr; |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1433 | wp->len_mask = len_mask; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1434 | wp->flags = flags; |
| 1435 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1436 | /* keep all GDB-injected watchpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1437 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1438 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1439 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1440 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1441 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1442 | tlb_flush_page(env, addr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1443 | |
| 1444 | if (watchpoint) |
| 1445 | *watchpoint = wp; |
| 1446 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1447 | } |
| 1448 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1449 | /* Remove a specific watchpoint. */ |
| 1450 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, |
| 1451 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1452 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1453 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1454 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1455 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1456 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1457 | if (addr == wp->vaddr && len_mask == wp->len_mask |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1458 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1459 | cpu_watchpoint_remove_by_ref(env, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1460 | return 0; |
| 1461 | } |
| 1462 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1463 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1464 | } |
| 1465 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1466 | /* Remove a specific watchpoint by reference. */ |
| 1467 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) |
| 1468 | { |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1469 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1470 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1471 | tlb_flush_page(env, watchpoint->vaddr); |
| 1472 | |
| 1473 | qemu_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1474 | } |
| 1475 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1476 | /* Remove all matching watchpoints. */ |
| 1477 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1478 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1479 | CPUWatchpoint *wp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1480 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1481 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1482 | if (wp->flags & mask) |
| 1483 | cpu_watchpoint_remove_by_ref(env, wp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1484 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1485 | } |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1486 | #endif |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1487 | |
| 1488 | /* Add a breakpoint. */ |
| 1489 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 1490 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1491 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1492 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1493 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1494 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1495 | bp = qemu_malloc(sizeof(*bp)); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1496 | |
| 1497 | bp->pc = pc; |
| 1498 | bp->flags = flags; |
| 1499 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1500 | /* keep all GDB-injected breakpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1501 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1502 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1503 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1504 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1505 | |
| 1506 | breakpoint_invalidate(env, pc); |
| 1507 | |
| 1508 | if (breakpoint) |
| 1509 | *breakpoint = bp; |
| 1510 | return 0; |
| 1511 | #else |
| 1512 | return -ENOSYS; |
| 1513 | #endif |
| 1514 | } |
| 1515 | |
| 1516 | /* Remove a specific breakpoint. */ |
| 1517 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) |
| 1518 | { |
| 1519 | #if defined(TARGET_HAS_ICE) |
| 1520 | CPUBreakpoint *bp; |
| 1521 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1522 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1523 | if (bp->pc == pc && bp->flags == flags) { |
| 1524 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1525 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1526 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1527 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1528 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1529 | #else |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1530 | return -ENOSYS; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1531 | #endif |
| 1532 | } |
| 1533 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1534 | /* Remove a specific breakpoint by reference. */ |
| 1535 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1536 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1537 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1538 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1539 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1540 | breakpoint_invalidate(env, breakpoint->pc); |
| 1541 | |
| 1542 | qemu_free(breakpoint); |
| 1543 | #endif |
| 1544 | } |
| 1545 | |
| 1546 | /* Remove all matching breakpoints. */ |
| 1547 | void cpu_breakpoint_remove_all(CPUState *env, int mask) |
| 1548 | { |
| 1549 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1550 | CPUBreakpoint *bp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1551 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1552 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1553 | if (bp->flags & mask) |
| 1554 | cpu_breakpoint_remove_by_ref(env, bp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1555 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1556 | #endif |
| 1557 | } |
| 1558 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1559 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 1560 | CPU loop after each instruction */ |
| 1561 | void cpu_single_step(CPUState *env, int enabled) |
| 1562 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1563 | #if defined(TARGET_HAS_ICE) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1564 | if (env->singlestep_enabled != enabled) { |
| 1565 | env->singlestep_enabled = enabled; |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1566 | if (kvm_enabled()) |
| 1567 | kvm_update_guest_debug(env, 0); |
| 1568 | else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 1569 | /* must flush all the translated code to avoid inconsistencies */ |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1570 | /* XXX: only flush what is necessary */ |
| 1571 | tb_flush(env); |
| 1572 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1573 | } |
| 1574 | #endif |
| 1575 | } |
| 1576 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1577 | /* enable or disable low levels log */ |
| 1578 | void cpu_set_log(int log_flags) |
| 1579 | { |
| 1580 | loglevel = log_flags; |
| 1581 | if (loglevel && !logfile) { |
pbrook | 11fcfab | 2007-07-01 18:21:11 +0000 | [diff] [blame] | 1582 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1583 | if (!logfile) { |
| 1584 | perror(logfilename); |
| 1585 | _exit(1); |
| 1586 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1587 | #if !defined(CONFIG_SOFTMMU) |
| 1588 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
| 1589 | { |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1590 | static char logfile_buf[4096]; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1591 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
| 1592 | } |
Filip Navara | bf65f53 | 2009-07-27 10:02:04 -0500 | [diff] [blame] | 1593 | #elif !defined(_WIN32) |
| 1594 | /* Win32 doesn't support line-buffering and requires size >= 2 */ |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1595 | setvbuf(logfile, NULL, _IOLBF, 0); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1596 | #endif |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1597 | log_append = 1; |
| 1598 | } |
| 1599 | if (!loglevel && logfile) { |
| 1600 | fclose(logfile); |
| 1601 | logfile = NULL; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1602 | } |
| 1603 | } |
| 1604 | |
| 1605 | void cpu_set_log_filename(const char *filename) |
| 1606 | { |
| 1607 | logfilename = strdup(filename); |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1608 | if (logfile) { |
| 1609 | fclose(logfile); |
| 1610 | logfile = NULL; |
| 1611 | } |
| 1612 | cpu_set_log(loglevel); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1613 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1614 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1615 | static void cpu_unlink_tb(CPUState *env) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1616 | { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1617 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
| 1618 | problem and hope the cpu will stop of its own accord. For userspace |
| 1619 | emulation this often isn't actually as bad as it sounds. Often |
| 1620 | signals are used primarily to interrupt blocking syscalls. */ |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1621 | TranslationBlock *tb; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1622 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1623 | |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1624 | spin_lock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1625 | tb = env->current_tb; |
| 1626 | /* if the cpu is currently executing code, we must unlink it and |
| 1627 | all the potentially executing TB */ |
Riku Voipio | f76cfe5 | 2009-12-04 15:16:30 +0200 | [diff] [blame] | 1628 | if (tb) { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1629 | env->current_tb = NULL; |
| 1630 | tb_reset_jump_recursive(tb); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1631 | } |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1632 | spin_unlock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1633 | } |
| 1634 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1635 | #ifndef CONFIG_USER_ONLY |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1636 | /* mask must never be zero, except for A20 change call */ |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1637 | static void tcg_handle_interrupt(CPUState *env, int mask) |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1638 | { |
| 1639 | int old_mask; |
| 1640 | |
| 1641 | old_mask = env->interrupt_request; |
| 1642 | env->interrupt_request |= mask; |
| 1643 | |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1644 | /* |
| 1645 | * If called from iothread context, wake the target cpu in |
| 1646 | * case its halted. |
| 1647 | */ |
Jan Kiszka | b7680cb | 2011-03-12 17:43:51 +0100 | [diff] [blame] | 1648 | if (!qemu_cpu_is_self(env)) { |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1649 | qemu_cpu_kick(env); |
| 1650 | return; |
| 1651 | } |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1652 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1653 | if (use_icount) { |
pbrook | 266910c | 2008-07-09 15:31:50 +0000 | [diff] [blame] | 1654 | env->icount_decr.u16.high = 0xffff; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1655 | if (!can_do_io(env) |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 1656 | && (mask & ~old_mask) != 0) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1657 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
| 1658 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1659 | } else { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1660 | cpu_unlink_tb(env); |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1661 | } |
| 1662 | } |
| 1663 | |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1664 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
| 1665 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1666 | #else /* CONFIG_USER_ONLY */ |
| 1667 | |
| 1668 | void cpu_interrupt(CPUState *env, int mask) |
| 1669 | { |
| 1670 | env->interrupt_request |= mask; |
| 1671 | cpu_unlink_tb(env); |
| 1672 | } |
| 1673 | #endif /* CONFIG_USER_ONLY */ |
| 1674 | |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 1675 | void cpu_reset_interrupt(CPUState *env, int mask) |
| 1676 | { |
| 1677 | env->interrupt_request &= ~mask; |
| 1678 | } |
| 1679 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1680 | void cpu_exit(CPUState *env) |
| 1681 | { |
| 1682 | env->exit_request = 1; |
| 1683 | cpu_unlink_tb(env); |
| 1684 | } |
| 1685 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1686 | const CPULogItem cpu_log_items[] = { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1687 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1688 | "show generated host assembly code for each compiled TB" }, |
| 1689 | { CPU_LOG_TB_IN_ASM, "in_asm", |
| 1690 | "show target assembly code for each compiled TB" }, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1691 | { CPU_LOG_TB_OP, "op", |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 1692 | "show micro ops for each compiled TB" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1693 | { CPU_LOG_TB_OP_OPT, "op_opt", |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1694 | "show micro ops " |
| 1695 | #ifdef TARGET_I386 |
| 1696 | "before eflags optimization and " |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1697 | #endif |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1698 | "after liveness analysis" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1699 | { CPU_LOG_INT, "int", |
| 1700 | "show interrupts/exceptions in short format" }, |
| 1701 | { CPU_LOG_EXEC, "exec", |
| 1702 | "show trace before each executed TB (lots of logs)" }, |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1703 | { CPU_LOG_TB_CPU, "cpu", |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 1704 | "show CPU state before block translation" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1705 | #ifdef TARGET_I386 |
| 1706 | { CPU_LOG_PCALL, "pcall", |
| 1707 | "show protected mode far calls/returns/exceptions" }, |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 1708 | { CPU_LOG_RESET, "cpu_reset", |
| 1709 | "show CPU state before CPU resets" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1710 | #endif |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1711 | #ifdef DEBUG_IOPORT |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 1712 | { CPU_LOG_IOPORT, "ioport", |
| 1713 | "show all i/o ports accesses" }, |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1714 | #endif |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1715 | { 0, NULL, NULL }, |
| 1716 | }; |
| 1717 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1718 | #ifndef CONFIG_USER_ONLY |
| 1719 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list |
| 1720 | = QLIST_HEAD_INITIALIZER(memory_client_list); |
| 1721 | |
| 1722 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1723 | ram_addr_t size, |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 1724 | ram_addr_t phys_offset, |
| 1725 | bool log_dirty) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1726 | { |
| 1727 | CPUPhysMemoryClient *client; |
| 1728 | QLIST_FOREACH(client, &memory_client_list, list) { |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 1729 | client->set_memory(client, start_addr, size, phys_offset, log_dirty); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1730 | } |
| 1731 | } |
| 1732 | |
| 1733 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1734 | target_phys_addr_t end) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1735 | { |
| 1736 | CPUPhysMemoryClient *client; |
| 1737 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1738 | int r = client->sync_dirty_bitmap(client, start, end); |
| 1739 | if (r < 0) |
| 1740 | return r; |
| 1741 | } |
| 1742 | return 0; |
| 1743 | } |
| 1744 | |
| 1745 | static int cpu_notify_migration_log(int enable) |
| 1746 | { |
| 1747 | CPUPhysMemoryClient *client; |
| 1748 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1749 | int r = client->migration_log(client, enable); |
| 1750 | if (r < 0) |
| 1751 | return r; |
| 1752 | } |
| 1753 | return 0; |
| 1754 | } |
| 1755 | |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1756 | /* The l1_phys_map provides the upper P_L1_BITs of the guest physical |
| 1757 | * address. Each intermediate table provides the next L2_BITs of guest |
| 1758 | * physical address space. The number of levels vary based on host and |
| 1759 | * guest configuration, making it efficient to build the final guest |
| 1760 | * physical address by seeding the L1 offset and shifting and adding in |
| 1761 | * each L2 offset as we recurse through them. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1762 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1763 | int level, void **lp, target_phys_addr_t addr) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1764 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1765 | int i; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1766 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1767 | if (*lp == NULL) { |
| 1768 | return; |
| 1769 | } |
| 1770 | if (level == 0) { |
| 1771 | PhysPageDesc *pd = *lp; |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1772 | addr <<= L2_BITS + TARGET_PAGE_BITS; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1773 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1774 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1775 | client->set_memory(client, addr | i << TARGET_PAGE_BITS, |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 1776 | TARGET_PAGE_SIZE, pd[i].phys_offset, false); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1777 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1778 | } |
| 1779 | } else { |
| 1780 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1781 | for (i = 0; i < L2_SIZE; ++i) { |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1782 | phys_page_for_each_1(client, level - 1, pp + i, |
| 1783 | (addr << L2_BITS) | i); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1784 | } |
| 1785 | } |
| 1786 | } |
| 1787 | |
| 1788 | static void phys_page_for_each(CPUPhysMemoryClient *client) |
| 1789 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1790 | int i; |
| 1791 | for (i = 0; i < P_L1_SIZE; ++i) { |
| 1792 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1793 | l1_phys_map + i, i); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1794 | } |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1795 | } |
| 1796 | |
| 1797 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) |
| 1798 | { |
| 1799 | QLIST_INSERT_HEAD(&memory_client_list, client, list); |
| 1800 | phys_page_for_each(client); |
| 1801 | } |
| 1802 | |
| 1803 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) |
| 1804 | { |
| 1805 | QLIST_REMOVE(client, list); |
| 1806 | } |
| 1807 | #endif |
| 1808 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1809 | static int cmp1(const char *s1, int n, const char *s2) |
| 1810 | { |
| 1811 | if (strlen(s2) != n) |
| 1812 | return 0; |
| 1813 | return memcmp(s1, s2, n) == 0; |
| 1814 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1815 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1816 | /* takes a comma separated list of log masks. Return 0 if error. */ |
| 1817 | int cpu_str_to_log_mask(const char *str) |
| 1818 | { |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1819 | const CPULogItem *item; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1820 | int mask; |
| 1821 | const char *p, *p1; |
| 1822 | |
| 1823 | p = str; |
| 1824 | mask = 0; |
| 1825 | for(;;) { |
| 1826 | p1 = strchr(p, ','); |
| 1827 | if (!p1) |
| 1828 | p1 = p + strlen(p); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1829 | if(cmp1(p,p1-p,"all")) { |
| 1830 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1831 | mask |= item->mask; |
| 1832 | } |
| 1833 | } else { |
| 1834 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1835 | if (cmp1(p, p1 - p, item->name)) |
| 1836 | goto found; |
| 1837 | } |
| 1838 | return 0; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1839 | } |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1840 | found: |
| 1841 | mask |= item->mask; |
| 1842 | if (*p1 != ',') |
| 1843 | break; |
| 1844 | p = p1 + 1; |
| 1845 | } |
| 1846 | return mask; |
| 1847 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1848 | |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1849 | void cpu_abort(CPUState *env, const char *fmt, ...) |
| 1850 | { |
| 1851 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1852 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1853 | |
| 1854 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1855 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1856 | fprintf(stderr, "qemu: fatal: "); |
| 1857 | vfprintf(stderr, fmt, ap); |
| 1858 | fprintf(stderr, "\n"); |
| 1859 | #ifdef TARGET_I386 |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 1860 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1861 | #else |
| 1862 | cpu_dump_state(env, stderr, fprintf, 0); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1863 | #endif |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1864 | if (qemu_log_enabled()) { |
| 1865 | qemu_log("qemu: fatal: "); |
| 1866 | qemu_log_vprintf(fmt, ap2); |
| 1867 | qemu_log("\n"); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1868 | #ifdef TARGET_I386 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1869 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1870 | #else |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1871 | log_cpu_state(env, 0); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1872 | #endif |
aliguori | 31b1a7b | 2009-01-15 22:35:09 +0000 | [diff] [blame] | 1873 | qemu_log_flush(); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1874 | qemu_log_close(); |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1875 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1876 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1877 | va_end(ap); |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 1878 | #if defined(CONFIG_USER_ONLY) |
| 1879 | { |
| 1880 | struct sigaction act; |
| 1881 | sigfillset(&act.sa_mask); |
| 1882 | act.sa_handler = SIG_DFL; |
| 1883 | sigaction(SIGABRT, &act, NULL); |
| 1884 | } |
| 1885 | #endif |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1886 | abort(); |
| 1887 | } |
| 1888 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1889 | CPUState *cpu_copy(CPUState *env) |
| 1890 | { |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 1891 | CPUState *new_env = cpu_init(env->cpu_model_str); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1892 | CPUState *next_cpu = new_env->next_cpu; |
| 1893 | int cpu_index = new_env->cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1894 | #if defined(TARGET_HAS_ICE) |
| 1895 | CPUBreakpoint *bp; |
| 1896 | CPUWatchpoint *wp; |
| 1897 | #endif |
| 1898 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1899 | memcpy(new_env, env, sizeof(CPUState)); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1900 | |
| 1901 | /* Preserve chaining and index. */ |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1902 | new_env->next_cpu = next_cpu; |
| 1903 | new_env->cpu_index = cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1904 | |
| 1905 | /* Clone all break/watchpoints. |
| 1906 | Note: Once we support ptrace with hw-debug register access, make sure |
| 1907 | BP_CPU break/watchpoints are handled correctly on clone. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1908 | QTAILQ_INIT(&env->breakpoints); |
| 1909 | QTAILQ_INIT(&env->watchpoints); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1910 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1911 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1912 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
| 1913 | } |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1914 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1915 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
| 1916 | wp->flags, NULL); |
| 1917 | } |
| 1918 | #endif |
| 1919 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1920 | return new_env; |
| 1921 | } |
| 1922 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1923 | #if !defined(CONFIG_USER_ONLY) |
| 1924 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1925 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
| 1926 | { |
| 1927 | unsigned int i; |
| 1928 | |
| 1929 | /* Discard jump cache entries for any tb which might potentially |
| 1930 | overlap the flushed page. */ |
| 1931 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); |
| 1932 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1933 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1934 | |
| 1935 | i = tb_jmp_cache_hash_page(addr); |
| 1936 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1937 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1938 | } |
| 1939 | |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1940 | static CPUTLBEntry s_cputlb_empty_entry = { |
| 1941 | .addr_read = -1, |
| 1942 | .addr_write = -1, |
| 1943 | .addr_code = -1, |
| 1944 | .addend = -1, |
| 1945 | }; |
| 1946 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 1947 | /* NOTE: if flush_global is true, also flush global entries (not |
| 1948 | implemented yet) */ |
| 1949 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1950 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1951 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1952 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1953 | #if defined(DEBUG_TLB) |
| 1954 | printf("tlb_flush:\n"); |
| 1955 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1956 | /* must reset current TB so that interrupts cannot modify the |
| 1957 | links while we are modifying them */ |
| 1958 | env->current_tb = NULL; |
| 1959 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1960 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1961 | int mmu_idx; |
| 1962 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1963 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1964 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1965 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1966 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1967 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1968 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1969 | env->tlb_flush_addr = -1; |
| 1970 | env->tlb_flush_mask = 0; |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 1971 | tlb_flush_count++; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1972 | } |
| 1973 | |
bellard | 274da6b | 2004-05-20 21:56:27 +0000 | [diff] [blame] | 1974 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1975 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1976 | if (addr == (tlb_entry->addr_read & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1977 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1978 | addr == (tlb_entry->addr_write & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1979 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1980 | addr == (tlb_entry->addr_code & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1981 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1982 | *tlb_entry = s_cputlb_empty_entry; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 1983 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 1984 | } |
| 1985 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 1986 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1987 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1988 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 1989 | int mmu_idx; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1990 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1991 | #if defined(DEBUG_TLB) |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 1992 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1993 | #endif |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 1994 | /* Check if we need to flush due to large pages. */ |
| 1995 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { |
| 1996 | #if defined(DEBUG_TLB) |
| 1997 | printf("tlb_flush_page: forced full flush (" |
| 1998 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
| 1999 | env->tlb_flush_addr, env->tlb_flush_mask); |
| 2000 | #endif |
| 2001 | tlb_flush(env, 1); |
| 2002 | return; |
| 2003 | } |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2004 | /* must reset current TB so that interrupts cannot modify the |
| 2005 | links while we are modifying them */ |
| 2006 | env->current_tb = NULL; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2007 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2008 | addr &= TARGET_PAGE_MASK; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2009 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2010 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2011 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2012 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2013 | tlb_flush_jmp_cache(env, addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2014 | } |
| 2015 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2016 | /* update the TLBs so that writes to code in the virtual page 'addr' |
| 2017 | can be detected */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2018 | static void tlb_protect_code(ram_addr_t ram_addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2019 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2020 | cpu_physical_memory_reset_dirty(ram_addr, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2021 | ram_addr + TARGET_PAGE_SIZE, |
| 2022 | CODE_DIRTY_FLAG); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2023 | } |
| 2024 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2025 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2026 | tested for self modifying code */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2027 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2028 | target_ulong vaddr) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2029 | { |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2030 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2031 | } |
| 2032 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2033 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2034 | unsigned long start, unsigned long length) |
| 2035 | { |
| 2036 | unsigned long addr; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2037 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
| 2038 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2039 | if ((addr - start) < length) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2040 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2041 | } |
| 2042 | } |
| 2043 | } |
| 2044 | |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2045 | /* Note: start and end must be within the same ram block. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2046 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 2047 | int dirty_flags) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2048 | { |
| 2049 | CPUState *env; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2050 | unsigned long length, start1; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2051 | int i; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2052 | |
| 2053 | start &= TARGET_PAGE_MASK; |
| 2054 | end = TARGET_PAGE_ALIGN(end); |
| 2055 | |
| 2056 | length = end - start; |
| 2057 | if (length == 0) |
| 2058 | return; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2059 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2060 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2061 | /* we modify the TLB cache so that the dirty bit will be set again |
| 2062 | when accessing the range */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2063 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2064 | /* Chek that we don't span multiple blocks - this breaks the |
| 2065 | address comparisons below. */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2066 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2067 | != (end - 1) - start) { |
| 2068 | abort(); |
| 2069 | } |
| 2070 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2071 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2072 | int mmu_idx; |
| 2073 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2074 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2075 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
| 2076 | start1, length); |
| 2077 | } |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2078 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2079 | } |
| 2080 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2081 | int cpu_physical_memory_set_dirty_tracking(int enable) |
| 2082 | { |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2083 | int ret = 0; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2084 | in_migration = enable; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2085 | ret = cpu_notify_migration_log(!!enable); |
| 2086 | return ret; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2087 | } |
| 2088 | |
| 2089 | int cpu_physical_memory_get_dirty_tracking(void) |
| 2090 | { |
| 2091 | return in_migration; |
| 2092 | } |
| 2093 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2094 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
| 2095 | target_phys_addr_t end_addr) |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2096 | { |
Michael S. Tsirkin | 7b8f3b7 | 2010-01-27 22:07:21 +0200 | [diff] [blame] | 2097 | int ret; |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2098 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2099 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2100 | return ret; |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2101 | } |
| 2102 | |
Anthony PERARD | e5896b1 | 2011-02-07 12:19:23 +0100 | [diff] [blame] | 2103 | int cpu_physical_log_start(target_phys_addr_t start_addr, |
| 2104 | ram_addr_t size) |
| 2105 | { |
| 2106 | CPUPhysMemoryClient *client; |
| 2107 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 2108 | if (client->log_start) { |
| 2109 | int r = client->log_start(client, start_addr, size); |
| 2110 | if (r < 0) { |
| 2111 | return r; |
| 2112 | } |
| 2113 | } |
| 2114 | } |
| 2115 | return 0; |
| 2116 | } |
| 2117 | |
| 2118 | int cpu_physical_log_stop(target_phys_addr_t start_addr, |
| 2119 | ram_addr_t size) |
| 2120 | { |
| 2121 | CPUPhysMemoryClient *client; |
| 2122 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 2123 | if (client->log_stop) { |
| 2124 | int r = client->log_stop(client, start_addr, size); |
| 2125 | if (r < 0) { |
| 2126 | return r; |
| 2127 | } |
| 2128 | } |
| 2129 | } |
| 2130 | return 0; |
| 2131 | } |
| 2132 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2133 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
| 2134 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2135 | ram_addr_t ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2136 | void *p; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2137 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2138 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2139 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
| 2140 | + tlb_entry->addend); |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 2141 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2142 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2143 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2144 | } |
| 2145 | } |
| 2146 | } |
| 2147 | |
| 2148 | /* update the TLB according to the current state of the dirty bits */ |
| 2149 | void cpu_tlb_update_dirty(CPUState *env) |
| 2150 | { |
| 2151 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2152 | int mmu_idx; |
| 2153 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2154 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2155 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); |
| 2156 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2157 | } |
| 2158 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2159 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2160 | { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2161 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
| 2162 | tlb_entry->addr_write = vaddr; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2163 | } |
| 2164 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2165 | /* update the TLB corresponding to virtual page vaddr |
| 2166 | so that it is no longer dirty */ |
| 2167 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2168 | { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2169 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2170 | int mmu_idx; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2171 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2172 | vaddr &= TARGET_PAGE_MASK; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2173 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2174 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2175 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2176 | } |
| 2177 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2178 | /* Our TLB does not support large pages, so remember the area covered by |
| 2179 | large pages and trigger a full TLB flush if these are invalidated. */ |
| 2180 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, |
| 2181 | target_ulong size) |
| 2182 | { |
| 2183 | target_ulong mask = ~(size - 1); |
| 2184 | |
| 2185 | if (env->tlb_flush_addr == (target_ulong)-1) { |
| 2186 | env->tlb_flush_addr = vaddr & mask; |
| 2187 | env->tlb_flush_mask = mask; |
| 2188 | return; |
| 2189 | } |
| 2190 | /* Extend the existing region to include the new page. |
| 2191 | This is a compromise between unnecessary flushes and the cost |
| 2192 | of maintaining a full variable size TLB. */ |
| 2193 | mask &= env->tlb_flush_mask; |
| 2194 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
| 2195 | mask <<= 1; |
| 2196 | } |
| 2197 | env->tlb_flush_addr &= mask; |
| 2198 | env->tlb_flush_mask = mask; |
| 2199 | } |
| 2200 | |
| 2201 | /* Add a new TLB entry. At most one entry for a given virtual address |
| 2202 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the |
| 2203 | supplied size is only used by tlb_flush_page. */ |
| 2204 | void tlb_set_page(CPUState *env, target_ulong vaddr, |
| 2205 | target_phys_addr_t paddr, int prot, |
| 2206 | int mmu_idx, target_ulong size) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2207 | { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2208 | PhysPageDesc *p; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2209 | unsigned long pd; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2210 | unsigned int index; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2211 | target_ulong address; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2212 | target_ulong code_address; |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 2213 | unsigned long addend; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2214 | CPUTLBEntry *te; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2215 | CPUWatchpoint *wp; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2216 | target_phys_addr_t iotlb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2217 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2218 | assert(size >= TARGET_PAGE_SIZE); |
| 2219 | if (size != TARGET_PAGE_SIZE) { |
| 2220 | tlb_add_large_page(env, vaddr, size); |
| 2221 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2222 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2223 | if (!p) { |
| 2224 | pd = IO_MEM_UNASSIGNED; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2225 | } else { |
| 2226 | pd = p->phys_offset; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2227 | } |
| 2228 | #if defined(DEBUG_TLB) |
Stefan Weil | 7fd3f49 | 2010-09-30 22:39:51 +0200 | [diff] [blame] | 2229 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
| 2230 | " prot=%x idx=%d pd=0x%08lx\n", |
| 2231 | vaddr, paddr, prot, mmu_idx, pd); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2232 | #endif |
| 2233 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2234 | address = vaddr; |
| 2235 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
| 2236 | /* IO memory case (romd handled later) */ |
| 2237 | address |= TLB_MMIO; |
| 2238 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2239 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2240 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
| 2241 | /* Normal RAM. */ |
| 2242 | iotlb = pd & TARGET_PAGE_MASK; |
| 2243 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 2244 | iotlb |= IO_MEM_NOTDIRTY; |
| 2245 | else |
| 2246 | iotlb |= IO_MEM_ROM; |
| 2247 | } else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2248 | /* IO handlers are currently passed a physical address. |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2249 | It would be nice to pass an offset from the base address |
| 2250 | of that region. This would avoid having to special case RAM, |
| 2251 | and avoid full address decoding in every device. |
| 2252 | We can't use the high bits of pd for this because |
| 2253 | IO_MEM_ROMD uses these as a ram address. */ |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2254 | iotlb = (pd & ~TARGET_PAGE_MASK); |
| 2255 | if (p) { |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2256 | iotlb += p->region_offset; |
| 2257 | } else { |
| 2258 | iotlb += paddr; |
| 2259 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2260 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2261 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2262 | code_address = address; |
| 2263 | /* Make accesses to pages with watchpoints go via the |
| 2264 | watchpoint trap routines. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2265 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2266 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
Jun Koi | bf298f8 | 2010-05-06 14:36:59 +0900 | [diff] [blame] | 2267 | /* Avoid trapping reads of pages with a write breakpoint. */ |
| 2268 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { |
| 2269 | iotlb = io_mem_watch + paddr; |
| 2270 | address |= TLB_MMIO; |
| 2271 | break; |
| 2272 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2273 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2274 | } |
balrog | d79acba | 2007-06-26 20:01:13 +0000 | [diff] [blame] | 2275 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2276 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 2277 | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
| 2278 | te = &env->tlb_table[mmu_idx][index]; |
| 2279 | te->addend = addend - vaddr; |
| 2280 | if (prot & PAGE_READ) { |
| 2281 | te->addr_read = address; |
| 2282 | } else { |
| 2283 | te->addr_read = -1; |
| 2284 | } |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2285 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2286 | if (prot & PAGE_EXEC) { |
| 2287 | te->addr_code = code_address; |
| 2288 | } else { |
| 2289 | te->addr_code = -1; |
| 2290 | } |
| 2291 | if (prot & PAGE_WRITE) { |
| 2292 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
| 2293 | (pd & IO_MEM_ROMD)) { |
| 2294 | /* Write access calls the I/O callback. */ |
| 2295 | te->addr_write = address | TLB_MMIO; |
| 2296 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
| 2297 | !cpu_physical_memory_is_dirty(pd)) { |
| 2298 | te->addr_write = address | TLB_NOTDIRTY; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2299 | } else { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2300 | te->addr_write = address; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2301 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2302 | } else { |
| 2303 | te->addr_write = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2304 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2305 | } |
| 2306 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2307 | #else |
| 2308 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 2309 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2310 | { |
| 2311 | } |
| 2312 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2313 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2314 | { |
| 2315 | } |
| 2316 | |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2317 | /* |
| 2318 | * Walks guest process memory "regions" one by one |
| 2319 | * and calls callback function 'fn' for each region. |
| 2320 | */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2321 | |
| 2322 | struct walk_memory_regions_data |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2323 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2324 | walk_memory_regions_fn fn; |
| 2325 | void *priv; |
| 2326 | unsigned long start; |
| 2327 | int prot; |
| 2328 | }; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2329 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2330 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2331 | abi_ulong end, int new_prot) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2332 | { |
| 2333 | if (data->start != -1ul) { |
| 2334 | int rc = data->fn(data->priv, data->start, end, data->prot); |
| 2335 | if (rc != 0) { |
| 2336 | return rc; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2337 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2338 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2339 | |
| 2340 | data->start = (new_prot ? end : -1ul); |
| 2341 | data->prot = new_prot; |
| 2342 | |
| 2343 | return 0; |
| 2344 | } |
| 2345 | |
| 2346 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2347 | abi_ulong base, int level, void **lp) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2348 | { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2349 | abi_ulong pa; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2350 | int i, rc; |
| 2351 | |
| 2352 | if (*lp == NULL) { |
| 2353 | return walk_memory_regions_end(data, base, 0); |
| 2354 | } |
| 2355 | |
| 2356 | if (level == 0) { |
| 2357 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2358 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2359 | int prot = pd[i].flags; |
| 2360 | |
| 2361 | pa = base | (i << TARGET_PAGE_BITS); |
| 2362 | if (prot != data->prot) { |
| 2363 | rc = walk_memory_regions_end(data, pa, prot); |
| 2364 | if (rc != 0) { |
| 2365 | return rc; |
| 2366 | } |
| 2367 | } |
| 2368 | } |
| 2369 | } else { |
| 2370 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2371 | for (i = 0; i < L2_SIZE; ++i) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2372 | pa = base | ((abi_ulong)i << |
| 2373 | (TARGET_PAGE_BITS + L2_BITS * level)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2374 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
| 2375 | if (rc != 0) { |
| 2376 | return rc; |
| 2377 | } |
| 2378 | } |
| 2379 | } |
| 2380 | |
| 2381 | return 0; |
| 2382 | } |
| 2383 | |
| 2384 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) |
| 2385 | { |
| 2386 | struct walk_memory_regions_data data; |
| 2387 | unsigned long i; |
| 2388 | |
| 2389 | data.fn = fn; |
| 2390 | data.priv = priv; |
| 2391 | data.start = -1ul; |
| 2392 | data.prot = 0; |
| 2393 | |
| 2394 | for (i = 0; i < V_L1_SIZE; i++) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2395 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2396 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
| 2397 | if (rc != 0) { |
| 2398 | return rc; |
| 2399 | } |
| 2400 | } |
| 2401 | |
| 2402 | return walk_memory_regions_end(&data, 0, 0); |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2403 | } |
| 2404 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2405 | static int dump_region(void *priv, abi_ulong start, |
| 2406 | abi_ulong end, unsigned long prot) |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2407 | { |
| 2408 | FILE *f = (FILE *)priv; |
| 2409 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2410 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
| 2411 | " "TARGET_ABI_FMT_lx" %c%c%c\n", |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2412 | start, end, end - start, |
| 2413 | ((prot & PAGE_READ) ? 'r' : '-'), |
| 2414 | ((prot & PAGE_WRITE) ? 'w' : '-'), |
| 2415 | ((prot & PAGE_EXEC) ? 'x' : '-')); |
| 2416 | |
| 2417 | return (0); |
| 2418 | } |
| 2419 | |
| 2420 | /* dump memory mappings */ |
| 2421 | void page_dump(FILE *f) |
| 2422 | { |
| 2423 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", |
| 2424 | "start", "end", "size", "prot"); |
| 2425 | walk_memory_regions(f, dump_region); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2426 | } |
| 2427 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2428 | int page_get_flags(target_ulong address) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2429 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2430 | PageDesc *p; |
| 2431 | |
| 2432 | p = page_find(address >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2433 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2434 | return 0; |
| 2435 | return p->flags; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2436 | } |
| 2437 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2438 | /* Modify the flags of a page and invalidate the code if necessary. |
| 2439 | The flag PAGE_WRITE_ORG is positioned automatically depending |
| 2440 | on PAGE_WRITE. The mmap_lock should already be held. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2441 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2442 | { |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2443 | target_ulong addr, len; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2444 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2445 | /* This function should never be called with addresses outside the |
| 2446 | guest address space. If this assert fires, it probably indicates |
| 2447 | a missing call to h2g_valid. */ |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2448 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2449 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2450 | #endif |
| 2451 | assert(start < end); |
| 2452 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2453 | start = start & TARGET_PAGE_MASK; |
| 2454 | end = TARGET_PAGE_ALIGN(end); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2455 | |
| 2456 | if (flags & PAGE_WRITE) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2457 | flags |= PAGE_WRITE_ORG; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | for (addr = start, len = end - start; |
| 2461 | len != 0; |
| 2462 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
| 2463 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2464 | |
| 2465 | /* If the write protection bit is set, then we invalidate |
| 2466 | the code inside. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2467 | if (!(p->flags & PAGE_WRITE) && |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2468 | (flags & PAGE_WRITE) && |
| 2469 | p->first_tb) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2470 | tb_invalidate_phys_page(addr, 0, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2471 | } |
| 2472 | p->flags = flags; |
| 2473 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2474 | } |
| 2475 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2476 | int page_check_range(target_ulong start, target_ulong len, int flags) |
| 2477 | { |
| 2478 | PageDesc *p; |
| 2479 | target_ulong end; |
| 2480 | target_ulong addr; |
| 2481 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2482 | /* This function should never be called with addresses outside the |
| 2483 | guest address space. If this assert fires, it probably indicates |
| 2484 | a missing call to h2g_valid. */ |
Blue Swirl | 338e9e6 | 2010-03-13 09:48:08 +0000 | [diff] [blame] | 2485 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2486 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2487 | #endif |
| 2488 | |
Richard Henderson | 3e0650a | 2010-03-29 10:54:42 -0700 | [diff] [blame] | 2489 | if (len == 0) { |
| 2490 | return 0; |
| 2491 | } |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2492 | if (start + len - 1 < start) { |
| 2493 | /* We've wrapped around. */ |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2494 | return -1; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2495 | } |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2496 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2497 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
| 2498 | start = start & TARGET_PAGE_MASK; |
| 2499 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2500 | for (addr = start, len = end - start; |
| 2501 | len != 0; |
| 2502 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2503 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2504 | if( !p ) |
| 2505 | return -1; |
| 2506 | if( !(p->flags & PAGE_VALID) ) |
| 2507 | return -1; |
| 2508 | |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2509 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2510 | return -1; |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2511 | if (flags & PAGE_WRITE) { |
| 2512 | if (!(p->flags & PAGE_WRITE_ORG)) |
| 2513 | return -1; |
| 2514 | /* unprotect the page if it was put read-only because it |
| 2515 | contains translated code */ |
| 2516 | if (!(p->flags & PAGE_WRITE)) { |
| 2517 | if (!page_unprotect(addr, 0, NULL)) |
| 2518 | return -1; |
| 2519 | } |
| 2520 | return 0; |
| 2521 | } |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2522 | } |
| 2523 | return 0; |
| 2524 | } |
| 2525 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2526 | /* called from signal handler: invalidate the code and unprotect the |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2527 | page. Return TRUE if the fault was successfully handled. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2528 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2529 | { |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2530 | unsigned int prot; |
| 2531 | PageDesc *p; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2532 | target_ulong host_start, host_end, addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2533 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2534 | /* Technically this isn't safe inside a signal handler. However we |
| 2535 | know this only ever happens in a synchronous SEGV handler, so in |
| 2536 | practice it seems to be ok. */ |
| 2537 | mmap_lock(); |
| 2538 | |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2539 | p = page_find(address >> TARGET_PAGE_BITS); |
| 2540 | if (!p) { |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2541 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2542 | return 0; |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2543 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2544 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2545 | /* if the page was really writable, then we change its |
| 2546 | protection back to writable */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2547 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
| 2548 | host_start = address & qemu_host_page_mask; |
| 2549 | host_end = host_start + qemu_host_page_size; |
| 2550 | |
| 2551 | prot = 0; |
| 2552 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { |
| 2553 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2554 | p->flags |= PAGE_WRITE; |
| 2555 | prot |= p->flags; |
| 2556 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2557 | /* and since the content will be modified, we must invalidate |
| 2558 | the corresponding translated code. */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2559 | tb_invalidate_phys_page(addr, pc, puc); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2560 | #ifdef DEBUG_TB_CHECK |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2561 | tb_invalidate_check(addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2562 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2563 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2564 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
| 2565 | prot & PAGE_BITS); |
| 2566 | |
| 2567 | mmap_unlock(); |
| 2568 | return 1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2569 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2570 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2571 | return 0; |
| 2572 | } |
| 2573 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2574 | static inline void tlb_set_dirty(CPUState *env, |
| 2575 | unsigned long addr, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2576 | { |
| 2577 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2578 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 2579 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2580 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2581 | |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2582 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 2583 | typedef struct subpage_t { |
| 2584 | target_phys_addr_t base; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2585 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
| 2586 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2587 | } subpage_t; |
| 2588 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2589 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 2590 | ram_addr_t memory, ram_addr_t region_offset); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2591 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2592 | ram_addr_t orig_memory, |
| 2593 | ram_addr_t region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2594 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2595 | need_subpage) \ |
| 2596 | do { \ |
| 2597 | if (addr > start_addr) \ |
| 2598 | start_addr2 = 0; \ |
| 2599 | else { \ |
| 2600 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ |
| 2601 | if (start_addr2 > 0) \ |
| 2602 | need_subpage = 1; \ |
| 2603 | } \ |
| 2604 | \ |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2605 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2606 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
| 2607 | else { \ |
| 2608 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ |
| 2609 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ |
| 2610 | need_subpage = 1; \ |
| 2611 | } \ |
| 2612 | } while (0) |
| 2613 | |
Michael S. Tsirkin | 8f2498f | 2009-09-29 18:53:16 +0200 | [diff] [blame] | 2614 | /* register physical memory. |
| 2615 | For RAM, 'size' must be a multiple of the target page size. |
| 2616 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2617 | io memory page. The address used when calling the IO function is |
| 2618 | the offset from the start of the region, plus region_offset. Both |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2619 | start_addr and region_offset are rounded down to a page boundary |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2620 | before calculating this offset. This should not be a problem unless |
| 2621 | the low bits of start_addr and region_offset differ. */ |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2622 | void cpu_register_physical_memory_log(target_phys_addr_t start_addr, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2623 | ram_addr_t size, |
| 2624 | ram_addr_t phys_offset, |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2625 | ram_addr_t region_offset, |
| 2626 | bool log_dirty) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2627 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2628 | target_phys_addr_t addr, end_addr; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2629 | PhysPageDesc *p; |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2630 | CPUState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2631 | ram_addr_t orig_size = size; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2632 | subpage_t *subpage; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2633 | |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2634 | assert(size); |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2635 | cpu_notify_set_memory(start_addr, size, phys_offset, log_dirty); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2636 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2637 | if (phys_offset == IO_MEM_UNASSIGNED) { |
| 2638 | region_offset = start_addr; |
| 2639 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2640 | region_offset &= TARGET_PAGE_MASK; |
bellard | 5fd386f | 2004-05-23 21:11:22 +0000 | [diff] [blame] | 2641 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2642 | end_addr = start_addr + (target_phys_addr_t)size; |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2643 | |
| 2644 | addr = start_addr; |
| 2645 | do { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2646 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2647 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2648 | ram_addr_t orig_memory = p->phys_offset; |
| 2649 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2650 | int need_subpage = 0; |
| 2651 | |
| 2652 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, |
| 2653 | need_subpage); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2654 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2655 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
| 2656 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2657 | &p->phys_offset, orig_memory, |
| 2658 | p->region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2659 | } else { |
| 2660 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) |
| 2661 | >> IO_MEM_SHIFT]; |
| 2662 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2663 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
| 2664 | region_offset); |
| 2665 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2666 | } else { |
| 2667 | p->phys_offset = phys_offset; |
| 2668 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2669 | (phys_offset & IO_MEM_ROMD)) |
| 2670 | phys_offset += TARGET_PAGE_SIZE; |
| 2671 | } |
| 2672 | } else { |
| 2673 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2674 | p->phys_offset = phys_offset; |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2675 | p->region_offset = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2676 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2677 | (phys_offset & IO_MEM_ROMD)) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2678 | phys_offset += TARGET_PAGE_SIZE; |
pbrook | 0e8f096 | 2008-12-02 09:02:15 +0000 | [diff] [blame] | 2679 | } else { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2680 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2681 | int need_subpage = 0; |
| 2682 | |
| 2683 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, |
| 2684 | end_addr2, need_subpage); |
| 2685 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2686 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2687 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2688 | &p->phys_offset, IO_MEM_UNASSIGNED, |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2689 | addr & TARGET_PAGE_MASK); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2690 | subpage_register(subpage, start_addr2, end_addr2, |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2691 | phys_offset, region_offset); |
| 2692 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2693 | } |
| 2694 | } |
| 2695 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2696 | region_offset += TARGET_PAGE_SIZE; |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2697 | addr += TARGET_PAGE_SIZE; |
| 2698 | } while (addr != end_addr); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2699 | |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2700 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2701 | reset the modified entries */ |
| 2702 | /* XXX: slow ! */ |
| 2703 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 2704 | tlb_flush(env, 1); |
| 2705 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2706 | } |
| 2707 | |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2708 | /* XXX: temporary until new memory mapping API */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2709 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2710 | { |
| 2711 | PhysPageDesc *p; |
| 2712 | |
| 2713 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2714 | if (!p) |
| 2715 | return IO_MEM_UNASSIGNED; |
| 2716 | return p->phys_offset; |
| 2717 | } |
| 2718 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2719 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2720 | { |
| 2721 | if (kvm_enabled()) |
| 2722 | kvm_coalesce_mmio_region(addr, size); |
| 2723 | } |
| 2724 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2725 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2726 | { |
| 2727 | if (kvm_enabled()) |
| 2728 | kvm_uncoalesce_mmio_region(addr, size); |
| 2729 | } |
| 2730 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 2731 | void qemu_flush_coalesced_mmio_buffer(void) |
| 2732 | { |
| 2733 | if (kvm_enabled()) |
| 2734 | kvm_flush_coalesced_mmio_buffer(); |
| 2735 | } |
| 2736 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2737 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 2738 | |
| 2739 | #include <sys/vfs.h> |
| 2740 | |
| 2741 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 2742 | |
| 2743 | static long gethugepagesize(const char *path) |
| 2744 | { |
| 2745 | struct statfs fs; |
| 2746 | int ret; |
| 2747 | |
| 2748 | do { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2749 | ret = statfs(path, &fs); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2750 | } while (ret != 0 && errno == EINTR); |
| 2751 | |
| 2752 | if (ret != 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2753 | perror(path); |
| 2754 | return 0; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2755 | } |
| 2756 | |
| 2757 | if (fs.f_type != HUGETLBFS_MAGIC) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2758 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2759 | |
| 2760 | return fs.f_bsize; |
| 2761 | } |
| 2762 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2763 | static void *file_ram_alloc(RAMBlock *block, |
| 2764 | ram_addr_t memory, |
| 2765 | const char *path) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2766 | { |
| 2767 | char *filename; |
| 2768 | void *area; |
| 2769 | int fd; |
| 2770 | #ifdef MAP_POPULATE |
| 2771 | int flags; |
| 2772 | #endif |
| 2773 | unsigned long hpagesize; |
| 2774 | |
| 2775 | hpagesize = gethugepagesize(path); |
| 2776 | if (!hpagesize) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2777 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2778 | } |
| 2779 | |
| 2780 | if (memory < hpagesize) { |
| 2781 | return NULL; |
| 2782 | } |
| 2783 | |
| 2784 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
| 2785 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); |
| 2786 | return NULL; |
| 2787 | } |
| 2788 | |
| 2789 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2790 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2791 | } |
| 2792 | |
| 2793 | fd = mkstemp(filename); |
| 2794 | if (fd < 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2795 | perror("unable to create backing store for hugepages"); |
| 2796 | free(filename); |
| 2797 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2798 | } |
| 2799 | unlink(filename); |
| 2800 | free(filename); |
| 2801 | |
| 2802 | memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 2803 | |
| 2804 | /* |
| 2805 | * ftruncate is not supported by hugetlbfs in older |
| 2806 | * hosts, so don't bother bailing out on errors. |
| 2807 | * If anything goes wrong with it under other filesystems, |
| 2808 | * mmap will fail. |
| 2809 | */ |
| 2810 | if (ftruncate(fd, memory)) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2811 | perror("ftruncate"); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2812 | |
| 2813 | #ifdef MAP_POPULATE |
| 2814 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case |
| 2815 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED |
| 2816 | * to sidestep this quirk. |
| 2817 | */ |
| 2818 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; |
| 2819 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); |
| 2820 | #else |
| 2821 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
| 2822 | #endif |
| 2823 | if (area == MAP_FAILED) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2824 | perror("file_ram_alloc: can't mmap RAM pages"); |
| 2825 | close(fd); |
| 2826 | return (NULL); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2827 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2828 | block->fd = fd; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2829 | return area; |
| 2830 | } |
| 2831 | #endif |
| 2832 | |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2833 | static ram_addr_t find_ram_offset(ram_addr_t size) |
| 2834 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2835 | RAMBlock *block, *next_block; |
Blue Swirl | 09d7ae9 | 2010-07-07 19:37:53 +0000 | [diff] [blame] | 2836 | ram_addr_t offset = 0, mingap = ULONG_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2837 | |
| 2838 | if (QLIST_EMPTY(&ram_list.blocks)) |
| 2839 | return 0; |
| 2840 | |
| 2841 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2842 | ram_addr_t end, next = ULONG_MAX; |
| 2843 | |
| 2844 | end = block->offset + block->length; |
| 2845 | |
| 2846 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { |
| 2847 | if (next_block->offset >= end) { |
| 2848 | next = MIN(next, next_block->offset); |
| 2849 | } |
| 2850 | } |
| 2851 | if (next - end >= size && next - end < mingap) { |
| 2852 | offset = end; |
| 2853 | mingap = next - end; |
| 2854 | } |
| 2855 | } |
| 2856 | return offset; |
| 2857 | } |
| 2858 | |
| 2859 | static ram_addr_t last_ram_offset(void) |
| 2860 | { |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2861 | RAMBlock *block; |
| 2862 | ram_addr_t last = 0; |
| 2863 | |
| 2864 | QLIST_FOREACH(block, &ram_list.blocks, next) |
| 2865 | last = MAX(last, block->offset + block->length); |
| 2866 | |
| 2867 | return last; |
| 2868 | } |
| 2869 | |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2870 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2871 | ram_addr_t size, void *host) |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2872 | { |
| 2873 | RAMBlock *new_block, *block; |
| 2874 | |
| 2875 | size = TARGET_PAGE_ALIGN(size); |
| 2876 | new_block = qemu_mallocz(sizeof(*new_block)); |
| 2877 | |
| 2878 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { |
| 2879 | char *id = dev->parent_bus->info->get_dev_path(dev); |
| 2880 | if (id) { |
| 2881 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
| 2882 | qemu_free(id); |
| 2883 | } |
| 2884 | } |
| 2885 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); |
| 2886 | |
| 2887 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2888 | if (!strcmp(block->idstr, new_block->idstr)) { |
| 2889 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
| 2890 | new_block->idstr); |
| 2891 | abort(); |
| 2892 | } |
| 2893 | } |
| 2894 | |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 2895 | new_block->offset = find_ram_offset(size); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2896 | if (host) { |
| 2897 | new_block->host = host; |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2898 | new_block->flags |= RAM_PREALLOC_MASK; |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2899 | } else { |
| 2900 | if (mem_path) { |
| 2901 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2902 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
| 2903 | if (!new_block->host) { |
| 2904 | new_block->host = qemu_vmalloc(size); |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2905 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2906 | } |
| 2907 | #else |
| 2908 | fprintf(stderr, "-mem-path option unsupported\n"); |
| 2909 | exit(1); |
| 2910 | #endif |
| 2911 | } else { |
| 2912 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 2913 | /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */ |
| 2914 | new_block->host = mmap((void*)0x1000000, size, |
| 2915 | PROT_EXEC|PROT_READ|PROT_WRITE, |
| 2916 | MAP_SHARED | MAP_ANONYMOUS, -1, 0); |
| 2917 | #else |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 2918 | if (xen_mapcache_enabled()) { |
| 2919 | xen_ram_alloc(new_block->offset, size); |
| 2920 | } else { |
| 2921 | new_block->host = qemu_vmalloc(size); |
| 2922 | } |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2923 | #endif |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2924 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2925 | } |
| 2926 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2927 | new_block->length = size; |
| 2928 | |
| 2929 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
| 2930 | |
| 2931 | ram_list.phys_dirty = qemu_realloc(ram_list.phys_dirty, |
| 2932 | last_ram_offset() >> TARGET_PAGE_BITS); |
| 2933 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
| 2934 | 0xff, size >> TARGET_PAGE_BITS); |
| 2935 | |
| 2936 | if (kvm_enabled()) |
| 2937 | kvm_setup_guest_memory(new_block->host, size); |
| 2938 | |
| 2939 | return new_block->offset; |
| 2940 | } |
| 2941 | |
Alex Williamson | 1724f04 | 2010-06-25 11:09:35 -0600 | [diff] [blame] | 2942 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2943 | { |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2944 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2945 | } |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2946 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2947 | void qemu_ram_free(ram_addr_t addr) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2948 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2949 | RAMBlock *block; |
| 2950 | |
| 2951 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2952 | if (addr == block->offset) { |
| 2953 | QLIST_REMOVE(block, next); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2954 | if (block->flags & RAM_PREALLOC_MASK) { |
| 2955 | ; |
| 2956 | } else if (mem_path) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2957 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2958 | if (block->fd) { |
| 2959 | munmap(block->host, block->length); |
| 2960 | close(block->fd); |
| 2961 | } else { |
| 2962 | qemu_vfree(block->host); |
| 2963 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 2964 | #else |
| 2965 | abort(); |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2966 | #endif |
| 2967 | } else { |
| 2968 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 2969 | munmap(block->host, block->length); |
| 2970 | #else |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 2971 | if (xen_mapcache_enabled()) { |
| 2972 | qemu_invalidate_entry(block->host); |
| 2973 | } else { |
| 2974 | qemu_vfree(block->host); |
| 2975 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2976 | #endif |
| 2977 | } |
| 2978 | qemu_free(block); |
| 2979 | return; |
| 2980 | } |
| 2981 | } |
| 2982 | |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 2983 | } |
| 2984 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2985 | #ifndef _WIN32 |
| 2986 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) |
| 2987 | { |
| 2988 | RAMBlock *block; |
| 2989 | ram_addr_t offset; |
| 2990 | int flags; |
| 2991 | void *area, *vaddr; |
| 2992 | |
| 2993 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2994 | offset = addr - block->offset; |
| 2995 | if (offset < block->length) { |
| 2996 | vaddr = block->host + offset; |
| 2997 | if (block->flags & RAM_PREALLOC_MASK) { |
| 2998 | ; |
| 2999 | } else { |
| 3000 | flags = MAP_FIXED; |
| 3001 | munmap(vaddr, length); |
| 3002 | if (mem_path) { |
| 3003 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 3004 | if (block->fd) { |
| 3005 | #ifdef MAP_POPULATE |
| 3006 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : |
| 3007 | MAP_PRIVATE; |
| 3008 | #else |
| 3009 | flags |= MAP_PRIVATE; |
| 3010 | #endif |
| 3011 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3012 | flags, block->fd, offset); |
| 3013 | } else { |
| 3014 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3015 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3016 | flags, -1, 0); |
| 3017 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 3018 | #else |
| 3019 | abort(); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3020 | #endif |
| 3021 | } else { |
| 3022 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 3023 | flags |= MAP_SHARED | MAP_ANONYMOUS; |
| 3024 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, |
| 3025 | flags, -1, 0); |
| 3026 | #else |
| 3027 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3028 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3029 | flags, -1, 0); |
| 3030 | #endif |
| 3031 | } |
| 3032 | if (area != vaddr) { |
| 3033 | fprintf(stderr, "Could not remap addr: %lx@%lx\n", |
| 3034 | length, addr); |
| 3035 | exit(1); |
| 3036 | } |
| 3037 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); |
| 3038 | } |
| 3039 | return; |
| 3040 | } |
| 3041 | } |
| 3042 | } |
| 3043 | #endif /* !_WIN32 */ |
| 3044 | |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3045 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3046 | With the exception of the softmmu code in this file, this should |
| 3047 | only be used for local memory (e.g. video ram) that the device owns, |
| 3048 | and knows it isn't going to access beyond the end of the block. |
| 3049 | |
| 3050 | It should not be used for general purpose DMA. |
| 3051 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. |
| 3052 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3053 | void *qemu_get_ram_ptr(ram_addr_t addr) |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3054 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3055 | RAMBlock *block; |
| 3056 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3057 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3058 | if (addr - block->offset < block->length) { |
Vincent Palatin | 7d82af3 | 2011-03-10 15:47:46 -0500 | [diff] [blame] | 3059 | /* Move this entry to to start of the list. */ |
| 3060 | if (block != QLIST_FIRST(&ram_list.blocks)) { |
| 3061 | QLIST_REMOVE(block, next); |
| 3062 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); |
| 3063 | } |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 3064 | if (xen_mapcache_enabled()) { |
| 3065 | /* We need to check if the requested address is in the RAM |
| 3066 | * because we don't want to map the entire memory in QEMU. |
| 3067 | */ |
| 3068 | if (block->offset == 0) { |
| 3069 | return qemu_map_cache(addr, 0, 1); |
| 3070 | } else if (block->host == NULL) { |
| 3071 | block->host = xen_map_block(block->offset, block->length); |
| 3072 | } |
| 3073 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3074 | return block->host + (addr - block->offset); |
| 3075 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3076 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3077 | |
| 3078 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3079 | abort(); |
| 3080 | |
| 3081 | return NULL; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3082 | } |
| 3083 | |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3084 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
| 3085 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. |
| 3086 | */ |
| 3087 | void *qemu_safe_ram_ptr(ram_addr_t addr) |
| 3088 | { |
| 3089 | RAMBlock *block; |
| 3090 | |
| 3091 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3092 | if (addr - block->offset < block->length) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 3093 | if (xen_mapcache_enabled()) { |
| 3094 | /* We need to check if the requested address is in the RAM |
| 3095 | * because we don't want to map the entire memory in QEMU. |
| 3096 | */ |
| 3097 | if (block->offset == 0) { |
| 3098 | return qemu_map_cache(addr, 0, 1); |
| 3099 | } else if (block->host == NULL) { |
| 3100 | block->host = xen_map_block(block->offset, block->length); |
| 3101 | } |
| 3102 | } |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3103 | return block->host + (addr - block->offset); |
| 3104 | } |
| 3105 | } |
| 3106 | |
| 3107 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3108 | abort(); |
| 3109 | |
| 3110 | return NULL; |
| 3111 | } |
| 3112 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3113 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3114 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3115 | RAMBlock *block; |
| 3116 | uint8_t *host = ptr; |
| 3117 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3118 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 3119 | /* This case append when the block is not mapped. */ |
| 3120 | if (block->host == NULL) { |
| 3121 | continue; |
| 3122 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3123 | if (host - block->host < block->length) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3124 | *ram_addr = block->offset + (host - block->host); |
| 3125 | return 0; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3126 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3127 | } |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame^] | 3128 | |
| 3129 | if (xen_mapcache_enabled()) { |
| 3130 | *ram_addr = qemu_ram_addr_from_mapcache(ptr); |
| 3131 | return 0; |
| 3132 | } |
| 3133 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3134 | return -1; |
| 3135 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3136 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3137 | /* Some of the softmmu routines need to translate from a host pointer |
| 3138 | (typically a TLB entry) back to a ram offset. */ |
| 3139 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) |
| 3140 | { |
| 3141 | ram_addr_t ram_addr; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3142 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3143 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
| 3144 | fprintf(stderr, "Bad ram pointer %p\n", ptr); |
| 3145 | abort(); |
| 3146 | } |
| 3147 | return ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3148 | } |
| 3149 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3150 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3151 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3152 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 3153 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3154 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3155 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3156 | do_unassigned_access(addr, 0, 0, 0, 1); |
| 3157 | #endif |
| 3158 | return 0; |
| 3159 | } |
| 3160 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3161 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3162 | { |
| 3163 | #ifdef DEBUG_UNASSIGNED |
| 3164 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 3165 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3166 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3167 | do_unassigned_access(addr, 0, 0, 0, 2); |
| 3168 | #endif |
| 3169 | return 0; |
| 3170 | } |
| 3171 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3172 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3173 | { |
| 3174 | #ifdef DEBUG_UNASSIGNED |
| 3175 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 3176 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3177 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3178 | do_unassigned_access(addr, 0, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 3179 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3180 | return 0; |
| 3181 | } |
| 3182 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3183 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3184 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3185 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 3186 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3187 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3188 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3189 | do_unassigned_access(addr, 1, 0, 0, 1); |
| 3190 | #endif |
| 3191 | } |
| 3192 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3193 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3194 | { |
| 3195 | #ifdef DEBUG_UNASSIGNED |
| 3196 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3197 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3198 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3199 | do_unassigned_access(addr, 1, 0, 0, 2); |
| 3200 | #endif |
| 3201 | } |
| 3202 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3203 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3204 | { |
| 3205 | #ifdef DEBUG_UNASSIGNED |
| 3206 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3207 | #endif |
Edgar E. Iglesias | faed1c2 | 2009-09-03 13:25:09 +0200 | [diff] [blame] | 3208 | #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3209 | do_unassigned_access(addr, 1, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 3210 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3211 | } |
| 3212 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3213 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3214 | unassigned_mem_readb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3215 | unassigned_mem_readw, |
| 3216 | unassigned_mem_readl, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3217 | }; |
| 3218 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3219 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3220 | unassigned_mem_writeb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3221 | unassigned_mem_writew, |
| 3222 | unassigned_mem_writel, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3223 | }; |
| 3224 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3225 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3226 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3227 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3228 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3229 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3230 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3231 | #if !defined(CONFIG_USER_ONLY) |
| 3232 | tb_invalidate_phys_page_fast(ram_addr, 1); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3233 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3234 | #endif |
| 3235 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3236 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3237 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3238 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3239 | /* we remove the notdirty callback only if the code has been |
| 3240 | flushed */ |
| 3241 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3242 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3243 | } |
| 3244 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3245 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3246 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3247 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3248 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3249 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3250 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3251 | #if !defined(CONFIG_USER_ONLY) |
| 3252 | tb_invalidate_phys_page_fast(ram_addr, 2); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3253 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3254 | #endif |
| 3255 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3256 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3257 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3258 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3259 | /* we remove the notdirty callback only if the code has been |
| 3260 | flushed */ |
| 3261 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3262 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3263 | } |
| 3264 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3265 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3266 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3267 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3268 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3269 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3270 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3271 | #if !defined(CONFIG_USER_ONLY) |
| 3272 | tb_invalidate_phys_page_fast(ram_addr, 4); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3273 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3274 | #endif |
| 3275 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3276 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3277 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3278 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3279 | /* we remove the notdirty callback only if the code has been |
| 3280 | flushed */ |
| 3281 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3282 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3283 | } |
| 3284 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3285 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3286 | NULL, /* never used */ |
| 3287 | NULL, /* never used */ |
| 3288 | NULL, /* never used */ |
| 3289 | }; |
| 3290 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3291 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3292 | notdirty_mem_writeb, |
| 3293 | notdirty_mem_writew, |
| 3294 | notdirty_mem_writel, |
| 3295 | }; |
| 3296 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3297 | /* Generate a debug exception if a watchpoint has been hit. */ |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3298 | static void check_watchpoint(int offset, int len_mask, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3299 | { |
| 3300 | CPUState *env = cpu_single_env; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3301 | target_ulong pc, cs_base; |
| 3302 | TranslationBlock *tb; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3303 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 3304 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3305 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3306 | |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3307 | if (env->watchpoint_hit) { |
| 3308 | /* We re-entered the check after replacing the TB. Now raise |
| 3309 | * the debug interrupt so that is will trigger after the |
| 3310 | * current instruction. */ |
| 3311 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); |
| 3312 | return; |
| 3313 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3314 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3315 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3316 | if ((vaddr == (wp->vaddr & len_mask) || |
| 3317 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3318 | wp->flags |= BP_WATCHPOINT_HIT; |
| 3319 | if (!env->watchpoint_hit) { |
| 3320 | env->watchpoint_hit = wp; |
| 3321 | tb = tb_find_pc(env->mem_io_pc); |
| 3322 | if (!tb) { |
| 3323 | cpu_abort(env, "check_watchpoint: could not find TB for " |
| 3324 | "pc=%p", (void *)env->mem_io_pc); |
| 3325 | } |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 3326 | cpu_restore_state(tb, env, env->mem_io_pc); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3327 | tb_phys_invalidate(tb, -1); |
| 3328 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
| 3329 | env->exception_index = EXCP_DEBUG; |
| 3330 | } else { |
| 3331 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 3332 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); |
| 3333 | } |
| 3334 | cpu_resume_from_signal(env, NULL); |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3335 | } |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3336 | } else { |
| 3337 | wp->flags &= ~BP_WATCHPOINT_HIT; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3338 | } |
| 3339 | } |
| 3340 | } |
| 3341 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3342 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 3343 | so these check for a hit then pass through to the normal out-of-line |
| 3344 | phys routines. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3345 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3346 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3347 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3348 | return ldub_phys(addr); |
| 3349 | } |
| 3350 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3351 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3352 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3353 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3354 | return lduw_phys(addr); |
| 3355 | } |
| 3356 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3357 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3358 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3359 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3360 | return ldl_phys(addr); |
| 3361 | } |
| 3362 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3363 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3364 | uint32_t val) |
| 3365 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3366 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3367 | stb_phys(addr, val); |
| 3368 | } |
| 3369 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3370 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3371 | uint32_t val) |
| 3372 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3373 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3374 | stw_phys(addr, val); |
| 3375 | } |
| 3376 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3377 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3378 | uint32_t val) |
| 3379 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3380 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3381 | stl_phys(addr, val); |
| 3382 | } |
| 3383 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3384 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3385 | watch_mem_readb, |
| 3386 | watch_mem_readw, |
| 3387 | watch_mem_readl, |
| 3388 | }; |
| 3389 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3390 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3391 | watch_mem_writeb, |
| 3392 | watch_mem_writew, |
| 3393 | watch_mem_writel, |
| 3394 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3395 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3396 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
| 3397 | target_phys_addr_t addr, |
| 3398 | unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3399 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3400 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3401 | #if defined(DEBUG_SUBPAGE) |
| 3402 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, |
| 3403 | mmio, len, addr, idx); |
| 3404 | #endif |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3405 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3406 | addr += mmio->region_offset[idx]; |
| 3407 | idx = mmio->sub_io_index[idx]; |
| 3408 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3409 | } |
| 3410 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3411 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3412 | uint32_t value, unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3413 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3414 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3415 | #if defined(DEBUG_SUBPAGE) |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3416 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
| 3417 | __func__, mmio, len, addr, idx, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3418 | #endif |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3419 | |
| 3420 | addr += mmio->region_offset[idx]; |
| 3421 | idx = mmio->sub_io_index[idx]; |
| 3422 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3423 | } |
| 3424 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3425 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3426 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3427 | return subpage_readlen(opaque, addr, 0); |
| 3428 | } |
| 3429 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3430 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3431 | uint32_t value) |
| 3432 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3433 | subpage_writelen(opaque, addr, value, 0); |
| 3434 | } |
| 3435 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3436 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3437 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3438 | return subpage_readlen(opaque, addr, 1); |
| 3439 | } |
| 3440 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3441 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3442 | uint32_t value) |
| 3443 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3444 | subpage_writelen(opaque, addr, value, 1); |
| 3445 | } |
| 3446 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3447 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3448 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3449 | return subpage_readlen(opaque, addr, 2); |
| 3450 | } |
| 3451 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3452 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
| 3453 | uint32_t value) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3454 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3455 | subpage_writelen(opaque, addr, value, 2); |
| 3456 | } |
| 3457 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3458 | static CPUReadMemoryFunc * const subpage_read[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3459 | &subpage_readb, |
| 3460 | &subpage_readw, |
| 3461 | &subpage_readl, |
| 3462 | }; |
| 3463 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3464 | static CPUWriteMemoryFunc * const subpage_write[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3465 | &subpage_writeb, |
| 3466 | &subpage_writew, |
| 3467 | &subpage_writel, |
| 3468 | }; |
| 3469 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3470 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 3471 | ram_addr_t memory, ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3472 | { |
| 3473 | int idx, eidx; |
| 3474 | |
| 3475 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 3476 | return -1; |
| 3477 | idx = SUBPAGE_IDX(start); |
| 3478 | eidx = SUBPAGE_IDX(end); |
| 3479 | #if defined(DEBUG_SUBPAGE) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 3480 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3481 | mmio, start, end, idx, eidx, memory); |
| 3482 | #endif |
Gleb Natapov | 95c318f | 2010-07-29 10:41:45 +0300 | [diff] [blame] | 3483 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 3484 | memory = IO_MEM_UNASSIGNED; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3485 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3486 | for (; idx <= eidx; idx++) { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3487 | mmio->sub_io_index[idx] = memory; |
| 3488 | mmio->region_offset[idx] = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3489 | } |
| 3490 | |
| 3491 | return 0; |
| 3492 | } |
| 3493 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3494 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 3495 | ram_addr_t orig_memory, |
| 3496 | ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3497 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3498 | subpage_t *mmio; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3499 | int subpage_memory; |
| 3500 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3501 | mmio = qemu_mallocz(sizeof(subpage_t)); |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3502 | |
| 3503 | mmio->base = base; |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3504 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, |
| 3505 | DEVICE_NATIVE_ENDIAN); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3506 | #if defined(DEBUG_SUBPAGE) |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3507 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
| 3508 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3509 | #endif |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3510 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3511 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3512 | |
| 3513 | return mmio; |
| 3514 | } |
| 3515 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3516 | static int get_free_io_mem_idx(void) |
| 3517 | { |
| 3518 | int i; |
| 3519 | |
| 3520 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) |
| 3521 | if (!io_mem_used[i]) { |
| 3522 | io_mem_used[i] = 1; |
| 3523 | return i; |
| 3524 | } |
Riku Voipio | c6703b4 | 2009-12-03 15:56:05 +0200 | [diff] [blame] | 3525 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3526 | return -1; |
| 3527 | } |
| 3528 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3529 | /* |
| 3530 | * Usually, devices operate in little endian mode. There are devices out |
| 3531 | * there that operate in big endian too. Each device gets byte swapped |
| 3532 | * mmio if plugged onto a CPU that does the other endianness. |
| 3533 | * |
| 3534 | * CPU Device swap? |
| 3535 | * |
| 3536 | * little little no |
| 3537 | * little big yes |
| 3538 | * big little yes |
| 3539 | * big big no |
| 3540 | */ |
| 3541 | |
| 3542 | typedef struct SwapEndianContainer { |
| 3543 | CPUReadMemoryFunc *read[3]; |
| 3544 | CPUWriteMemoryFunc *write[3]; |
| 3545 | void *opaque; |
| 3546 | } SwapEndianContainer; |
| 3547 | |
| 3548 | static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr) |
| 3549 | { |
| 3550 | uint32_t val; |
| 3551 | SwapEndianContainer *c = opaque; |
| 3552 | val = c->read[0](c->opaque, addr); |
| 3553 | return val; |
| 3554 | } |
| 3555 | |
| 3556 | static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr) |
| 3557 | { |
| 3558 | uint32_t val; |
| 3559 | SwapEndianContainer *c = opaque; |
| 3560 | val = bswap16(c->read[1](c->opaque, addr)); |
| 3561 | return val; |
| 3562 | } |
| 3563 | |
| 3564 | static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr) |
| 3565 | { |
| 3566 | uint32_t val; |
| 3567 | SwapEndianContainer *c = opaque; |
| 3568 | val = bswap32(c->read[2](c->opaque, addr)); |
| 3569 | return val; |
| 3570 | } |
| 3571 | |
| 3572 | static CPUReadMemoryFunc * const swapendian_readfn[3]={ |
| 3573 | swapendian_mem_readb, |
| 3574 | swapendian_mem_readw, |
| 3575 | swapendian_mem_readl |
| 3576 | }; |
| 3577 | |
| 3578 | static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr, |
| 3579 | uint32_t val) |
| 3580 | { |
| 3581 | SwapEndianContainer *c = opaque; |
| 3582 | c->write[0](c->opaque, addr, val); |
| 3583 | } |
| 3584 | |
| 3585 | static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr, |
| 3586 | uint32_t val) |
| 3587 | { |
| 3588 | SwapEndianContainer *c = opaque; |
| 3589 | c->write[1](c->opaque, addr, bswap16(val)); |
| 3590 | } |
| 3591 | |
| 3592 | static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr, |
| 3593 | uint32_t val) |
| 3594 | { |
| 3595 | SwapEndianContainer *c = opaque; |
| 3596 | c->write[2](c->opaque, addr, bswap32(val)); |
| 3597 | } |
| 3598 | |
| 3599 | static CPUWriteMemoryFunc * const swapendian_writefn[3]={ |
| 3600 | swapendian_mem_writeb, |
| 3601 | swapendian_mem_writew, |
| 3602 | swapendian_mem_writel |
| 3603 | }; |
| 3604 | |
| 3605 | static void swapendian_init(int io_index) |
| 3606 | { |
| 3607 | SwapEndianContainer *c = qemu_malloc(sizeof(SwapEndianContainer)); |
| 3608 | int i; |
| 3609 | |
| 3610 | /* Swap mmio for big endian targets */ |
| 3611 | c->opaque = io_mem_opaque[io_index]; |
| 3612 | for (i = 0; i < 3; i++) { |
| 3613 | c->read[i] = io_mem_read[io_index][i]; |
| 3614 | c->write[i] = io_mem_write[io_index][i]; |
| 3615 | |
| 3616 | io_mem_read[io_index][i] = swapendian_readfn[i]; |
| 3617 | io_mem_write[io_index][i] = swapendian_writefn[i]; |
| 3618 | } |
| 3619 | io_mem_opaque[io_index] = c; |
| 3620 | } |
| 3621 | |
| 3622 | static void swapendian_del(int io_index) |
| 3623 | { |
| 3624 | if (io_mem_read[io_index][0] == swapendian_readfn[0]) { |
| 3625 | qemu_free(io_mem_opaque[io_index]); |
| 3626 | } |
| 3627 | } |
| 3628 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3629 | /* mem_read and mem_write are arrays of functions containing the |
| 3630 | function to access byte (index 0), word (index 1) and dword (index |
Paul Brook | 0b4e6e3 | 2009-04-30 18:37:55 +0100 | [diff] [blame] | 3631 | 2). Functions can be omitted with a NULL function pointer. |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 3632 | If io_index is non zero, the corresponding io zone is |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 3633 | modified. If it is zero, a new io zone is allocated. The return |
| 3634 | value can be used with cpu_register_physical_memory(). (-1) is |
| 3635 | returned if error. */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3636 | static int cpu_register_io_memory_fixed(int io_index, |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3637 | CPUReadMemoryFunc * const *mem_read, |
| 3638 | CPUWriteMemoryFunc * const *mem_write, |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3639 | void *opaque, enum device_endian endian) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3640 | { |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3641 | int i; |
| 3642 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3643 | if (io_index <= 0) { |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3644 | io_index = get_free_io_mem_idx(); |
| 3645 | if (io_index == -1) |
| 3646 | return io_index; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3647 | } else { |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3648 | io_index >>= IO_MEM_SHIFT; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3649 | if (io_index >= IO_MEM_NB_ENTRIES) |
| 3650 | return -1; |
| 3651 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3652 | |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3653 | for (i = 0; i < 3; ++i) { |
| 3654 | io_mem_read[io_index][i] |
| 3655 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); |
| 3656 | } |
| 3657 | for (i = 0; i < 3; ++i) { |
| 3658 | io_mem_write[io_index][i] |
| 3659 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); |
| 3660 | } |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 3661 | io_mem_opaque[io_index] = opaque; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3662 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3663 | switch (endian) { |
| 3664 | case DEVICE_BIG_ENDIAN: |
| 3665 | #ifndef TARGET_WORDS_BIGENDIAN |
| 3666 | swapendian_init(io_index); |
| 3667 | #endif |
| 3668 | break; |
| 3669 | case DEVICE_LITTLE_ENDIAN: |
| 3670 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3671 | swapendian_init(io_index); |
| 3672 | #endif |
| 3673 | break; |
| 3674 | case DEVICE_NATIVE_ENDIAN: |
| 3675 | default: |
| 3676 | break; |
| 3677 | } |
| 3678 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3679 | return (io_index << IO_MEM_SHIFT); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3680 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3681 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3682 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
| 3683 | CPUWriteMemoryFunc * const *mem_write, |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3684 | void *opaque, enum device_endian endian) |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3685 | { |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3686 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3687 | } |
| 3688 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3689 | void cpu_unregister_io_memory(int io_table_address) |
| 3690 | { |
| 3691 | int i; |
| 3692 | int io_index = io_table_address >> IO_MEM_SHIFT; |
| 3693 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3694 | swapendian_del(io_index); |
| 3695 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3696 | for (i=0;i < 3; i++) { |
| 3697 | io_mem_read[io_index][i] = unassigned_mem_read[i]; |
| 3698 | io_mem_write[io_index][i] = unassigned_mem_write[i]; |
| 3699 | } |
| 3700 | io_mem_opaque[io_index] = NULL; |
| 3701 | io_mem_used[io_index] = 0; |
| 3702 | } |
| 3703 | |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3704 | static void io_mem_init(void) |
| 3705 | { |
| 3706 | int i; |
| 3707 | |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3708 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, |
| 3709 | unassigned_mem_write, NULL, |
| 3710 | DEVICE_NATIVE_ENDIAN); |
| 3711 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, |
| 3712 | unassigned_mem_write, NULL, |
| 3713 | DEVICE_NATIVE_ENDIAN); |
| 3714 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, |
| 3715 | notdirty_mem_write, NULL, |
| 3716 | DEVICE_NATIVE_ENDIAN); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3717 | for (i=0; i<5; i++) |
| 3718 | io_mem_used[i] = 1; |
| 3719 | |
| 3720 | io_mem_watch = cpu_register_io_memory(watch_mem_read, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3721 | watch_mem_write, NULL, |
| 3722 | DEVICE_NATIVE_ENDIAN); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3723 | } |
| 3724 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 3725 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 3726 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3727 | /* physical memory access (slow version, mainly for debug) */ |
| 3728 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3729 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 3730 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3731 | { |
| 3732 | int l, flags; |
| 3733 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 3734 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3735 | |
| 3736 | while (len > 0) { |
| 3737 | page = addr & TARGET_PAGE_MASK; |
| 3738 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3739 | if (l > len) |
| 3740 | l = len; |
| 3741 | flags = page_get_flags(page); |
| 3742 | if (!(flags & PAGE_VALID)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3743 | return -1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3744 | if (is_write) { |
| 3745 | if (!(flags & PAGE_WRITE)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3746 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3747 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3748 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3749 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3750 | memcpy(p, buf, l); |
| 3751 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3752 | } else { |
| 3753 | if (!(flags & PAGE_READ)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3754 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3755 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3756 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3757 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3758 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 3759 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3760 | } |
| 3761 | len -= l; |
| 3762 | buf += l; |
| 3763 | addr += l; |
| 3764 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3765 | return 0; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3766 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3767 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3768 | #else |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3769 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3770 | int len, int is_write) |
| 3771 | { |
| 3772 | int l, io_index; |
| 3773 | uint8_t *ptr; |
| 3774 | uint32_t val; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3775 | target_phys_addr_t page; |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 3776 | unsigned long pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3777 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3778 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3779 | while (len > 0) { |
| 3780 | page = addr & TARGET_PAGE_MASK; |
| 3781 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3782 | if (l > len) |
| 3783 | l = len; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3784 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3785 | if (!p) { |
| 3786 | pd = IO_MEM_UNASSIGNED; |
| 3787 | } else { |
| 3788 | pd = p->phys_offset; |
| 3789 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3790 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3791 | if (is_write) { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3792 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3793 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3794 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3795 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3796 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 3797 | /* XXX: could force cpu_single_env to NULL to avoid |
| 3798 | potential bugs */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3799 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3800 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3801 | val = ldl_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3802 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3803 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3804 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3805 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3806 | val = lduw_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3807 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3808 | l = 2; |
| 3809 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3810 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3811 | val = ldub_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3812 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3813 | l = 1; |
| 3814 | } |
| 3815 | } else { |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3816 | unsigned long addr1; |
| 3817 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3818 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3819 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3820 | memcpy(ptr, buf, l); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3821 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3822 | /* invalidate code */ |
| 3823 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 3824 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3825 | cpu_physical_memory_set_dirty_flags( |
| 3826 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3827 | } |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3828 | } |
| 3829 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3830 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3831 | !(pd & IO_MEM_ROMD)) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3832 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3833 | /* I/O case */ |
| 3834 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3835 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3836 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 3837 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3838 | /* 32 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3839 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3840 | stl_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3841 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3842 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3843 | /* 16 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3844 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3845 | stw_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3846 | l = 2; |
| 3847 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3848 | /* 8 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3849 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3850 | stb_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3851 | l = 1; |
| 3852 | } |
| 3853 | } else { |
| 3854 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3855 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3856 | (addr & ~TARGET_PAGE_MASK); |
| 3857 | memcpy(buf, ptr, l); |
| 3858 | } |
| 3859 | } |
| 3860 | len -= l; |
| 3861 | buf += l; |
| 3862 | addr += l; |
| 3863 | } |
| 3864 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3865 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3866 | /* used for ROM loading : can write in RAM and ROM */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3867 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3868 | const uint8_t *buf, int len) |
| 3869 | { |
| 3870 | int l; |
| 3871 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3872 | target_phys_addr_t page; |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3873 | unsigned long pd; |
| 3874 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3875 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3876 | while (len > 0) { |
| 3877 | page = addr & TARGET_PAGE_MASK; |
| 3878 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3879 | if (l > len) |
| 3880 | l = len; |
| 3881 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 3882 | if (!p) { |
| 3883 | pd = IO_MEM_UNASSIGNED; |
| 3884 | } else { |
| 3885 | pd = p->phys_offset; |
| 3886 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3887 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3888 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3889 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
| 3890 | !(pd & IO_MEM_ROMD)) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3891 | /* do nothing */ |
| 3892 | } else { |
| 3893 | unsigned long addr1; |
| 3894 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 3895 | /* ROM/RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3896 | ptr = qemu_get_ram_ptr(addr1); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3897 | memcpy(ptr, buf, l); |
| 3898 | } |
| 3899 | len -= l; |
| 3900 | buf += l; |
| 3901 | addr += l; |
| 3902 | } |
| 3903 | } |
| 3904 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3905 | typedef struct { |
| 3906 | void *buffer; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3907 | target_phys_addr_t addr; |
| 3908 | target_phys_addr_t len; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3909 | } BounceBuffer; |
| 3910 | |
| 3911 | static BounceBuffer bounce; |
| 3912 | |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3913 | typedef struct MapClient { |
| 3914 | void *opaque; |
| 3915 | void (*callback)(void *opaque); |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3916 | QLIST_ENTRY(MapClient) link; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3917 | } MapClient; |
| 3918 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3919 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
| 3920 | = QLIST_HEAD_INITIALIZER(map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3921 | |
| 3922 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 3923 | { |
| 3924 | MapClient *client = qemu_malloc(sizeof(*client)); |
| 3925 | |
| 3926 | client->opaque = opaque; |
| 3927 | client->callback = callback; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3928 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3929 | return client; |
| 3930 | } |
| 3931 | |
| 3932 | void cpu_unregister_map_client(void *_client) |
| 3933 | { |
| 3934 | MapClient *client = (MapClient *)_client; |
| 3935 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3936 | QLIST_REMOVE(client, link); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 3937 | qemu_free(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3938 | } |
| 3939 | |
| 3940 | static void cpu_notify_map_clients(void) |
| 3941 | { |
| 3942 | MapClient *client; |
| 3943 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3944 | while (!QLIST_EMPTY(&map_client_list)) { |
| 3945 | client = QLIST_FIRST(&map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3946 | client->callback(client->opaque); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 3947 | cpu_unregister_map_client(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3948 | } |
| 3949 | } |
| 3950 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3951 | /* Map a physical memory region into a host virtual address. |
| 3952 | * May map a subset of the requested range, given by and returned in *plen. |
| 3953 | * May return NULL if resources needed to perform the mapping are exhausted. |
| 3954 | * Use only for reads OR writes - not for read-modify-write operations. |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 3955 | * Use cpu_register_map_client() to know when retrying the map operation is |
| 3956 | * likely to succeed. |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3957 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3958 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
| 3959 | target_phys_addr_t *plen, |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3960 | int is_write) |
| 3961 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3962 | target_phys_addr_t len = *plen; |
| 3963 | target_phys_addr_t done = 0; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3964 | int l; |
| 3965 | uint8_t *ret = NULL; |
| 3966 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3967 | target_phys_addr_t page; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3968 | unsigned long pd; |
| 3969 | PhysPageDesc *p; |
| 3970 | unsigned long addr1; |
| 3971 | |
| 3972 | while (len > 0) { |
| 3973 | page = addr & TARGET_PAGE_MASK; |
| 3974 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3975 | if (l > len) |
| 3976 | l = len; |
| 3977 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 3978 | if (!p) { |
| 3979 | pd = IO_MEM_UNASSIGNED; |
| 3980 | } else { |
| 3981 | pd = p->phys_offset; |
| 3982 | } |
| 3983 | |
| 3984 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 3985 | if (done || bounce.buffer) { |
| 3986 | break; |
| 3987 | } |
| 3988 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); |
| 3989 | bounce.addr = addr; |
| 3990 | bounce.len = l; |
| 3991 | if (!is_write) { |
Stefan Weil | 54f7b4a | 2011-04-10 18:23:39 +0200 | [diff] [blame] | 3992 | cpu_physical_memory_read(addr, bounce.buffer, l); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3993 | } |
| 3994 | ptr = bounce.buffer; |
| 3995 | } else { |
| 3996 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3997 | ptr = qemu_get_ram_ptr(addr1); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 3998 | } |
| 3999 | if (!done) { |
| 4000 | ret = ptr; |
| 4001 | } else if (ret + done != ptr) { |
| 4002 | break; |
| 4003 | } |
| 4004 | |
| 4005 | len -= l; |
| 4006 | addr += l; |
| 4007 | done += l; |
| 4008 | } |
| 4009 | *plen = done; |
| 4010 | return ret; |
| 4011 | } |
| 4012 | |
| 4013 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). |
| 4014 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
| 4015 | * the amount of memory that was actually read or written by the caller. |
| 4016 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4017 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
| 4018 | int is_write, target_phys_addr_t access_len) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4019 | { |
| 4020 | if (buffer != bounce.buffer) { |
| 4021 | if (is_write) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 4022 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4023 | while (access_len) { |
| 4024 | unsigned l; |
| 4025 | l = TARGET_PAGE_SIZE; |
| 4026 | if (l > access_len) |
| 4027 | l = access_len; |
| 4028 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4029 | /* invalidate code */ |
| 4030 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 4031 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4032 | cpu_physical_memory_set_dirty_flags( |
| 4033 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4034 | } |
| 4035 | addr1 += l; |
| 4036 | access_len -= l; |
| 4037 | } |
| 4038 | } |
| 4039 | return; |
| 4040 | } |
| 4041 | if (is_write) { |
| 4042 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); |
| 4043 | } |
Herve Poussineau | f8a8324 | 2010-01-24 21:23:56 +0000 | [diff] [blame] | 4044 | qemu_vfree(bounce.buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4045 | bounce.buffer = NULL; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4046 | cpu_notify_map_clients(); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4047 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4048 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4049 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4050 | uint32_t ldl_phys(target_phys_addr_t addr) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4051 | { |
| 4052 | int io_index; |
| 4053 | uint8_t *ptr; |
| 4054 | uint32_t val; |
| 4055 | unsigned long pd; |
| 4056 | PhysPageDesc *p; |
| 4057 | |
| 4058 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4059 | if (!p) { |
| 4060 | pd = IO_MEM_UNASSIGNED; |
| 4061 | } else { |
| 4062 | pd = p->phys_offset; |
| 4063 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4064 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4065 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 4066 | !(pd & IO_MEM_ROMD)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4067 | /* I/O case */ |
| 4068 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4069 | if (p) |
| 4070 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4071 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 4072 | } else { |
| 4073 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4074 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4075 | (addr & ~TARGET_PAGE_MASK); |
| 4076 | val = ldl_p(ptr); |
| 4077 | } |
| 4078 | return val; |
| 4079 | } |
| 4080 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4081 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4082 | uint64_t ldq_phys(target_phys_addr_t addr) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4083 | { |
| 4084 | int io_index; |
| 4085 | uint8_t *ptr; |
| 4086 | uint64_t val; |
| 4087 | unsigned long pd; |
| 4088 | PhysPageDesc *p; |
| 4089 | |
| 4090 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4091 | if (!p) { |
| 4092 | pd = IO_MEM_UNASSIGNED; |
| 4093 | } else { |
| 4094 | pd = p->phys_offset; |
| 4095 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4096 | |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 4097 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 4098 | !(pd & IO_MEM_ROMD)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4099 | /* I/O case */ |
| 4100 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4101 | if (p) |
| 4102 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4103 | #ifdef TARGET_WORDS_BIGENDIAN |
| 4104 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; |
| 4105 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); |
| 4106 | #else |
| 4107 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 4108 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; |
| 4109 | #endif |
| 4110 | } else { |
| 4111 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4112 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4113 | (addr & ~TARGET_PAGE_MASK); |
| 4114 | val = ldq_p(ptr); |
| 4115 | } |
| 4116 | return val; |
| 4117 | } |
| 4118 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4119 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4120 | uint32_t ldub_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4121 | { |
| 4122 | uint8_t val; |
| 4123 | cpu_physical_memory_read(addr, &val, 1); |
| 4124 | return val; |
| 4125 | } |
| 4126 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4127 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4128 | uint32_t lduw_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4129 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4130 | int io_index; |
| 4131 | uint8_t *ptr; |
| 4132 | uint64_t val; |
| 4133 | unsigned long pd; |
| 4134 | PhysPageDesc *p; |
| 4135 | |
| 4136 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4137 | if (!p) { |
| 4138 | pd = IO_MEM_UNASSIGNED; |
| 4139 | } else { |
| 4140 | pd = p->phys_offset; |
| 4141 | } |
| 4142 | |
| 4143 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 4144 | !(pd & IO_MEM_ROMD)) { |
| 4145 | /* I/O case */ |
| 4146 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 4147 | if (p) |
| 4148 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 4149 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
| 4150 | } else { |
| 4151 | /* RAM case */ |
| 4152 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
| 4153 | (addr & ~TARGET_PAGE_MASK); |
| 4154 | val = lduw_p(ptr); |
| 4155 | } |
| 4156 | return val; |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4157 | } |
| 4158 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4159 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 4160 | and the code inside is not invalidated. It is useful if the dirty |
| 4161 | bits are used to track modified PTEs */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4162 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4163 | { |
| 4164 | int io_index; |
| 4165 | uint8_t *ptr; |
| 4166 | unsigned long pd; |
| 4167 | PhysPageDesc *p; |
| 4168 | |
| 4169 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4170 | if (!p) { |
| 4171 | pd = IO_MEM_UNASSIGNED; |
| 4172 | } else { |
| 4173 | pd = p->phys_offset; |
| 4174 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4175 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4176 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4177 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4178 | if (p) |
| 4179 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4180 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4181 | } else { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4182 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4183 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4184 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4185 | |
| 4186 | if (unlikely(in_migration)) { |
| 4187 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4188 | /* invalidate code */ |
| 4189 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4190 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4191 | cpu_physical_memory_set_dirty_flags( |
| 4192 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4193 | } |
| 4194 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4195 | } |
| 4196 | } |
| 4197 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4198 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4199 | { |
| 4200 | int io_index; |
| 4201 | uint8_t *ptr; |
| 4202 | unsigned long pd; |
| 4203 | PhysPageDesc *p; |
| 4204 | |
| 4205 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4206 | if (!p) { |
| 4207 | pd = IO_MEM_UNASSIGNED; |
| 4208 | } else { |
| 4209 | pd = p->phys_offset; |
| 4210 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4211 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4212 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 4213 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4214 | if (p) |
| 4215 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4216 | #ifdef TARGET_WORDS_BIGENDIAN |
| 4217 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); |
| 4218 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); |
| 4219 | #else |
| 4220 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4221 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); |
| 4222 | #endif |
| 4223 | } else { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4224 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4225 | (addr & ~TARGET_PAGE_MASK); |
| 4226 | stq_p(ptr, val); |
| 4227 | } |
| 4228 | } |
| 4229 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4230 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4231 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4232 | { |
| 4233 | int io_index; |
| 4234 | uint8_t *ptr; |
| 4235 | unsigned long pd; |
| 4236 | PhysPageDesc *p; |
| 4237 | |
| 4238 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4239 | if (!p) { |
| 4240 | pd = IO_MEM_UNASSIGNED; |
| 4241 | } else { |
| 4242 | pd = p->phys_offset; |
| 4243 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4244 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4245 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4246 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4247 | if (p) |
| 4248 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4249 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4250 | } else { |
| 4251 | unsigned long addr1; |
| 4252 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4253 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4254 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4255 | stl_p(ptr, val); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4256 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4257 | /* invalidate code */ |
| 4258 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4259 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4260 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4261 | (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4262 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4263 | } |
| 4264 | } |
| 4265 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4266 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4267 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4268 | { |
| 4269 | uint8_t v = val; |
| 4270 | cpu_physical_memory_write(addr, &v, 1); |
| 4271 | } |
| 4272 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4273 | /* warning: addr must be aligned */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4274 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4275 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4276 | int io_index; |
| 4277 | uint8_t *ptr; |
| 4278 | unsigned long pd; |
| 4279 | PhysPageDesc *p; |
| 4280 | |
| 4281 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4282 | if (!p) { |
| 4283 | pd = IO_MEM_UNASSIGNED; |
| 4284 | } else { |
| 4285 | pd = p->phys_offset; |
| 4286 | } |
| 4287 | |
| 4288 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 4289 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 4290 | if (p) |
| 4291 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 4292 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
| 4293 | } else { |
| 4294 | unsigned long addr1; |
| 4295 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4296 | /* RAM case */ |
| 4297 | ptr = qemu_get_ram_ptr(addr1); |
| 4298 | stw_p(ptr, val); |
| 4299 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4300 | /* invalidate code */ |
| 4301 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); |
| 4302 | /* set dirty bit */ |
| 4303 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4304 | (0xff & ~CODE_DIRTY_FLAG)); |
| 4305 | } |
| 4306 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4307 | } |
| 4308 | |
| 4309 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4310 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4311 | { |
| 4312 | val = tswap64(val); |
Stefan Weil | 71d2b72 | 2011-03-26 21:06:56 +0100 | [diff] [blame] | 4313 | cpu_physical_memory_write(addr, &val, 8); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4314 | } |
| 4315 | |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4316 | /* virtual memory access for debug (includes writing to ROM) */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4317 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 4318 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4319 | { |
| 4320 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4321 | target_phys_addr_t phys_addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 4322 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4323 | |
| 4324 | while (len > 0) { |
| 4325 | page = addr & TARGET_PAGE_MASK; |
| 4326 | phys_addr = cpu_get_phys_page_debug(env, page); |
| 4327 | /* if no physical page mapped, return an error */ |
| 4328 | if (phys_addr == -1) |
| 4329 | return -1; |
| 4330 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4331 | if (l > len) |
| 4332 | l = len; |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4333 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4334 | if (is_write) |
| 4335 | cpu_physical_memory_write_rom(phys_addr, buf, l); |
| 4336 | else |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4337 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4338 | len -= l; |
| 4339 | buf += l; |
| 4340 | addr += l; |
| 4341 | } |
| 4342 | return 0; |
| 4343 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 4344 | #endif |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4345 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4346 | /* in deterministic execution mode, instructions doing device I/Os |
| 4347 | must be at the end of the TB */ |
| 4348 | void cpu_io_recompile(CPUState *env, void *retaddr) |
| 4349 | { |
| 4350 | TranslationBlock *tb; |
| 4351 | uint32_t n, cflags; |
| 4352 | target_ulong pc, cs_base; |
| 4353 | uint64_t flags; |
| 4354 | |
| 4355 | tb = tb_find_pc((unsigned long)retaddr); |
| 4356 | if (!tb) { |
| 4357 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", |
| 4358 | retaddr); |
| 4359 | } |
| 4360 | n = env->icount_decr.u16.low + tb->icount; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 4361 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4362 | /* Calculate how many instructions had been executed before the fault |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4363 | occurred. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4364 | n = n - env->icount_decr.u16.low; |
| 4365 | /* Generate a new TB ending on the I/O insn. */ |
| 4366 | n++; |
| 4367 | /* On MIPS and SH, delay slot instructions can only be restarted if |
| 4368 | they were already the first instruction in the TB. If this is not |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4369 | the first instruction in a TB then re-execute the preceding |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4370 | branch. */ |
| 4371 | #if defined(TARGET_MIPS) |
| 4372 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { |
| 4373 | env->active_tc.PC -= 4; |
| 4374 | env->icount_decr.u16.low++; |
| 4375 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 4376 | } |
| 4377 | #elif defined(TARGET_SH4) |
| 4378 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
| 4379 | && n > 1) { |
| 4380 | env->pc -= 2; |
| 4381 | env->icount_decr.u16.low++; |
| 4382 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 4383 | } |
| 4384 | #endif |
| 4385 | /* This should never happen. */ |
| 4386 | if (n > CF_COUNT_MASK) |
| 4387 | cpu_abort(env, "TB too big during recompile"); |
| 4388 | |
| 4389 | cflags = n | CF_LAST_IO; |
| 4390 | pc = tb->pc; |
| 4391 | cs_base = tb->cs_base; |
| 4392 | flags = tb->flags; |
| 4393 | tb_phys_invalidate(tb, -1); |
| 4394 | /* FIXME: In theory this could raise an exception. In practice |
| 4395 | we have already translated the block once so it's probably ok. */ |
| 4396 | tb_gen_code(env, pc, cs_base, flags, cflags); |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4397 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4398 | the first in the TB) then we end up generating a whole new TB and |
| 4399 | repeating the fault, which is horribly inefficient. |
| 4400 | Better would be to execute just this insn uncached, or generate a |
| 4401 | second new TB. */ |
| 4402 | cpu_resume_from_signal(env, NULL); |
| 4403 | } |
| 4404 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 4405 | #if !defined(CONFIG_USER_ONLY) |
| 4406 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4407 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4408 | { |
| 4409 | int i, target_code_size, max_target_code_size; |
| 4410 | int direct_jmp_count, direct_jmp2_count, cross_page; |
| 4411 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4412 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4413 | target_code_size = 0; |
| 4414 | max_target_code_size = 0; |
| 4415 | cross_page = 0; |
| 4416 | direct_jmp_count = 0; |
| 4417 | direct_jmp2_count = 0; |
| 4418 | for(i = 0; i < nb_tbs; i++) { |
| 4419 | tb = &tbs[i]; |
| 4420 | target_code_size += tb->size; |
| 4421 | if (tb->size > max_target_code_size) |
| 4422 | max_target_code_size = tb->size; |
| 4423 | if (tb->page_addr[1] != -1) |
| 4424 | cross_page++; |
| 4425 | if (tb->tb_next_offset[0] != 0xffff) { |
| 4426 | direct_jmp_count++; |
| 4427 | if (tb->tb_next_offset[1] != 0xffff) { |
| 4428 | direct_jmp2_count++; |
| 4429 | } |
| 4430 | } |
| 4431 | } |
| 4432 | /* XXX: avoid using doubles ? */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4433 | cpu_fprintf(f, "Translation buffer state:\n"); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4434 | cpu_fprintf(f, "gen code size %td/%ld\n", |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 4435 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
| 4436 | cpu_fprintf(f, "TB count %d/%d\n", |
| 4437 | nb_tbs, code_gen_max_blocks); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4438 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4439 | nb_tbs ? target_code_size / nb_tbs : 0, |
| 4440 | max_target_code_size); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4441 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4442 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
| 4443 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4444 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
| 4445 | cross_page, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4446 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
| 4447 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4448 | direct_jmp_count, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4449 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
| 4450 | direct_jmp2_count, |
| 4451 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4452 | cpu_fprintf(f, "\nStatistics:\n"); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4453 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
| 4454 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); |
| 4455 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 4456 | tcg_dump_info(f, cpu_fprintf); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4457 | } |
| 4458 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4459 | #define MMUSUFFIX _cmmu |
| 4460 | #define GETPC() NULL |
| 4461 | #define env cpu_single_env |
bellard | b769d8f | 2004-10-03 15:07:13 +0000 | [diff] [blame] | 4462 | #define SOFTMMU_CODE_ACCESS |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4463 | |
| 4464 | #define SHIFT 0 |
| 4465 | #include "softmmu_template.h" |
| 4466 | |
| 4467 | #define SHIFT 1 |
| 4468 | #include "softmmu_template.h" |
| 4469 | |
| 4470 | #define SHIFT 2 |
| 4471 | #include "softmmu_template.h" |
| 4472 | |
| 4473 | #define SHIFT 3 |
| 4474 | #include "softmmu_template.h" |
| 4475 | |
| 4476 | #undef env |
| 4477 | |
| 4478 | #endif |