bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 1 | /* |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 2 | * virtual page mapping and translated block handling |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 18 | */ |
bellard | 67b915a | 2004-03-31 23:37:16 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 20 | #ifdef _WIN32 |
| 21 | #include <windows.h> |
| 22 | #else |
bellard | a98d49b | 2004-11-14 16:22:05 +0000 | [diff] [blame] | 23 | #include <sys/types.h> |
bellard | d5a8f07 | 2004-09-29 21:15:28 +0000 | [diff] [blame] | 24 | #include <sys/mman.h> |
| 25 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 26 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 27 | #include "qemu-common.h" |
bellard | 6180a18 | 2003-09-30 21:04:53 +0000 | [diff] [blame] | 28 | #include "cpu.h" |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 29 | #include "tcg.h" |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 30 | #include "hw/hw.h" |
Alex Williamson | cc9e98c | 2010-06-25 11:09:43 -0600 | [diff] [blame] | 31 | #include "hw/qdev.h" |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 32 | #include "osdep.h" |
aliguori | 7ba1e61 | 2008-11-05 16:04:33 +0000 | [diff] [blame] | 33 | #include "kvm.h" |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 34 | #include "hw/xen.h" |
Blue Swirl | 29e922b | 2010-03-29 19:24:00 +0000 | [diff] [blame] | 35 | #include "qemu-timer.h" |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 36 | #include "memory.h" |
| 37 | #include "exec-memory.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 38 | #if defined(CONFIG_USER_ONLY) |
| 39 | #include <qemu.h> |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 40 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) |
| 41 | #include <sys/param.h> |
| 42 | #if __FreeBSD_version >= 700104 |
| 43 | #define HAVE_KINFO_GETVMMAP |
| 44 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ |
| 45 | #include <sys/time.h> |
| 46 | #include <sys/proc.h> |
| 47 | #include <machine/profile.h> |
| 48 | #define _KERNEL |
| 49 | #include <sys/user.h> |
| 50 | #undef _KERNEL |
| 51 | #undef sigqueue |
| 52 | #include <libutil.h> |
| 53 | #endif |
| 54 | #endif |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 55 | #else /* !CONFIG_USER_ONLY */ |
| 56 | #include "xen-mapcache.h" |
Stefano Stabellini | 6506e4f | 2011-05-19 18:35:44 +0100 | [diff] [blame] | 57 | #include "trace.h" |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 58 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 59 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 60 | //#define DEBUG_TB_INVALIDATE |
bellard | 66e85a2 | 2003-06-24 13:28:12 +0000 | [diff] [blame] | 61 | //#define DEBUG_FLUSH |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 62 | //#define DEBUG_TLB |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 63 | //#define DEBUG_UNASSIGNED |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 64 | |
| 65 | /* make various TB consistency checks */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 66 | //#define DEBUG_TB_CHECK |
| 67 | //#define DEBUG_TLB_CHECK |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 68 | |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 69 | //#define DEBUG_IOPORT |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 70 | //#define DEBUG_SUBPAGE |
ths | 1196be3 | 2007-03-17 15:17:58 +0000 | [diff] [blame] | 71 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 72 | #if !defined(CONFIG_USER_ONLY) |
| 73 | /* TB consistency checks only implemented for usermode emulation. */ |
| 74 | #undef DEBUG_TB_CHECK |
| 75 | #endif |
| 76 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 77 | #define SMC_BITMAP_USE_THRESHOLD 10 |
| 78 | |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 79 | static TranslationBlock *tbs; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 80 | static int code_gen_max_blocks; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 81 | TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 82 | static int nb_tbs; |
bellard | eb51d10 | 2003-05-14 21:51:13 +0000 | [diff] [blame] | 83 | /* any access to the tbs or the page table must use this lock */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 84 | spinlock_t tb_lock = SPIN_LOCK_UNLOCKED; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 85 | |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 86 | #if defined(__arm__) || defined(__sparc_v9__) |
| 87 | /* The prologue must be reachable with a direct jump. ARM and Sparc64 |
| 88 | have limited branch ranges (possibly also PPC) so place it in a |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 89 | section close to code segment. */ |
| 90 | #define code_gen_section \ |
| 91 | __attribute__((__section__(".gen_code"))) \ |
| 92 | __attribute__((aligned (32))) |
Stefan Weil | f8e2af1 | 2009-06-18 23:04:48 +0200 | [diff] [blame] | 93 | #elif defined(_WIN32) |
| 94 | /* Maximum alignment for Win32 is 16. */ |
| 95 | #define code_gen_section \ |
| 96 | __attribute__((aligned (16))) |
blueswir1 | d03d860 | 2008-07-10 17:21:31 +0000 | [diff] [blame] | 97 | #else |
| 98 | #define code_gen_section \ |
| 99 | __attribute__((aligned (32))) |
| 100 | #endif |
| 101 | |
| 102 | uint8_t code_gen_prologue[1024] code_gen_section; |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 103 | static uint8_t *code_gen_buffer; |
| 104 | static unsigned long code_gen_buffer_size; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 105 | /* threshold to flush the translated code buffer */ |
blueswir1 | bdaf78e | 2008-10-04 07:24:27 +0000 | [diff] [blame] | 106 | static unsigned long code_gen_buffer_max_size; |
Stefan Weil | 24ab68a | 2010-07-19 18:23:17 +0200 | [diff] [blame] | 107 | static uint8_t *code_gen_ptr; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 108 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 109 | #if !defined(CONFIG_USER_ONLY) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 110 | int phys_ram_fd; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 111 | static int in_migration; |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 112 | |
Paolo Bonzini | 85d59fe | 2011-08-12 13:18:14 +0200 | [diff] [blame] | 113 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 114 | |
| 115 | static MemoryRegion *system_memory; |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 116 | static MemoryRegion *system_io; |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 117 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 118 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 119 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 120 | CPUState *first_cpu; |
| 121 | /* current CPU in the current thread. It is only valid inside |
| 122 | cpu_exec() */ |
Paolo Bonzini | b3c4bbe | 2011-10-28 10:52:42 +0100 | [diff] [blame^] | 123 | DEFINE_TLS(CPUState *,cpu_single_env); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 124 | /* 0 = Do not count executed instructions. |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 125 | 1 = Precise instruction counting. |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 126 | 2 = Adaptive rate instruction counting. */ |
| 127 | int use_icount = 0; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 128 | |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 129 | typedef struct PageDesc { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 130 | /* list of TBs intersecting this ram page */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 131 | TranslationBlock *first_tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 132 | /* in order to optimize self modifying code, we count the number |
| 133 | of lookups we do to a given page to use a bitmap */ |
| 134 | unsigned int code_write_count; |
| 135 | uint8_t *code_bitmap; |
| 136 | #if defined(CONFIG_USER_ONLY) |
| 137 | unsigned long flags; |
| 138 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 139 | } PageDesc; |
| 140 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 141 | /* In system mode we want L1_MAP to be based on ram offsets, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 142 | while in user mode we want it to be based on virtual addresses. */ |
| 143 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 144 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS |
| 145 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS |
| 146 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 147 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 148 | #endif |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 149 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 150 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS |
j_mayer | bedb69e | 2007-04-05 20:08:21 +0000 | [diff] [blame] | 151 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 152 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 153 | /* Size of the L2 (and L3, etc) page tables. */ |
| 154 | #define L2_BITS 10 |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 155 | #define L2_SIZE (1 << L2_BITS) |
| 156 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 157 | /* The bits remaining after N lower levels of page tables. */ |
| 158 | #define P_L1_BITS_REM \ |
| 159 | ((TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 160 | #define V_L1_BITS_REM \ |
| 161 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % L2_BITS) |
| 162 | |
| 163 | /* Size of the L1 page table. Avoid silly small sizes. */ |
| 164 | #if P_L1_BITS_REM < 4 |
| 165 | #define P_L1_BITS (P_L1_BITS_REM + L2_BITS) |
| 166 | #else |
| 167 | #define P_L1_BITS P_L1_BITS_REM |
| 168 | #endif |
| 169 | |
| 170 | #if V_L1_BITS_REM < 4 |
| 171 | #define V_L1_BITS (V_L1_BITS_REM + L2_BITS) |
| 172 | #else |
| 173 | #define V_L1_BITS V_L1_BITS_REM |
| 174 | #endif |
| 175 | |
| 176 | #define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS) |
| 177 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) |
| 178 | |
| 179 | #define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS) |
| 180 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) |
| 181 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 182 | unsigned long qemu_real_host_page_size; |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 183 | unsigned long qemu_host_page_size; |
| 184 | unsigned long qemu_host_page_mask; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 185 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 186 | /* This is a multi-level map on the virtual address space. |
| 187 | The bottom level has pointers to PageDesc. */ |
| 188 | static void *l1_map[V_L1_SIZE]; |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 189 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 190 | #if !defined(CONFIG_USER_ONLY) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 191 | typedef struct PhysPageDesc { |
| 192 | /* offset in host memory of the page + io_index in the low bits */ |
| 193 | ram_addr_t phys_offset; |
| 194 | ram_addr_t region_offset; |
| 195 | } PhysPageDesc; |
| 196 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 197 | /* This is a multi-level map on the physical address space. |
| 198 | The bottom level has pointers to PhysPageDesc. */ |
| 199 | static void *l1_phys_map[P_L1_SIZE]; |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 200 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 201 | static void io_mem_init(void); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 202 | static void memory_map_init(void); |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 203 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 204 | /* io memory support */ |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 205 | CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
| 206 | CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 207 | void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
blueswir1 | 511d2b1 | 2009-03-07 15:32:56 +0000 | [diff] [blame] | 208 | static char io_mem_used[IO_MEM_NB_ENTRIES]; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 209 | static int io_mem_watch; |
| 210 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 211 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 212 | /* log support */ |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 213 | #ifdef WIN32 |
| 214 | static const char *logfilename = "qemu.log"; |
| 215 | #else |
blueswir1 | d9b630f | 2008-10-05 09:57:08 +0000 | [diff] [blame] | 216 | static const char *logfilename = "/tmp/qemu.log"; |
Juha Riihimäki | 1e8b27c | 2009-12-03 15:56:02 +0200 | [diff] [blame] | 217 | #endif |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 218 | FILE *logfile; |
| 219 | int loglevel; |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 220 | static int log_append = 0; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 221 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 222 | /* statistics */ |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 223 | #if !defined(CONFIG_USER_ONLY) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 224 | static int tlb_flush_count; |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 225 | #endif |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 226 | static int tb_flush_count; |
| 227 | static int tb_phys_invalidate_count; |
| 228 | |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 229 | #ifdef _WIN32 |
| 230 | static void map_exec(void *addr, long size) |
| 231 | { |
| 232 | DWORD old_protect; |
| 233 | VirtualProtect(addr, size, |
| 234 | PAGE_EXECUTE_READWRITE, &old_protect); |
| 235 | |
| 236 | } |
| 237 | #else |
| 238 | static void map_exec(void *addr, long size) |
| 239 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 240 | unsigned long start, end, page_size; |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 241 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 242 | page_size = getpagesize(); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 243 | start = (unsigned long)addr; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 244 | start &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 245 | |
| 246 | end = (unsigned long)addr + size; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 247 | end += page_size - 1; |
| 248 | end &= ~(page_size - 1); |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 249 | |
| 250 | mprotect((void *)start, end - start, |
| 251 | PROT_READ | PROT_WRITE | PROT_EXEC); |
| 252 | } |
| 253 | #endif |
| 254 | |
bellard | b346ff4 | 2003-06-15 20:05:50 +0000 | [diff] [blame] | 255 | static void page_init(void) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 256 | { |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 257 | /* NOTE: we can always suppose that qemu_host_page_size >= |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 258 | TARGET_PAGE_SIZE */ |
aliguori | c2b48b6 | 2008-11-11 22:06:42 +0000 | [diff] [blame] | 259 | #ifdef _WIN32 |
| 260 | { |
| 261 | SYSTEM_INFO system_info; |
| 262 | |
| 263 | GetSystemInfo(&system_info); |
| 264 | qemu_real_host_page_size = system_info.dwPageSize; |
| 265 | } |
| 266 | #else |
| 267 | qemu_real_host_page_size = getpagesize(); |
| 268 | #endif |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 269 | if (qemu_host_page_size == 0) |
| 270 | qemu_host_page_size = qemu_real_host_page_size; |
| 271 | if (qemu_host_page_size < TARGET_PAGE_SIZE) |
| 272 | qemu_host_page_size = TARGET_PAGE_SIZE; |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 273 | qemu_host_page_mask = ~(qemu_host_page_size - 1); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 274 | |
Paul Brook | 2e9a571 | 2010-05-05 16:32:59 +0100 | [diff] [blame] | 275 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 276 | { |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 277 | #ifdef HAVE_KINFO_GETVMMAP |
| 278 | struct kinfo_vmentry *freep; |
| 279 | int i, cnt; |
| 280 | |
| 281 | freep = kinfo_getvmmap(getpid(), &cnt); |
| 282 | if (freep) { |
| 283 | mmap_lock(); |
| 284 | for (i = 0; i < cnt; i++) { |
| 285 | unsigned long startaddr, endaddr; |
| 286 | |
| 287 | startaddr = freep[i].kve_start; |
| 288 | endaddr = freep[i].kve_end; |
| 289 | if (h2g_valid(startaddr)) { |
| 290 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 291 | |
| 292 | if (h2g_valid(endaddr)) { |
| 293 | endaddr = h2g(endaddr); |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 294 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 295 | } else { |
| 296 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS |
| 297 | endaddr = ~0ul; |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 298 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 299 | #endif |
| 300 | } |
| 301 | } |
| 302 | } |
| 303 | free(freep); |
| 304 | mmap_unlock(); |
| 305 | } |
| 306 | #else |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 307 | FILE *f; |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 308 | |
pbrook | 0776590 | 2008-05-31 16:33:53 +0000 | [diff] [blame] | 309 | last_brk = (unsigned long)sbrk(0); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 310 | |
Aurelien Jarno | fd43690 | 2010-04-10 17:20:36 +0200 | [diff] [blame] | 311 | f = fopen("/compat/linux/proc/self/maps", "r"); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 312 | if (f) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 313 | mmap_lock(); |
| 314 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 315 | do { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 316 | unsigned long startaddr, endaddr; |
| 317 | int n; |
| 318 | |
| 319 | n = fscanf (f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); |
| 320 | |
| 321 | if (n == 2 && h2g_valid(startaddr)) { |
| 322 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; |
| 323 | |
| 324 | if (h2g_valid(endaddr)) { |
| 325 | endaddr = h2g(endaddr); |
| 326 | } else { |
| 327 | endaddr = ~0ul; |
| 328 | } |
| 329 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 330 | } |
| 331 | } while (!feof(f)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 332 | |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 333 | fclose(f); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 334 | mmap_unlock(); |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 335 | } |
Juergen Lock | f01576f | 2010-03-25 22:32:16 +0100 | [diff] [blame] | 336 | #endif |
balrog | 50a9569 | 2007-12-12 01:16:23 +0000 | [diff] [blame] | 337 | } |
| 338 | #endif |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 339 | } |
| 340 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 341 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 342 | { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 343 | PageDesc *pd; |
| 344 | void **lp; |
| 345 | int i; |
| 346 | |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 347 | #if defined(CONFIG_USER_ONLY) |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 348 | /* We can't use g_malloc because it may recurse into a locked mutex. */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 349 | # define ALLOC(P, SIZE) \ |
| 350 | do { \ |
| 351 | P = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, \ |
| 352 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); \ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 353 | } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 354 | #else |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 355 | # define ALLOC(P, SIZE) \ |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 356 | do { P = g_malloc0(SIZE); } while (0) |
pbrook | 17e2377 | 2008-06-09 13:47:45 +0000 | [diff] [blame] | 357 | #endif |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 358 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 359 | /* Level 1. Always allocated. */ |
| 360 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); |
| 361 | |
| 362 | /* Level 2..N-1. */ |
| 363 | for (i = V_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 364 | void **p = *lp; |
| 365 | |
| 366 | if (p == NULL) { |
| 367 | if (!alloc) { |
| 368 | return NULL; |
| 369 | } |
| 370 | ALLOC(p, sizeof(void *) * L2_SIZE); |
| 371 | *lp = p; |
| 372 | } |
| 373 | |
| 374 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 375 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 376 | |
| 377 | pd = *lp; |
| 378 | if (pd == NULL) { |
| 379 | if (!alloc) { |
| 380 | return NULL; |
| 381 | } |
| 382 | ALLOC(pd, sizeof(PageDesc) * L2_SIZE); |
| 383 | *lp = pd; |
| 384 | } |
| 385 | |
| 386 | #undef ALLOC |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 387 | |
| 388 | return pd + (index & (L2_SIZE - 1)); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 389 | } |
| 390 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 391 | static inline PageDesc *page_find(tb_page_addr_t index) |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 392 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 393 | return page_find_alloc(index, 0); |
bellard | 5493600 | 2003-05-13 00:25:15 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Paul Brook | 6d9a130 | 2010-02-28 23:55:53 +0000 | [diff] [blame] | 396 | #if !defined(CONFIG_USER_ONLY) |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 397 | static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 398 | { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 399 | PhysPageDesc *pd; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 400 | void **lp; |
| 401 | int i; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 402 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 403 | /* Level 1. Always allocated. */ |
| 404 | lp = l1_phys_map + ((index >> P_L1_SHIFT) & (P_L1_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 405 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 406 | /* Level 2..N-1. */ |
| 407 | for (i = P_L1_SHIFT / L2_BITS - 1; i > 0; i--) { |
| 408 | void **p = *lp; |
| 409 | if (p == NULL) { |
| 410 | if (!alloc) { |
| 411 | return NULL; |
| 412 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 413 | *lp = p = g_malloc0(sizeof(void *) * L2_SIZE); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 414 | } |
| 415 | lp = p + ((index >> (i * L2_BITS)) & (L2_SIZE - 1)); |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 416 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 417 | |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 418 | pd = *lp; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 419 | if (pd == NULL) { |
pbrook | e3f4e2a | 2006-04-08 20:02:06 +0000 | [diff] [blame] | 420 | int i; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 421 | |
| 422 | if (!alloc) { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 423 | return NULL; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 424 | } |
| 425 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 426 | *lp = pd = g_malloc(sizeof(PhysPageDesc) * L2_SIZE); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 427 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 428 | for (i = 0; i < L2_SIZE; i++) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 429 | pd[i].phys_offset = IO_MEM_UNASSIGNED; |
| 430 | pd[i].region_offset = (index + i) << TARGET_PAGE_BITS; |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 431 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 432 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 433 | |
| 434 | return pd + (index & (L2_SIZE - 1)); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 435 | } |
| 436 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 437 | static inline PhysPageDesc *phys_page_find(target_phys_addr_t index) |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 438 | { |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 439 | return phys_page_find_alloc(index, 0); |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 440 | } |
| 441 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 442 | static void tlb_protect_code(ram_addr_t ram_addr); |
| 443 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 444 | target_ulong vaddr); |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 445 | #define mmap_lock() do { } while(0) |
| 446 | #define mmap_unlock() do { } while(0) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 447 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 448 | |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 449 | #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024) |
| 450 | |
| 451 | #if defined(CONFIG_USER_ONLY) |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 452 | /* Currently it is not recommended to allocate big chunks of data in |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 453 | user mode. It will change when a dedicated libc will be used */ |
| 454 | #define USE_STATIC_CODE_GEN_BUFFER |
| 455 | #endif |
| 456 | |
| 457 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
Aurelien Jarno | ebf50fb | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 458 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] |
| 459 | __attribute__((aligned (CODE_GEN_ALIGN))); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 460 | #endif |
| 461 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 462 | static void code_gen_alloc(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 463 | { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 464 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
| 465 | code_gen_buffer = static_code_gen_buffer; |
| 466 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 467 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 468 | #else |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 469 | code_gen_buffer_size = tb_size; |
| 470 | if (code_gen_buffer_size == 0) { |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 471 | #if defined(CONFIG_USER_ONLY) |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 472 | code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE; |
| 473 | #else |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 474 | /* XXX: needs adjustments */ |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 475 | code_gen_buffer_size = (unsigned long)(ram_size / 4); |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 476 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 477 | } |
| 478 | if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE) |
| 479 | code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE; |
| 480 | /* The code gen buffer location may have constraints depending on |
| 481 | the host cpu and OS */ |
| 482 | #if defined(__linux__) |
| 483 | { |
| 484 | int flags; |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 485 | void *start = NULL; |
| 486 | |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 487 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 488 | #if defined(__x86_64__) |
| 489 | flags |= MAP_32BIT; |
| 490 | /* Cannot map more than that */ |
| 491 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 492 | code_gen_buffer_size = (800 * 1024 * 1024); |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 493 | #elif defined(__sparc_v9__) |
| 494 | // Map the buffer below 2G, so we can use direct calls and branches |
| 495 | flags |= MAP_FIXED; |
| 496 | start = (void *) 0x60000000UL; |
| 497 | if (code_gen_buffer_size > (512 * 1024 * 1024)) |
| 498 | code_gen_buffer_size = (512 * 1024 * 1024); |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 499 | #elif defined(__arm__) |
balrog | 63d4124 | 2008-12-01 02:19:41 +0000 | [diff] [blame] | 500 | /* Map the buffer below 32M, so we can use direct calls and branches */ |
balrog | 1cb0661 | 2008-12-01 02:10:17 +0000 | [diff] [blame] | 501 | flags |= MAP_FIXED; |
| 502 | start = (void *) 0x01000000UL; |
| 503 | if (code_gen_buffer_size > 16 * 1024 * 1024) |
| 504 | code_gen_buffer_size = 16 * 1024 * 1024; |
Richard Henderson | eba0b89 | 2010-06-04 12:14:14 -0700 | [diff] [blame] | 505 | #elif defined(__s390x__) |
| 506 | /* Map the buffer so that we can use direct calls and branches. */ |
| 507 | /* We have a +- 4GB range on the branches; leave some slop. */ |
| 508 | if (code_gen_buffer_size > (3ul * 1024 * 1024 * 1024)) { |
| 509 | code_gen_buffer_size = 3ul * 1024 * 1024 * 1024; |
| 510 | } |
| 511 | start = (void *)0x90000000UL; |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 512 | #endif |
blueswir1 | 141ac46 | 2008-07-26 15:05:57 +0000 | [diff] [blame] | 513 | code_gen_buffer = mmap(start, code_gen_buffer_size, |
| 514 | PROT_WRITE | PROT_READ | PROT_EXEC, |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 515 | flags, -1, 0); |
| 516 | if (code_gen_buffer == MAP_FAILED) { |
| 517 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 518 | exit(1); |
| 519 | } |
| 520 | } |
Brad | cbb608a | 2010-12-20 21:25:40 -0500 | [diff] [blame] | 521 | #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
Tobias Nygren | 9f4b09a | 2011-08-07 09:57:05 +0000 | [diff] [blame] | 522 | || defined(__DragonFly__) || defined(__OpenBSD__) \ |
| 523 | || defined(__NetBSD__) |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 524 | { |
| 525 | int flags; |
| 526 | void *addr = NULL; |
| 527 | flags = MAP_PRIVATE | MAP_ANONYMOUS; |
| 528 | #if defined(__x86_64__) |
| 529 | /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume |
| 530 | * 0x40000000 is free */ |
| 531 | flags |= MAP_FIXED; |
| 532 | addr = (void *)0x40000000; |
| 533 | /* Cannot map more than that */ |
| 534 | if (code_gen_buffer_size > (800 * 1024 * 1024)) |
| 535 | code_gen_buffer_size = (800 * 1024 * 1024); |
Blue Swirl | 4cd31ad | 2011-01-16 08:32:27 +0000 | [diff] [blame] | 536 | #elif defined(__sparc_v9__) |
| 537 | // Map the buffer below 2G, so we can use direct calls and branches |
| 538 | flags |= MAP_FIXED; |
| 539 | addr = (void *) 0x60000000UL; |
| 540 | if (code_gen_buffer_size > (512 * 1024 * 1024)) { |
| 541 | code_gen_buffer_size = (512 * 1024 * 1024); |
| 542 | } |
aliguori | 06e67a8 | 2008-09-27 15:32:41 +0000 | [diff] [blame] | 543 | #endif |
| 544 | code_gen_buffer = mmap(addr, code_gen_buffer_size, |
| 545 | PROT_WRITE | PROT_READ | PROT_EXEC, |
| 546 | flags, -1, 0); |
| 547 | if (code_gen_buffer == MAP_FAILED) { |
| 548 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
| 549 | exit(1); |
| 550 | } |
| 551 | } |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 552 | #else |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 553 | code_gen_buffer = g_malloc(code_gen_buffer_size); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 554 | map_exec(code_gen_buffer, code_gen_buffer_size); |
| 555 | #endif |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 556 | #endif /* !USE_STATIC_CODE_GEN_BUFFER */ |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 557 | map_exec(code_gen_prologue, sizeof(code_gen_prologue)); |
Peter Maydell | a884da8 | 2011-06-22 11:58:25 +0100 | [diff] [blame] | 558 | code_gen_buffer_max_size = code_gen_buffer_size - |
| 559 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 560 | code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 561 | tbs = g_malloc(code_gen_max_blocks * sizeof(TranslationBlock)); |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
| 565 | (in bytes) allocated to the translation buffer. Zero means default |
| 566 | size. */ |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 567 | void tcg_exec_init(unsigned long tb_size) |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 568 | { |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 569 | cpu_gen_init(); |
| 570 | code_gen_alloc(tb_size); |
| 571 | code_gen_ptr = code_gen_buffer; |
bellard | 4369415 | 2008-05-29 09:35:57 +0000 | [diff] [blame] | 572 | page_init(); |
Richard Henderson | 9002ec7 | 2010-05-06 08:50:41 -0700 | [diff] [blame] | 573 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) |
| 574 | /* There's no guest base to take into account, so go ahead and |
| 575 | initialize the prologue now. */ |
| 576 | tcg_prologue_init(&tcg_ctx); |
| 577 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 578 | } |
| 579 | |
Jan Kiszka | d5ab971 | 2011-08-02 16:10:21 +0200 | [diff] [blame] | 580 | bool tcg_enabled(void) |
| 581 | { |
| 582 | return code_gen_buffer != NULL; |
| 583 | } |
| 584 | |
| 585 | void cpu_exec_init_all(void) |
| 586 | { |
| 587 | #if !defined(CONFIG_USER_ONLY) |
| 588 | memory_map_init(); |
| 589 | io_mem_init(); |
| 590 | #endif |
| 591 | } |
| 592 | |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 593 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
| 594 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 595 | static int cpu_common_post_load(void *opaque, int version_id) |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 596 | { |
| 597 | CPUState *env = opaque; |
| 598 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 599 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the |
| 600 | version_id is increased. */ |
| 601 | env->interrupt_request &= ~0x01; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 602 | tlb_flush(env, 1); |
| 603 | |
| 604 | return 0; |
| 605 | } |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 606 | |
| 607 | static const VMStateDescription vmstate_cpu_common = { |
| 608 | .name = "cpu_common", |
| 609 | .version_id = 1, |
| 610 | .minimum_version_id = 1, |
| 611 | .minimum_version_id_old = 1, |
Juan Quintela | e7f4eff | 2009-09-10 03:04:33 +0200 | [diff] [blame] | 612 | .post_load = cpu_common_post_load, |
| 613 | .fields = (VMStateField []) { |
| 614 | VMSTATE_UINT32(halted, CPUState), |
| 615 | VMSTATE_UINT32(interrupt_request, CPUState), |
| 616 | VMSTATE_END_OF_LIST() |
| 617 | } |
| 618 | }; |
pbrook | 9656f32 | 2008-07-01 20:01:19 +0000 | [diff] [blame] | 619 | #endif |
| 620 | |
Glauber Costa | 950f147 | 2009-06-09 12:15:18 -0400 | [diff] [blame] | 621 | CPUState *qemu_get_cpu(int cpu) |
| 622 | { |
| 623 | CPUState *env = first_cpu; |
| 624 | |
| 625 | while (env) { |
| 626 | if (env->cpu_index == cpu) |
| 627 | break; |
| 628 | env = env->next_cpu; |
| 629 | } |
| 630 | |
| 631 | return env; |
| 632 | } |
| 633 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 634 | void cpu_exec_init(CPUState *env) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 635 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 636 | CPUState **penv; |
| 637 | int cpu_index; |
| 638 | |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 639 | #if defined(CONFIG_USER_ONLY) |
| 640 | cpu_list_lock(); |
| 641 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 642 | env->next_cpu = NULL; |
| 643 | penv = &first_cpu; |
| 644 | cpu_index = 0; |
| 645 | while (*penv != NULL) { |
Nathan Froyd | 1e9fa73 | 2009-06-03 11:33:08 -0700 | [diff] [blame] | 646 | penv = &(*penv)->next_cpu; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 647 | cpu_index++; |
| 648 | } |
| 649 | env->cpu_index = cpu_index; |
aliguori | 268a362 | 2009-04-21 22:30:27 +0000 | [diff] [blame] | 650 | env->numa_node = 0; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 651 | QTAILQ_INIT(&env->breakpoints); |
| 652 | QTAILQ_INIT(&env->watchpoints); |
Jan Kiszka | dc7a09c | 2011-03-15 12:26:31 +0100 | [diff] [blame] | 653 | #ifndef CONFIG_USER_ONLY |
| 654 | env->thread_id = qemu_get_thread_id(); |
| 655 | #endif |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 656 | *penv = env; |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 657 | #if defined(CONFIG_USER_ONLY) |
| 658 | cpu_list_unlock(); |
| 659 | #endif |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 660 | #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY) |
Alex Williamson | 0be71e3 | 2010-06-25 11:09:07 -0600 | [diff] [blame] | 661 | vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env); |
| 662 | register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION, |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 663 | cpu_save, cpu_load, env); |
| 664 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 665 | } |
| 666 | |
Tristan Gingold | d1a1eb7 | 2011-02-10 10:04:57 +0100 | [diff] [blame] | 667 | /* Allocate a new translation block. Flush the translation buffer if |
| 668 | too many translation blocks or too much generated code. */ |
| 669 | static TranslationBlock *tb_alloc(target_ulong pc) |
| 670 | { |
| 671 | TranslationBlock *tb; |
| 672 | |
| 673 | if (nb_tbs >= code_gen_max_blocks || |
| 674 | (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size) |
| 675 | return NULL; |
| 676 | tb = &tbs[nb_tbs++]; |
| 677 | tb->pc = pc; |
| 678 | tb->cflags = 0; |
| 679 | return tb; |
| 680 | } |
| 681 | |
| 682 | void tb_free(TranslationBlock *tb) |
| 683 | { |
| 684 | /* In practice this is mostly used for single use temporary TB |
| 685 | Ignore the hard cases and just back up if this TB happens to |
| 686 | be the last one generated. */ |
| 687 | if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) { |
| 688 | code_gen_ptr = tb->tc_ptr; |
| 689 | nb_tbs--; |
| 690 | } |
| 691 | } |
| 692 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 693 | static inline void invalidate_page_bitmap(PageDesc *p) |
| 694 | { |
| 695 | if (p->code_bitmap) { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 696 | g_free(p->code_bitmap); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 697 | p->code_bitmap = NULL; |
| 698 | } |
| 699 | p->code_write_count = 0; |
| 700 | } |
| 701 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 702 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ |
| 703 | |
| 704 | static void page_flush_tb_1 (int level, void **lp) |
| 705 | { |
| 706 | int i; |
| 707 | |
| 708 | if (*lp == NULL) { |
| 709 | return; |
| 710 | } |
| 711 | if (level == 0) { |
| 712 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 713 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 714 | pd[i].first_tb = NULL; |
| 715 | invalidate_page_bitmap(pd + i); |
| 716 | } |
| 717 | } else { |
| 718 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 719 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 720 | page_flush_tb_1 (level - 1, pp + i); |
| 721 | } |
| 722 | } |
| 723 | } |
| 724 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 725 | static void page_flush_tb(void) |
| 726 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 727 | int i; |
| 728 | for (i = 0; i < V_L1_SIZE; i++) { |
| 729 | page_flush_tb_1(V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 730 | } |
| 731 | } |
| 732 | |
| 733 | /* flush all the translation blocks */ |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 734 | /* XXX: tb_flush is currently not thread safe */ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 735 | void tb_flush(CPUState *env1) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 736 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 737 | CPUState *env; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 738 | #if defined(DEBUG_FLUSH) |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 739 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", |
| 740 | (unsigned long)(code_gen_ptr - code_gen_buffer), |
| 741 | nb_tbs, nb_tbs > 0 ? |
| 742 | ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 743 | #endif |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 744 | if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size) |
pbrook | a208e54 | 2008-03-31 17:07:36 +0000 | [diff] [blame] | 745 | cpu_abort(env1, "Internal error: code buffer overflow\n"); |
| 746 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 747 | nb_tbs = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 748 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 749 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 750 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
| 751 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 752 | |
bellard | 8a8a608 | 2004-10-03 13:36:49 +0000 | [diff] [blame] | 753 | memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 754 | page_flush_tb(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 755 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 756 | code_gen_ptr = code_gen_buffer; |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 757 | /* XXX: flush processor icache at this point if cache flush is |
| 758 | expensive */ |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 759 | tb_flush_count++; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | #ifdef DEBUG_TB_CHECK |
| 763 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 764 | static void tb_invalidate_check(target_ulong address) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 765 | { |
| 766 | TranslationBlock *tb; |
| 767 | int i; |
| 768 | address &= TARGET_PAGE_MASK; |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 769 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 770 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 771 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
| 772 | address >= tb->pc + tb->size)) { |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 773 | printf("ERROR invalidate: address=" TARGET_FMT_lx |
| 774 | " PC=%08lx size=%04x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 775 | address, (long)tb->pc, tb->size); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 776 | } |
| 777 | } |
| 778 | } |
| 779 | } |
| 780 | |
| 781 | /* verify that all the pages have correct rights for code */ |
| 782 | static void tb_page_check(void) |
| 783 | { |
| 784 | TranslationBlock *tb; |
| 785 | int i, flags1, flags2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 786 | |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 787 | for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) { |
| 788 | for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 789 | flags1 = page_get_flags(tb->pc); |
| 790 | flags2 = page_get_flags(tb->pc + tb->size - 1); |
| 791 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { |
| 792 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", |
pbrook | 99773bd | 2006-04-16 15:14:59 +0000 | [diff] [blame] | 793 | (long)tb->pc, tb->size, flags1, flags2); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 794 | } |
| 795 | } |
| 796 | } |
| 797 | } |
| 798 | |
| 799 | #endif |
| 800 | |
| 801 | /* invalidate one TB */ |
| 802 | static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb, |
| 803 | int next_offset) |
| 804 | { |
| 805 | TranslationBlock *tb1; |
| 806 | for(;;) { |
| 807 | tb1 = *ptb; |
| 808 | if (tb1 == tb) { |
| 809 | *ptb = *(TranslationBlock **)((char *)tb1 + next_offset); |
| 810 | break; |
| 811 | } |
| 812 | ptb = (TranslationBlock **)((char *)tb1 + next_offset); |
| 813 | } |
| 814 | } |
| 815 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 816 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) |
| 817 | { |
| 818 | TranslationBlock *tb1; |
| 819 | unsigned int n1; |
| 820 | |
| 821 | for(;;) { |
| 822 | tb1 = *ptb; |
| 823 | n1 = (long)tb1 & 3; |
| 824 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 825 | if (tb1 == tb) { |
| 826 | *ptb = tb1->page_next[n1]; |
| 827 | break; |
| 828 | } |
| 829 | ptb = &tb1->page_next[n1]; |
| 830 | } |
| 831 | } |
| 832 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 833 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) |
| 834 | { |
| 835 | TranslationBlock *tb1, **ptb; |
| 836 | unsigned int n1; |
| 837 | |
| 838 | ptb = &tb->jmp_next[n]; |
| 839 | tb1 = *ptb; |
| 840 | if (tb1) { |
| 841 | /* find tb(n) in circular list */ |
| 842 | for(;;) { |
| 843 | tb1 = *ptb; |
| 844 | n1 = (long)tb1 & 3; |
| 845 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 846 | if (n1 == n && tb1 == tb) |
| 847 | break; |
| 848 | if (n1 == 2) { |
| 849 | ptb = &tb1->jmp_first; |
| 850 | } else { |
| 851 | ptb = &tb1->jmp_next[n1]; |
| 852 | } |
| 853 | } |
| 854 | /* now we can suppress tb(n) from the list */ |
| 855 | *ptb = tb->jmp_next[n]; |
| 856 | |
| 857 | tb->jmp_next[n] = NULL; |
| 858 | } |
| 859 | } |
| 860 | |
| 861 | /* reset the jump entry 'n' of a TB so that it is not chained to |
| 862 | another TB */ |
| 863 | static inline void tb_reset_jump(TranslationBlock *tb, int n) |
| 864 | { |
| 865 | tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n])); |
| 866 | } |
| 867 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 868 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 869 | { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 870 | CPUState *env; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 871 | PageDesc *p; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 872 | unsigned int h, n1; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 873 | tb_page_addr_t phys_pc; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 874 | TranslationBlock *tb1, *tb2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 875 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 876 | /* remove the TB from the hash list */ |
| 877 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 878 | h = tb_phys_hash_func(phys_pc); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 879 | tb_remove(&tb_phys_hash[h], tb, |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 880 | offsetof(TranslationBlock, phys_hash_next)); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 881 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 882 | /* remove the TB from the page list */ |
| 883 | if (tb->page_addr[0] != page_addr) { |
| 884 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); |
| 885 | tb_page_remove(&p->first_tb, tb); |
| 886 | invalidate_page_bitmap(p); |
| 887 | } |
| 888 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { |
| 889 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); |
| 890 | tb_page_remove(&p->first_tb, tb); |
| 891 | invalidate_page_bitmap(p); |
| 892 | } |
| 893 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 894 | tb_invalidated_flag = 1; |
| 895 | |
| 896 | /* remove the TB from the hash list */ |
| 897 | h = tb_jmp_cache_hash_func(tb->pc); |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 898 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 899 | if (env->tb_jmp_cache[h] == tb) |
| 900 | env->tb_jmp_cache[h] = NULL; |
| 901 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 902 | |
| 903 | /* suppress this TB from the two jump lists */ |
| 904 | tb_jmp_remove(tb, 0); |
| 905 | tb_jmp_remove(tb, 1); |
| 906 | |
| 907 | /* suppress any remaining jumps to this TB */ |
| 908 | tb1 = tb->jmp_first; |
| 909 | for(;;) { |
| 910 | n1 = (long)tb1 & 3; |
| 911 | if (n1 == 2) |
| 912 | break; |
| 913 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 914 | tb2 = tb1->jmp_next[n1]; |
| 915 | tb_reset_jump(tb1, n1); |
| 916 | tb1->jmp_next[n1] = NULL; |
| 917 | tb1 = tb2; |
| 918 | } |
| 919 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */ |
| 920 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 921 | tb_phys_invalidate_count++; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 922 | } |
| 923 | |
| 924 | static inline void set_bits(uint8_t *tab, int start, int len) |
| 925 | { |
| 926 | int end, mask, end1; |
| 927 | |
| 928 | end = start + len; |
| 929 | tab += start >> 3; |
| 930 | mask = 0xff << (start & 7); |
| 931 | if ((start & ~7) == (end & ~7)) { |
| 932 | if (start < end) { |
| 933 | mask &= ~(0xff << (end & 7)); |
| 934 | *tab |= mask; |
| 935 | } |
| 936 | } else { |
| 937 | *tab++ |= mask; |
| 938 | start = (start + 8) & ~7; |
| 939 | end1 = end & ~7; |
| 940 | while (start < end1) { |
| 941 | *tab++ = 0xff; |
| 942 | start += 8; |
| 943 | } |
| 944 | if (start < end) { |
| 945 | mask = ~(0xff << (end & 7)); |
| 946 | *tab |= mask; |
| 947 | } |
| 948 | } |
| 949 | } |
| 950 | |
| 951 | static void build_page_bitmap(PageDesc *p) |
| 952 | { |
| 953 | int n, tb_start, tb_end; |
| 954 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 955 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 956 | p->code_bitmap = g_malloc0(TARGET_PAGE_SIZE / 8); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 957 | |
| 958 | tb = p->first_tb; |
| 959 | while (tb != NULL) { |
| 960 | n = (long)tb & 3; |
| 961 | tb = (TranslationBlock *)((long)tb & ~3); |
| 962 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 963 | if (n == 0) { |
| 964 | /* NOTE: tb_end may be after the end of the page, but |
| 965 | it is not a problem */ |
| 966 | tb_start = tb->pc & ~TARGET_PAGE_MASK; |
| 967 | tb_end = tb_start + tb->size; |
| 968 | if (tb_end > TARGET_PAGE_SIZE) |
| 969 | tb_end = TARGET_PAGE_SIZE; |
| 970 | } else { |
| 971 | tb_start = 0; |
| 972 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 973 | } |
| 974 | set_bits(p->code_bitmap, tb_start, tb_end - tb_start); |
| 975 | tb = tb->page_next[n]; |
| 976 | } |
| 977 | } |
| 978 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 979 | TranslationBlock *tb_gen_code(CPUState *env, |
| 980 | target_ulong pc, target_ulong cs_base, |
| 981 | int flags, int cflags) |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 982 | { |
| 983 | TranslationBlock *tb; |
| 984 | uint8_t *tc_ptr; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 985 | tb_page_addr_t phys_pc, phys_page2; |
| 986 | target_ulong virt_page2; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 987 | int code_gen_size; |
| 988 | |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 989 | phys_pc = get_page_addr_code(env, pc); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 990 | tb = tb_alloc(pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 991 | if (!tb) { |
| 992 | /* flush must be done */ |
| 993 | tb_flush(env); |
| 994 | /* cannot fail at this point */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 995 | tb = tb_alloc(pc); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 996 | /* Don't forget to invalidate previous TB info. */ |
| 997 | tb_invalidated_flag = 1; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 998 | } |
| 999 | tc_ptr = code_gen_ptr; |
| 1000 | tb->tc_ptr = tc_ptr; |
| 1001 | tb->cs_base = cs_base; |
| 1002 | tb->flags = flags; |
| 1003 | tb->cflags = cflags; |
blueswir1 | d07bde8 | 2007-12-11 19:35:45 +0000 | [diff] [blame] | 1004 | cpu_gen_code(env, tb, &code_gen_size); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1005 | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1006 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1007 | /* check next page if needed */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1008 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1009 | phys_page2 = -1; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1010 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1011 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1012 | } |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1013 | tb_link_page(tb, phys_pc, phys_page2); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1014 | return tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1015 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1016 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1017 | /* invalidate all TBs which intersect with the target physical page |
| 1018 | starting in range [start;end[. NOTE: start and end must refer to |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1019 | the same physical page. 'is_cpu_write_access' should be true if called |
| 1020 | from a real cpu write access: the virtual CPU will exit the current |
| 1021 | TB if code is modified inside this TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1022 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1023 | int is_cpu_write_access) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1024 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1025 | TranslationBlock *tb, *tb_next, *saved_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1026 | CPUState *env = cpu_single_env; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1027 | tb_page_addr_t tb_start, tb_end; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1028 | PageDesc *p; |
| 1029 | int n; |
| 1030 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1031 | int current_tb_not_found = is_cpu_write_access; |
| 1032 | TranslationBlock *current_tb = NULL; |
| 1033 | int current_tb_modified = 0; |
| 1034 | target_ulong current_pc = 0; |
| 1035 | target_ulong current_cs_base = 0; |
| 1036 | int current_flags = 0; |
| 1037 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1038 | |
| 1039 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1040 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1041 | return; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1042 | if (!p->code_bitmap && |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1043 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD && |
| 1044 | is_cpu_write_access) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1045 | /* build code bitmap */ |
| 1046 | build_page_bitmap(p); |
| 1047 | } |
| 1048 | |
| 1049 | /* we remove all the TBs in the range [start, end[ */ |
| 1050 | /* XXX: see if in some cases it could be faster to invalidate all the code */ |
| 1051 | tb = p->first_tb; |
| 1052 | while (tb != NULL) { |
| 1053 | n = (long)tb & 3; |
| 1054 | tb = (TranslationBlock *)((long)tb & ~3); |
| 1055 | tb_next = tb->page_next[n]; |
| 1056 | /* NOTE: this is subtle as a TB may span two physical pages */ |
| 1057 | if (n == 0) { |
| 1058 | /* NOTE: tb_end may be after the end of the page, but |
| 1059 | it is not a problem */ |
| 1060 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); |
| 1061 | tb_end = tb_start + tb->size; |
| 1062 | } else { |
| 1063 | tb_start = tb->page_addr[1]; |
| 1064 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); |
| 1065 | } |
| 1066 | if (!(tb_end <= start || tb_start >= end)) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1067 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1068 | if (current_tb_not_found) { |
| 1069 | current_tb_not_found = 0; |
| 1070 | current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1071 | if (env->mem_io_pc) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1072 | /* now we have a real cpu fault */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1073 | current_tb = tb_find_pc(env->mem_io_pc); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1074 | } |
| 1075 | } |
| 1076 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1077 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1078 | /* If we are modifying the current TB, we must stop |
| 1079 | its execution. We could be more precise by checking |
| 1080 | that the modification is after the current PC, but it |
| 1081 | would require a specialized function to partially |
| 1082 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1083 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1084 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1085 | cpu_restore_state(current_tb, env, env->mem_io_pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1086 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1087 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1088 | } |
| 1089 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1090 | /* we need to do that to handle the case where a signal |
| 1091 | occurs while doing tb_phys_invalidate() */ |
| 1092 | saved_tb = NULL; |
| 1093 | if (env) { |
| 1094 | saved_tb = env->current_tb; |
| 1095 | env->current_tb = NULL; |
| 1096 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1097 | tb_phys_invalidate(tb, -1); |
bellard | 6f5a9f7 | 2005-11-26 20:12:28 +0000 | [diff] [blame] | 1098 | if (env) { |
| 1099 | env->current_tb = saved_tb; |
| 1100 | if (env->interrupt_request && env->current_tb) |
| 1101 | cpu_interrupt(env, env->interrupt_request); |
| 1102 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1103 | } |
| 1104 | tb = tb_next; |
| 1105 | } |
| 1106 | #if !defined(CONFIG_USER_ONLY) |
| 1107 | /* if no code remaining, no need to continue to use slow writes */ |
| 1108 | if (!p->first_tb) { |
| 1109 | invalidate_page_bitmap(p); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1110 | if (is_cpu_write_access) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1111 | tlb_unprotect_code_phys(env, start, env->mem_io_vaddr); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1112 | } |
| 1113 | } |
| 1114 | #endif |
| 1115 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1116 | if (current_tb_modified) { |
| 1117 | /* we generate a block containing just the instruction |
| 1118 | modifying the memory. It will ensure that it cannot modify |
| 1119 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1120 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1121 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1122 | cpu_resume_from_signal(env, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1123 | } |
| 1124 | #endif |
| 1125 | } |
| 1126 | |
| 1127 | /* len must be <= 8 and start must be a multiple of len */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1128 | static inline void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1129 | { |
| 1130 | PageDesc *p; |
| 1131 | int offset, b; |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1132 | #if 0 |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 1133 | if (1) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1134 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", |
| 1135 | cpu_single_env->mem_io_vaddr, len, |
| 1136 | cpu_single_env->eip, |
| 1137 | cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base); |
bellard | 59817cc | 2004-02-16 22:01:13 +0000 | [diff] [blame] | 1138 | } |
| 1139 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1140 | p = page_find(start >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1141 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1142 | return; |
| 1143 | if (p->code_bitmap) { |
| 1144 | offset = start & ~TARGET_PAGE_MASK; |
| 1145 | b = p->code_bitmap[offset >> 3] >> (offset & 7); |
| 1146 | if (b & ((1 << len) - 1)) |
| 1147 | goto do_invalidate; |
| 1148 | } else { |
| 1149 | do_invalidate: |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1150 | tb_invalidate_phys_page_range(start, start + len, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1151 | } |
| 1152 | } |
| 1153 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1154 | #if !defined(CONFIG_SOFTMMU) |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1155 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1156 | unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1157 | { |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1158 | TranslationBlock *tb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1159 | PageDesc *p; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1160 | int n; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1161 | #ifdef TARGET_HAS_PRECISE_SMC |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1162 | TranslationBlock *current_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1163 | CPUState *env = cpu_single_env; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1164 | int current_tb_modified = 0; |
| 1165 | target_ulong current_pc = 0; |
| 1166 | target_ulong current_cs_base = 0; |
| 1167 | int current_flags = 0; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1168 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1169 | |
| 1170 | addr &= TARGET_PAGE_MASK; |
| 1171 | p = page_find(addr >> TARGET_PAGE_BITS); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1172 | if (!p) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1173 | return; |
| 1174 | tb = p->first_tb; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1175 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1176 | if (tb && pc != 0) { |
| 1177 | current_tb = tb_find_pc(pc); |
| 1178 | } |
| 1179 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1180 | while (tb != NULL) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1181 | n = (long)tb & 3; |
| 1182 | tb = (TranslationBlock *)((long)tb & ~3); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1183 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1184 | if (current_tb == tb && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1185 | (current_tb->cflags & CF_COUNT_MASK) != 1) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1186 | /* If we are modifying the current TB, we must stop |
| 1187 | its execution. We could be more precise by checking |
| 1188 | that the modification is after the current PC, but it |
| 1189 | would require a specialized function to partially |
| 1190 | restore the CPU state */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1191 | |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1192 | current_tb_modified = 1; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 1193 | cpu_restore_state(current_tb, env, pc); |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 1194 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
| 1195 | ¤t_flags); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1196 | } |
| 1197 | #endif /* TARGET_HAS_PRECISE_SMC */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1198 | tb_phys_invalidate(tb, addr); |
| 1199 | tb = tb->page_next[n]; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1200 | } |
| 1201 | p->first_tb = NULL; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1202 | #ifdef TARGET_HAS_PRECISE_SMC |
| 1203 | if (current_tb_modified) { |
| 1204 | /* we generate a block containing just the instruction |
| 1205 | modifying the memory. It will ensure that it cannot modify |
| 1206 | itself */ |
bellard | ea1c180 | 2004-06-14 18:56:36 +0000 | [diff] [blame] | 1207 | env->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1208 | tb_gen_code(env, current_pc, current_cs_base, current_flags, 1); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1209 | cpu_resume_from_signal(env, puc); |
| 1210 | } |
| 1211 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1212 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1213 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1214 | |
| 1215 | /* add the tb in the target page and protect it if necessary */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1216 | static inline void tb_alloc_page(TranslationBlock *tb, |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1217 | unsigned int n, tb_page_addr_t page_addr) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1218 | { |
| 1219 | PageDesc *p; |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1220 | #ifndef CONFIG_USER_ONLY |
| 1221 | bool page_already_protected; |
| 1222 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1223 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1224 | tb->page_addr[n] = page_addr; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1225 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1226 | tb->page_next[n] = p->first_tb; |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1227 | #ifndef CONFIG_USER_ONLY |
| 1228 | page_already_protected = p->first_tb != NULL; |
| 1229 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1230 | p->first_tb = (TranslationBlock *)((long)tb | n); |
| 1231 | invalidate_page_bitmap(p); |
| 1232 | |
bellard | 107db44 | 2004-06-22 18:48:46 +0000 | [diff] [blame] | 1233 | #if defined(TARGET_HAS_SMC) || 1 |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1234 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1235 | #if defined(CONFIG_USER_ONLY) |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1236 | if (p->flags & PAGE_WRITE) { |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1237 | target_ulong addr; |
| 1238 | PageDesc *p2; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1239 | int prot; |
| 1240 | |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1241 | /* force the host page as non writable (writes will have a |
| 1242 | page fault + mprotect overhead) */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1243 | page_addr &= qemu_host_page_mask; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1244 | prot = 0; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1245 | for(addr = page_addr; addr < page_addr + qemu_host_page_size; |
| 1246 | addr += TARGET_PAGE_SIZE) { |
| 1247 | |
| 1248 | p2 = page_find (addr >> TARGET_PAGE_BITS); |
| 1249 | if (!p2) |
| 1250 | continue; |
| 1251 | prot |= p2->flags; |
| 1252 | p2->flags &= ~PAGE_WRITE; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1253 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1254 | mprotect(g2h(page_addr), qemu_host_page_size, |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1255 | (prot & PAGE_BITS) & ~PAGE_WRITE); |
| 1256 | #ifdef DEBUG_TB_INVALIDATE |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 1257 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 1258 | page_addr); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1259 | #endif |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1260 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1261 | #else |
| 1262 | /* if some code is already present, then the pages are already |
| 1263 | protected. So we handle the case where only the first TB is |
| 1264 | allocated in a physical page */ |
Juan Quintela | 4429ab4 | 2011-06-02 01:53:44 +0000 | [diff] [blame] | 1265 | if (!page_already_protected) { |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 1266 | tlb_protect_code(page_addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1267 | } |
| 1268 | #endif |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1269 | |
| 1270 | #endif /* TARGET_HAS_SMC */ |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1273 | /* add a new TB and link it to the physical page tables. phys_page2 is |
| 1274 | (-1) to indicate that only one page contains the TB. */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 1275 | void tb_link_page(TranslationBlock *tb, |
| 1276 | tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1277 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1278 | unsigned int h; |
| 1279 | TranslationBlock **ptb; |
| 1280 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1281 | /* Grab the mmap lock to stop another thread invalidating this TB |
| 1282 | before we are done. */ |
| 1283 | mmap_lock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1284 | /* add in the physical hash table */ |
| 1285 | h = tb_phys_hash_func(phys_pc); |
| 1286 | ptb = &tb_phys_hash[h]; |
| 1287 | tb->phys_hash_next = *ptb; |
| 1288 | *ptb = tb; |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1289 | |
| 1290 | /* add in the page list */ |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1291 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); |
| 1292 | if (phys_page2 != -1) |
| 1293 | tb_alloc_page(tb, 1, phys_page2); |
| 1294 | else |
| 1295 | tb->page_addr[1] = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1296 | |
bellard | d4e8164 | 2003-05-25 16:46:15 +0000 | [diff] [blame] | 1297 | tb->jmp_first = (TranslationBlock *)((long)tb | 2); |
| 1298 | tb->jmp_next[0] = NULL; |
| 1299 | tb->jmp_next[1] = NULL; |
| 1300 | |
| 1301 | /* init original jump addresses */ |
| 1302 | if (tb->tb_next_offset[0] != 0xffff) |
| 1303 | tb_reset_jump(tb, 0); |
| 1304 | if (tb->tb_next_offset[1] != 0xffff) |
| 1305 | tb_reset_jump(tb, 1); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 1306 | |
| 1307 | #ifdef DEBUG_TB_CHECK |
| 1308 | tb_page_check(); |
| 1309 | #endif |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 1310 | mmap_unlock(); |
bellard | fd6ce8f | 2003-05-14 19:00:11 +0000 | [diff] [blame] | 1311 | } |
| 1312 | |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1313 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
| 1314 | tb[1].tc_ptr. Return NULL if not found */ |
| 1315 | TranslationBlock *tb_find_pc(unsigned long tc_ptr) |
| 1316 | { |
| 1317 | int m_min, m_max, m; |
| 1318 | unsigned long v; |
| 1319 | TranslationBlock *tb; |
| 1320 | |
| 1321 | if (nb_tbs <= 0) |
| 1322 | return NULL; |
| 1323 | if (tc_ptr < (unsigned long)code_gen_buffer || |
| 1324 | tc_ptr >= (unsigned long)code_gen_ptr) |
| 1325 | return NULL; |
| 1326 | /* binary search (cf Knuth) */ |
| 1327 | m_min = 0; |
| 1328 | m_max = nb_tbs - 1; |
| 1329 | while (m_min <= m_max) { |
| 1330 | m = (m_min + m_max) >> 1; |
| 1331 | tb = &tbs[m]; |
| 1332 | v = (unsigned long)tb->tc_ptr; |
| 1333 | if (v == tc_ptr) |
| 1334 | return tb; |
| 1335 | else if (tc_ptr < v) { |
| 1336 | m_max = m - 1; |
| 1337 | } else { |
| 1338 | m_min = m + 1; |
| 1339 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1340 | } |
bellard | a513fe1 | 2003-05-27 23:29:48 +0000 | [diff] [blame] | 1341 | return &tbs[m_max]; |
| 1342 | } |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1343 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1344 | static void tb_reset_jump_recursive(TranslationBlock *tb); |
| 1345 | |
| 1346 | static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n) |
| 1347 | { |
| 1348 | TranslationBlock *tb1, *tb_next, **ptb; |
| 1349 | unsigned int n1; |
| 1350 | |
| 1351 | tb1 = tb->jmp_next[n]; |
| 1352 | if (tb1 != NULL) { |
| 1353 | /* find head of list */ |
| 1354 | for(;;) { |
| 1355 | n1 = (long)tb1 & 3; |
| 1356 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1357 | if (n1 == 2) |
| 1358 | break; |
| 1359 | tb1 = tb1->jmp_next[n1]; |
| 1360 | } |
| 1361 | /* we are now sure now that tb jumps to tb1 */ |
| 1362 | tb_next = tb1; |
| 1363 | |
| 1364 | /* remove tb from the jmp_first list */ |
| 1365 | ptb = &tb_next->jmp_first; |
| 1366 | for(;;) { |
| 1367 | tb1 = *ptb; |
| 1368 | n1 = (long)tb1 & 3; |
| 1369 | tb1 = (TranslationBlock *)((long)tb1 & ~3); |
| 1370 | if (n1 == n && tb1 == tb) |
| 1371 | break; |
| 1372 | ptb = &tb1->jmp_next[n1]; |
| 1373 | } |
| 1374 | *ptb = tb->jmp_next[n]; |
| 1375 | tb->jmp_next[n] = NULL; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1376 | |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1377 | /* suppress the jump to next tb in generated code */ |
| 1378 | tb_reset_jump(tb, n); |
| 1379 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1380 | /* suppress jumps in the tb on which we could have jumped */ |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1381 | tb_reset_jump_recursive(tb_next); |
| 1382 | } |
| 1383 | } |
| 1384 | |
| 1385 | static void tb_reset_jump_recursive(TranslationBlock *tb) |
| 1386 | { |
| 1387 | tb_reset_jump_recursive2(tb, 0); |
| 1388 | tb_reset_jump_recursive2(tb, 1); |
| 1389 | } |
| 1390 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1391 | #if defined(TARGET_HAS_ICE) |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1392 | #if defined(CONFIG_USER_ONLY) |
| 1393 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1394 | { |
| 1395 | tb_invalidate_phys_page_range(pc, pc + 1, 0); |
| 1396 | } |
| 1397 | #else |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1398 | static void breakpoint_invalidate(CPUState *env, target_ulong pc) |
| 1399 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1400 | target_phys_addr_t addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 1401 | target_ulong pd; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1402 | ram_addr_t ram_addr; |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1403 | PhysPageDesc *p; |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1404 | |
pbrook | c2f07f8 | 2006-04-08 17:14:56 +0000 | [diff] [blame] | 1405 | addr = cpu_get_phys_page_debug(env, pc); |
| 1406 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 1407 | if (!p) { |
| 1408 | pd = IO_MEM_UNASSIGNED; |
| 1409 | } else { |
| 1410 | pd = p->phys_offset; |
| 1411 | } |
| 1412 | ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK); |
pbrook | 706cd4b | 2006-04-08 17:36:21 +0000 | [diff] [blame] | 1413 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1414 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 1415 | #endif |
Paul Brook | 94df27f | 2010-02-28 23:47:45 +0000 | [diff] [blame] | 1416 | #endif /* TARGET_HAS_ICE */ |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1417 | |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1418 | #if defined(CONFIG_USER_ONLY) |
| 1419 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1420 | |
| 1421 | { |
| 1422 | } |
| 1423 | |
| 1424 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1425 | int flags, CPUWatchpoint **watchpoint) |
| 1426 | { |
| 1427 | return -ENOSYS; |
| 1428 | } |
| 1429 | #else |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1430 | /* Add a watchpoint. */ |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1431 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len, |
| 1432 | int flags, CPUWatchpoint **watchpoint) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1433 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1434 | target_ulong len_mask = ~(len - 1); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1435 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1436 | |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1437 | /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ |
| 1438 | if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) { |
| 1439 | fprintf(stderr, "qemu: tried to set invalid watchpoint at " |
| 1440 | TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); |
| 1441 | return -EINVAL; |
| 1442 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1443 | wp = g_malloc(sizeof(*wp)); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1444 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1445 | wp->vaddr = addr; |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1446 | wp->len_mask = len_mask; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1447 | wp->flags = flags; |
| 1448 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1449 | /* keep all GDB-injected watchpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1450 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1451 | QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1452 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1453 | QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1454 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1455 | tlb_flush_page(env, addr); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1456 | |
| 1457 | if (watchpoint) |
| 1458 | *watchpoint = wp; |
| 1459 | return 0; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1460 | } |
| 1461 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1462 | /* Remove a specific watchpoint. */ |
| 1463 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len, |
| 1464 | int flags) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1465 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1466 | target_ulong len_mask = ~(len - 1); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1467 | CPUWatchpoint *wp; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1468 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1469 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 1470 | if (addr == wp->vaddr && len_mask == wp->len_mask |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 1471 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1472 | cpu_watchpoint_remove_by_ref(env, wp); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1473 | return 0; |
| 1474 | } |
| 1475 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1476 | return -ENOENT; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 1477 | } |
| 1478 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1479 | /* Remove a specific watchpoint by reference. */ |
| 1480 | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint) |
| 1481 | { |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1482 | QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1483 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1484 | tlb_flush_page(env, watchpoint->vaddr); |
| 1485 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1486 | g_free(watchpoint); |
edgar_igl | 7d03f82 | 2008-05-17 18:58:29 +0000 | [diff] [blame] | 1487 | } |
| 1488 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1489 | /* Remove all matching watchpoints. */ |
| 1490 | void cpu_watchpoint_remove_all(CPUState *env, int mask) |
| 1491 | { |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1492 | CPUWatchpoint *wp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1493 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1494 | QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1495 | if (wp->flags & mask) |
| 1496 | cpu_watchpoint_remove_by_ref(env, wp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1497 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1498 | } |
Paul Brook | c527ee8 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 1499 | #endif |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1500 | |
| 1501 | /* Add a breakpoint. */ |
| 1502 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
| 1503 | CPUBreakpoint **breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1504 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1505 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1506 | CPUBreakpoint *bp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1507 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1508 | bp = g_malloc(sizeof(*bp)); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1509 | |
| 1510 | bp->pc = pc; |
| 1511 | bp->flags = flags; |
| 1512 | |
aliguori | 2dc9f41 | 2008-11-18 20:56:59 +0000 | [diff] [blame] | 1513 | /* keep all GDB-injected breakpoints in front */ |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1514 | if (flags & BP_GDB) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1515 | QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1516 | else |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1517 | QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1518 | |
| 1519 | breakpoint_invalidate(env, pc); |
| 1520 | |
| 1521 | if (breakpoint) |
| 1522 | *breakpoint = bp; |
| 1523 | return 0; |
| 1524 | #else |
| 1525 | return -ENOSYS; |
| 1526 | #endif |
| 1527 | } |
| 1528 | |
| 1529 | /* Remove a specific breakpoint. */ |
| 1530 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags) |
| 1531 | { |
| 1532 | #if defined(TARGET_HAS_ICE) |
| 1533 | CPUBreakpoint *bp; |
| 1534 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1535 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1536 | if (bp->pc == pc && bp->flags == flags) { |
| 1537 | cpu_breakpoint_remove_by_ref(env, bp); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1538 | return 0; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1539 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1540 | } |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1541 | return -ENOENT; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1542 | #else |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1543 | return -ENOSYS; |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1544 | #endif |
| 1545 | } |
| 1546 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1547 | /* Remove a specific breakpoint by reference. */ |
| 1548 | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint) |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1549 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1550 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1551 | QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 1552 | |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1553 | breakpoint_invalidate(env, breakpoint->pc); |
| 1554 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1555 | g_free(breakpoint); |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1556 | #endif |
| 1557 | } |
| 1558 | |
| 1559 | /* Remove all matching breakpoints. */ |
| 1560 | void cpu_breakpoint_remove_all(CPUState *env, int mask) |
| 1561 | { |
| 1562 | #if defined(TARGET_HAS_ICE) |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1563 | CPUBreakpoint *bp, *next; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1564 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1565 | QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 1566 | if (bp->flags & mask) |
| 1567 | cpu_breakpoint_remove_by_ref(env, bp); |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 1568 | } |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 1569 | #endif |
| 1570 | } |
| 1571 | |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1572 | /* enable or disable single step mode. EXCP_DEBUG is returned by the |
| 1573 | CPU loop after each instruction */ |
| 1574 | void cpu_single_step(CPUState *env, int enabled) |
| 1575 | { |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 1576 | #if defined(TARGET_HAS_ICE) |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1577 | if (env->singlestep_enabled != enabled) { |
| 1578 | env->singlestep_enabled = enabled; |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1579 | if (kvm_enabled()) |
| 1580 | kvm_update_guest_debug(env, 0); |
| 1581 | else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 1582 | /* must flush all the translated code to avoid inconsistencies */ |
aliguori | e22a25c | 2009-03-12 20:12:48 +0000 | [diff] [blame] | 1583 | /* XXX: only flush what is necessary */ |
| 1584 | tb_flush(env); |
| 1585 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1586 | } |
| 1587 | #endif |
| 1588 | } |
| 1589 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1590 | /* enable or disable low levels log */ |
| 1591 | void cpu_set_log(int log_flags) |
| 1592 | { |
| 1593 | loglevel = log_flags; |
| 1594 | if (loglevel && !logfile) { |
pbrook | 11fcfab | 2007-07-01 18:21:11 +0000 | [diff] [blame] | 1595 | logfile = fopen(logfilename, log_append ? "a" : "w"); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1596 | if (!logfile) { |
| 1597 | perror(logfilename); |
| 1598 | _exit(1); |
| 1599 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1600 | #if !defined(CONFIG_SOFTMMU) |
| 1601 | /* must avoid mmap() usage of glibc by setting a buffer "by hand" */ |
| 1602 | { |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1603 | static char logfile_buf[4096]; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1604 | setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf)); |
| 1605 | } |
Filip Navara | bf65f53 | 2009-07-27 10:02:04 -0500 | [diff] [blame] | 1606 | #elif !defined(_WIN32) |
| 1607 | /* Win32 doesn't support line-buffering and requires size >= 2 */ |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1608 | setvbuf(logfile, NULL, _IOLBF, 0); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1609 | #endif |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1610 | log_append = 1; |
| 1611 | } |
| 1612 | if (!loglevel && logfile) { |
| 1613 | fclose(logfile); |
| 1614 | logfile = NULL; |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1615 | } |
| 1616 | } |
| 1617 | |
| 1618 | void cpu_set_log_filename(const char *filename) |
| 1619 | { |
| 1620 | logfilename = strdup(filename); |
pbrook | e735b91 | 2007-06-30 13:53:24 +0000 | [diff] [blame] | 1621 | if (logfile) { |
| 1622 | fclose(logfile); |
| 1623 | logfile = NULL; |
| 1624 | } |
| 1625 | cpu_set_log(loglevel); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 1626 | } |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 1627 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1628 | static void cpu_unlink_tb(CPUState *env) |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1629 | { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 1630 | /* FIXME: TB unchaining isn't SMP safe. For now just ignore the |
| 1631 | problem and hope the cpu will stop of its own accord. For userspace |
| 1632 | emulation this often isn't actually as bad as it sounds. Often |
| 1633 | signals are used primarily to interrupt blocking syscalls. */ |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1634 | TranslationBlock *tb; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1635 | static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED; |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1636 | |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1637 | spin_lock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1638 | tb = env->current_tb; |
| 1639 | /* if the cpu is currently executing code, we must unlink it and |
| 1640 | all the potentially executing TB */ |
Riku Voipio | f76cfe5 | 2009-12-04 15:16:30 +0200 | [diff] [blame] | 1641 | if (tb) { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1642 | env->current_tb = NULL; |
| 1643 | tb_reset_jump_recursive(tb); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1644 | } |
Riku Voipio | cab1b4b | 2010-01-20 12:56:27 +0200 | [diff] [blame] | 1645 | spin_unlock(&interrupt_lock); |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1646 | } |
| 1647 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1648 | #ifndef CONFIG_USER_ONLY |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1649 | /* mask must never be zero, except for A20 change call */ |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1650 | static void tcg_handle_interrupt(CPUState *env, int mask) |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1651 | { |
| 1652 | int old_mask; |
| 1653 | |
| 1654 | old_mask = env->interrupt_request; |
| 1655 | env->interrupt_request |= mask; |
| 1656 | |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1657 | /* |
| 1658 | * If called from iothread context, wake the target cpu in |
| 1659 | * case its halted. |
| 1660 | */ |
Jan Kiszka | b7680cb | 2011-03-12 17:43:51 +0100 | [diff] [blame] | 1661 | if (!qemu_cpu_is_self(env)) { |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1662 | qemu_cpu_kick(env); |
| 1663 | return; |
| 1664 | } |
aliguori | 8edac96 | 2009-04-24 18:03:45 +0000 | [diff] [blame] | 1665 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1666 | if (use_icount) { |
pbrook | 266910c | 2008-07-09 15:31:50 +0000 | [diff] [blame] | 1667 | env->icount_decr.u16.high = 0xffff; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1668 | if (!can_do_io(env) |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 1669 | && (mask & ~old_mask) != 0) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1670 | cpu_abort(env, "Raised interrupt while not in I/O function"); |
| 1671 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1672 | } else { |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1673 | cpu_unlink_tb(env); |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1674 | } |
| 1675 | } |
| 1676 | |
Jan Kiszka | ec6959d | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1677 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; |
| 1678 | |
Jan Kiszka | 97ffbd8 | 2011-04-13 01:32:56 +0200 | [diff] [blame] | 1679 | #else /* CONFIG_USER_ONLY */ |
| 1680 | |
| 1681 | void cpu_interrupt(CPUState *env, int mask) |
| 1682 | { |
| 1683 | env->interrupt_request |= mask; |
| 1684 | cpu_unlink_tb(env); |
| 1685 | } |
| 1686 | #endif /* CONFIG_USER_ONLY */ |
| 1687 | |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 1688 | void cpu_reset_interrupt(CPUState *env, int mask) |
| 1689 | { |
| 1690 | env->interrupt_request &= ~mask; |
| 1691 | } |
| 1692 | |
aurel32 | 3098dba | 2009-03-07 21:28:24 +0000 | [diff] [blame] | 1693 | void cpu_exit(CPUState *env) |
| 1694 | { |
| 1695 | env->exit_request = 1; |
| 1696 | cpu_unlink_tb(env); |
| 1697 | } |
| 1698 | |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1699 | const CPULogItem cpu_log_items[] = { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1700 | { CPU_LOG_TB_OUT_ASM, "out_asm", |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1701 | "show generated host assembly code for each compiled TB" }, |
| 1702 | { CPU_LOG_TB_IN_ASM, "in_asm", |
| 1703 | "show target assembly code for each compiled TB" }, |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1704 | { CPU_LOG_TB_OP, "op", |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 1705 | "show micro ops for each compiled TB" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1706 | { CPU_LOG_TB_OP_OPT, "op_opt", |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1707 | "show micro ops " |
| 1708 | #ifdef TARGET_I386 |
| 1709 | "before eflags optimization and " |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1710 | #endif |
blueswir1 | e01a115 | 2008-03-14 17:37:11 +0000 | [diff] [blame] | 1711 | "after liveness analysis" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1712 | { CPU_LOG_INT, "int", |
| 1713 | "show interrupts/exceptions in short format" }, |
| 1714 | { CPU_LOG_EXEC, "exec", |
| 1715 | "show trace before each executed TB (lots of logs)" }, |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1716 | { CPU_LOG_TB_CPU, "cpu", |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 1717 | "show CPU state before block translation" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1718 | #ifdef TARGET_I386 |
| 1719 | { CPU_LOG_PCALL, "pcall", |
| 1720 | "show protected mode far calls/returns/exceptions" }, |
aliguori | eca1bdf | 2009-01-26 19:54:31 +0000 | [diff] [blame] | 1721 | { CPU_LOG_RESET, "cpu_reset", |
| 1722 | "show CPU state before CPU resets" }, |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1723 | #endif |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1724 | #ifdef DEBUG_IOPORT |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 1725 | { CPU_LOG_IOPORT, "ioport", |
| 1726 | "show all i/o ports accesses" }, |
bellard | 8e3a9fd | 2004-10-09 17:32:58 +0000 | [diff] [blame] | 1727 | #endif |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1728 | { 0, NULL, NULL }, |
| 1729 | }; |
| 1730 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1731 | #ifndef CONFIG_USER_ONLY |
| 1732 | static QLIST_HEAD(memory_client_list, CPUPhysMemoryClient) memory_client_list |
| 1733 | = QLIST_HEAD_INITIALIZER(memory_client_list); |
| 1734 | |
| 1735 | static void cpu_notify_set_memory(target_phys_addr_t start_addr, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1736 | ram_addr_t size, |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 1737 | ram_addr_t phys_offset, |
| 1738 | bool log_dirty) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1739 | { |
| 1740 | CPUPhysMemoryClient *client; |
| 1741 | QLIST_FOREACH(client, &memory_client_list, list) { |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 1742 | client->set_memory(client, start_addr, size, phys_offset, log_dirty); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1743 | } |
| 1744 | } |
| 1745 | |
| 1746 | static int cpu_notify_sync_dirty_bitmap(target_phys_addr_t start, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1747 | target_phys_addr_t end) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1748 | { |
| 1749 | CPUPhysMemoryClient *client; |
| 1750 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1751 | int r = client->sync_dirty_bitmap(client, start, end); |
| 1752 | if (r < 0) |
| 1753 | return r; |
| 1754 | } |
| 1755 | return 0; |
| 1756 | } |
| 1757 | |
| 1758 | static int cpu_notify_migration_log(int enable) |
| 1759 | { |
| 1760 | CPUPhysMemoryClient *client; |
| 1761 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 1762 | int r = client->migration_log(client, enable); |
| 1763 | if (r < 0) |
| 1764 | return r; |
| 1765 | } |
| 1766 | return 0; |
| 1767 | } |
| 1768 | |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1769 | struct last_map { |
| 1770 | target_phys_addr_t start_addr; |
| 1771 | ram_addr_t size; |
| 1772 | ram_addr_t phys_offset; |
| 1773 | }; |
| 1774 | |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1775 | /* The l1_phys_map provides the upper P_L1_BITs of the guest physical |
| 1776 | * address. Each intermediate table provides the next L2_BITs of guest |
| 1777 | * physical address space. The number of levels vary based on host and |
| 1778 | * guest configuration, making it efficient to build the final guest |
| 1779 | * physical address by seeding the L1 offset and shifting and adding in |
| 1780 | * each L2 offset as we recurse through them. */ |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1781 | static void phys_page_for_each_1(CPUPhysMemoryClient *client, int level, |
| 1782 | void **lp, target_phys_addr_t addr, |
| 1783 | struct last_map *map) |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1784 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1785 | int i; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1786 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1787 | if (*lp == NULL) { |
| 1788 | return; |
| 1789 | } |
| 1790 | if (level == 0) { |
| 1791 | PhysPageDesc *pd = *lp; |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1792 | addr <<= L2_BITS + TARGET_PAGE_BITS; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1793 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1794 | if (pd[i].phys_offset != IO_MEM_UNASSIGNED) { |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1795 | target_phys_addr_t start_addr = addr | i << TARGET_PAGE_BITS; |
| 1796 | |
| 1797 | if (map->size && |
| 1798 | start_addr == map->start_addr + map->size && |
| 1799 | pd[i].phys_offset == map->phys_offset + map->size) { |
| 1800 | |
| 1801 | map->size += TARGET_PAGE_SIZE; |
| 1802 | continue; |
| 1803 | } else if (map->size) { |
| 1804 | client->set_memory(client, map->start_addr, |
| 1805 | map->size, map->phys_offset, false); |
| 1806 | } |
| 1807 | |
| 1808 | map->start_addr = start_addr; |
| 1809 | map->size = TARGET_PAGE_SIZE; |
| 1810 | map->phys_offset = pd[i].phys_offset; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1811 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1812 | } |
| 1813 | } else { |
| 1814 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 1815 | for (i = 0; i < L2_SIZE; ++i) { |
Alex Williamson | 8d4c78e | 2011-05-03 12:36:46 -0600 | [diff] [blame] | 1816 | phys_page_for_each_1(client, level - 1, pp + i, |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1817 | (addr << L2_BITS) | i, map); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1818 | } |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | static void phys_page_for_each(CPUPhysMemoryClient *client) |
| 1823 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1824 | int i; |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1825 | struct last_map map = { }; |
| 1826 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 1827 | for (i = 0; i < P_L1_SIZE; ++i) { |
| 1828 | phys_page_for_each_1(client, P_L1_SHIFT / L2_BITS - 1, |
Alex Williamson | 2173a75 | 2011-05-03 12:36:58 -0600 | [diff] [blame] | 1829 | l1_phys_map + i, i, &map); |
| 1830 | } |
| 1831 | if (map.size) { |
| 1832 | client->set_memory(client, map.start_addr, map.size, map.phys_offset, |
| 1833 | false); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1834 | } |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 1835 | } |
| 1836 | |
| 1837 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *client) |
| 1838 | { |
| 1839 | QLIST_INSERT_HEAD(&memory_client_list, client, list); |
| 1840 | phys_page_for_each(client); |
| 1841 | } |
| 1842 | |
| 1843 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *client) |
| 1844 | { |
| 1845 | QLIST_REMOVE(client, list); |
| 1846 | } |
| 1847 | #endif |
| 1848 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1849 | static int cmp1(const char *s1, int n, const char *s2) |
| 1850 | { |
| 1851 | if (strlen(s2) != n) |
| 1852 | return 0; |
| 1853 | return memcmp(s1, s2, n) == 0; |
| 1854 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1855 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1856 | /* takes a comma separated list of log masks. Return 0 if error. */ |
| 1857 | int cpu_str_to_log_mask(const char *str) |
| 1858 | { |
blueswir1 | c7cd6a3 | 2008-10-02 18:27:46 +0000 | [diff] [blame] | 1859 | const CPULogItem *item; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1860 | int mask; |
| 1861 | const char *p, *p1; |
| 1862 | |
| 1863 | p = str; |
| 1864 | mask = 0; |
| 1865 | for(;;) { |
| 1866 | p1 = strchr(p, ','); |
| 1867 | if (!p1) |
| 1868 | p1 = p + strlen(p); |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1869 | if(cmp1(p,p1-p,"all")) { |
| 1870 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1871 | mask |= item->mask; |
| 1872 | } |
| 1873 | } else { |
| 1874 | for(item = cpu_log_items; item->mask != 0; item++) { |
| 1875 | if (cmp1(p, p1 - p, item->name)) |
| 1876 | goto found; |
| 1877 | } |
| 1878 | return 0; |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1879 | } |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 1880 | found: |
| 1881 | mask |= item->mask; |
| 1882 | if (*p1 != ',') |
| 1883 | break; |
| 1884 | p = p1 + 1; |
| 1885 | } |
| 1886 | return mask; |
| 1887 | } |
bellard | ea041c0 | 2003-06-25 16:16:50 +0000 | [diff] [blame] | 1888 | |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1889 | void cpu_abort(CPUState *env, const char *fmt, ...) |
| 1890 | { |
| 1891 | va_list ap; |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1892 | va_list ap2; |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1893 | |
| 1894 | va_start(ap, fmt); |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1895 | va_copy(ap2, ap); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1896 | fprintf(stderr, "qemu: fatal: "); |
| 1897 | vfprintf(stderr, fmt, ap); |
| 1898 | fprintf(stderr, "\n"); |
| 1899 | #ifdef TARGET_I386 |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 1900 | cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP); |
| 1901 | #else |
| 1902 | cpu_dump_state(env, stderr, fprintf, 0); |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1903 | #endif |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1904 | if (qemu_log_enabled()) { |
| 1905 | qemu_log("qemu: fatal: "); |
| 1906 | qemu_log_vprintf(fmt, ap2); |
| 1907 | qemu_log("\n"); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1908 | #ifdef TARGET_I386 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1909 | log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1910 | #else |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1911 | log_cpu_state(env, 0); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1912 | #endif |
aliguori | 31b1a7b | 2009-01-15 22:35:09 +0000 | [diff] [blame] | 1913 | qemu_log_flush(); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1914 | qemu_log_close(); |
balrog | 924edca | 2007-06-10 14:07:13 +0000 | [diff] [blame] | 1915 | } |
pbrook | 493ae1f | 2007-11-23 16:53:59 +0000 | [diff] [blame] | 1916 | va_end(ap2); |
j_mayer | f937329 | 2007-09-29 12:18:20 +0000 | [diff] [blame] | 1917 | va_end(ap); |
Riku Voipio | fd052bf | 2010-01-25 14:30:49 +0200 | [diff] [blame] | 1918 | #if defined(CONFIG_USER_ONLY) |
| 1919 | { |
| 1920 | struct sigaction act; |
| 1921 | sigfillset(&act.sa_mask); |
| 1922 | act.sa_handler = SIG_DFL; |
| 1923 | sigaction(SIGABRT, &act, NULL); |
| 1924 | } |
| 1925 | #endif |
bellard | 7501267 | 2003-06-21 13:11:07 +0000 | [diff] [blame] | 1926 | abort(); |
| 1927 | } |
| 1928 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1929 | CPUState *cpu_copy(CPUState *env) |
| 1930 | { |
ths | 01ba981 | 2007-12-09 02:22:57 +0000 | [diff] [blame] | 1931 | CPUState *new_env = cpu_init(env->cpu_model_str); |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1932 | CPUState *next_cpu = new_env->next_cpu; |
| 1933 | int cpu_index = new_env->cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1934 | #if defined(TARGET_HAS_ICE) |
| 1935 | CPUBreakpoint *bp; |
| 1936 | CPUWatchpoint *wp; |
| 1937 | #endif |
| 1938 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1939 | memcpy(new_env, env, sizeof(CPUState)); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1940 | |
| 1941 | /* Preserve chaining and index. */ |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1942 | new_env->next_cpu = next_cpu; |
| 1943 | new_env->cpu_index = cpu_index; |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1944 | |
| 1945 | /* Clone all break/watchpoints. |
| 1946 | Note: Once we support ptrace with hw-debug register access, make sure |
| 1947 | BP_CPU break/watchpoints are handled correctly on clone. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1948 | QTAILQ_INIT(&env->breakpoints); |
| 1949 | QTAILQ_INIT(&env->watchpoints); |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1950 | #if defined(TARGET_HAS_ICE) |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1951 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1952 | cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); |
| 1953 | } |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 1954 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | 5a38f08 | 2009-01-15 20:16:51 +0000 | [diff] [blame] | 1955 | cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, |
| 1956 | wp->flags, NULL); |
| 1957 | } |
| 1958 | #endif |
| 1959 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 1960 | return new_env; |
| 1961 | } |
| 1962 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1963 | #if !defined(CONFIG_USER_ONLY) |
| 1964 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1965 | static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr) |
| 1966 | { |
| 1967 | unsigned int i; |
| 1968 | |
| 1969 | /* Discard jump cache entries for any tb which might potentially |
| 1970 | overlap the flushed page. */ |
| 1971 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); |
| 1972 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1973 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1974 | |
| 1975 | i = tb_jmp_cache_hash_page(addr); |
| 1976 | memset (&env->tb_jmp_cache[i], 0, |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 1977 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 1978 | } |
| 1979 | |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 1980 | static CPUTLBEntry s_cputlb_empty_entry = { |
| 1981 | .addr_read = -1, |
| 1982 | .addr_write = -1, |
| 1983 | .addr_code = -1, |
| 1984 | .addend = -1, |
| 1985 | }; |
| 1986 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 1987 | /* NOTE: if flush_global is true, also flush global entries (not |
| 1988 | implemented yet) */ |
| 1989 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1990 | { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 1991 | int i; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1992 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 1993 | #if defined(DEBUG_TLB) |
| 1994 | printf("tlb_flush:\n"); |
| 1995 | #endif |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 1996 | /* must reset current TB so that interrupts cannot modify the |
| 1997 | links while we are modifying them */ |
| 1998 | env->current_tb = NULL; |
| 1999 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2000 | for(i = 0; i < CPU_TLB_SIZE; i++) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2001 | int mmu_idx; |
| 2002 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 2003 | env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2004 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2005 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2006 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 2007 | memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2008 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2009 | env->tlb_flush_addr = -1; |
| 2010 | env->tlb_flush_mask = 0; |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 2011 | tlb_flush_count++; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2012 | } |
| 2013 | |
bellard | 274da6b | 2004-05-20 21:56:27 +0000 | [diff] [blame] | 2014 | static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2015 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2016 | if (addr == (tlb_entry->addr_read & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2017 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2018 | addr == (tlb_entry->addr_write & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2019 | (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2020 | addr == (tlb_entry->addr_code & |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2021 | (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
Igor Kovalenko | 0873898 | 2009-07-12 02:15:40 +0400 | [diff] [blame] | 2022 | *tlb_entry = s_cputlb_empty_entry; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2023 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2024 | } |
| 2025 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2026 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2027 | { |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 2028 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2029 | int mmu_idx; |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2030 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2031 | #if defined(DEBUG_TLB) |
bellard | 108c49b | 2005-07-24 12:55:09 +0000 | [diff] [blame] | 2032 | printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2033 | #endif |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2034 | /* Check if we need to flush due to large pages. */ |
| 2035 | if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { |
| 2036 | #if defined(DEBUG_TLB) |
| 2037 | printf("tlb_flush_page: forced full flush (" |
| 2038 | TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", |
| 2039 | env->tlb_flush_addr, env->tlb_flush_mask); |
| 2040 | #endif |
| 2041 | tlb_flush(env, 1); |
| 2042 | return; |
| 2043 | } |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2044 | /* must reset current TB so that interrupts cannot modify the |
| 2045 | links while we are modifying them */ |
| 2046 | env->current_tb = NULL; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2047 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2048 | addr &= TARGET_PAGE_MASK; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2049 | i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2050 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2051 | tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2052 | |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2053 | tlb_flush_jmp_cache(env, addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2054 | } |
| 2055 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2056 | /* update the TLBs so that writes to code in the virtual page 'addr' |
| 2057 | can be detected */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2058 | static void tlb_protect_code(ram_addr_t ram_addr) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 2059 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2060 | cpu_physical_memory_reset_dirty(ram_addr, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2061 | ram_addr + TARGET_PAGE_SIZE, |
| 2062 | CODE_DIRTY_FLAG); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2063 | } |
| 2064 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2065 | /* update the TLB so that writes in physical page 'phys_addr' are no longer |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2066 | tested for self modifying code */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2067 | static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr, |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2068 | target_ulong vaddr) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2069 | { |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2070 | cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2071 | } |
| 2072 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2073 | static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2074 | unsigned long start, unsigned long length) |
| 2075 | { |
| 2076 | unsigned long addr; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2077 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
| 2078 | addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2079 | if ((addr - start) < length) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2080 | tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2081 | } |
| 2082 | } |
| 2083 | } |
| 2084 | |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2085 | /* Note: start and end must be within the same ram block. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2086 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 2087 | int dirty_flags) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2088 | { |
| 2089 | CPUState *env; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2090 | unsigned long length, start1; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2091 | int i; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2092 | |
| 2093 | start &= TARGET_PAGE_MASK; |
| 2094 | end = TARGET_PAGE_ALIGN(end); |
| 2095 | |
| 2096 | length = end - start; |
| 2097 | if (length == 0) |
| 2098 | return; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 2099 | cpu_physical_memory_mask_dirty_range(start, length, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 2100 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2101 | /* we modify the TLB cache so that the dirty bit will be set again |
| 2102 | when accessing the range */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2103 | start1 = (unsigned long)qemu_safe_ram_ptr(start); |
Stefan Weil | a57d23e | 2011-04-30 22:49:26 +0200 | [diff] [blame] | 2104 | /* Check that we don't span multiple blocks - this breaks the |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2105 | address comparisons below. */ |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 2106 | if ((unsigned long)qemu_safe_ram_ptr(end - 1) - start1 |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2107 | != (end - 1) - start) { |
| 2108 | abort(); |
| 2109 | } |
| 2110 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2111 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2112 | int mmu_idx; |
| 2113 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2114 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2115 | tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], |
| 2116 | start1, length); |
| 2117 | } |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2118 | } |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2119 | } |
| 2120 | |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2121 | int cpu_physical_memory_set_dirty_tracking(int enable) |
| 2122 | { |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2123 | int ret = 0; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2124 | in_migration = enable; |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2125 | ret = cpu_notify_migration_log(!!enable); |
| 2126 | return ret; |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 2127 | } |
| 2128 | |
| 2129 | int cpu_physical_memory_get_dirty_tracking(void) |
| 2130 | { |
| 2131 | return in_migration; |
| 2132 | } |
| 2133 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2134 | int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, |
| 2135 | target_phys_addr_t end_addr) |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2136 | { |
Michael S. Tsirkin | 7b8f3b7 | 2010-01-27 22:07:21 +0200 | [diff] [blame] | 2137 | int ret; |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2138 | |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2139 | ret = cpu_notify_sync_dirty_bitmap(start_addr, end_addr); |
Jan Kiszka | 151f774 | 2009-05-01 20:52:47 +0200 | [diff] [blame] | 2140 | return ret; |
aliguori | 2bec46d | 2008-11-24 20:21:41 +0000 | [diff] [blame] | 2141 | } |
| 2142 | |
Anthony PERARD | e5896b1 | 2011-02-07 12:19:23 +0100 | [diff] [blame] | 2143 | int cpu_physical_log_start(target_phys_addr_t start_addr, |
| 2144 | ram_addr_t size) |
| 2145 | { |
| 2146 | CPUPhysMemoryClient *client; |
| 2147 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 2148 | if (client->log_start) { |
| 2149 | int r = client->log_start(client, start_addr, size); |
| 2150 | if (r < 0) { |
| 2151 | return r; |
| 2152 | } |
| 2153 | } |
| 2154 | } |
| 2155 | return 0; |
| 2156 | } |
| 2157 | |
| 2158 | int cpu_physical_log_stop(target_phys_addr_t start_addr, |
| 2159 | ram_addr_t size) |
| 2160 | { |
| 2161 | CPUPhysMemoryClient *client; |
| 2162 | QLIST_FOREACH(client, &memory_client_list, list) { |
| 2163 | if (client->log_stop) { |
| 2164 | int r = client->log_stop(client, start_addr, size); |
| 2165 | if (r < 0) { |
| 2166 | return r; |
| 2167 | } |
| 2168 | } |
| 2169 | } |
| 2170 | return 0; |
| 2171 | } |
| 2172 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2173 | static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry) |
| 2174 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2175 | ram_addr_t ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2176 | void *p; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2177 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2178 | if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2179 | p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK) |
| 2180 | + tlb_entry->addend); |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 2181 | ram_addr = qemu_ram_addr_from_host_nofail(p); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2182 | if (!cpu_physical_memory_is_dirty(ram_addr)) { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2183 | tlb_entry->addr_write |= TLB_NOTDIRTY; |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2184 | } |
| 2185 | } |
| 2186 | } |
| 2187 | |
| 2188 | /* update the TLB according to the current state of the dirty bits */ |
| 2189 | void cpu_tlb_update_dirty(CPUState *env) |
| 2190 | { |
| 2191 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2192 | int mmu_idx; |
| 2193 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { |
| 2194 | for(i = 0; i < CPU_TLB_SIZE; i++) |
| 2195 | tlb_update_dirty(&env->tlb_table[mmu_idx][i]); |
| 2196 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 2197 | } |
| 2198 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2199 | static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2200 | { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2201 | if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) |
| 2202 | tlb_entry->addr_write = vaddr; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2203 | } |
| 2204 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2205 | /* update the TLB corresponding to virtual page vaddr |
| 2206 | so that it is no longer dirty */ |
| 2207 | static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2208 | { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2209 | int i; |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2210 | int mmu_idx; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2211 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2212 | vaddr &= TARGET_PAGE_MASK; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2213 | i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
Isaku Yamahata | cfde4bd | 2009-05-20 11:31:43 +0900 | [diff] [blame] | 2214 | for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) |
| 2215 | tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2216 | } |
| 2217 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2218 | /* Our TLB does not support large pages, so remember the area covered by |
| 2219 | large pages and trigger a full TLB flush if these are invalidated. */ |
| 2220 | static void tlb_add_large_page(CPUState *env, target_ulong vaddr, |
| 2221 | target_ulong size) |
| 2222 | { |
| 2223 | target_ulong mask = ~(size - 1); |
| 2224 | |
| 2225 | if (env->tlb_flush_addr == (target_ulong)-1) { |
| 2226 | env->tlb_flush_addr = vaddr & mask; |
| 2227 | env->tlb_flush_mask = mask; |
| 2228 | return; |
| 2229 | } |
| 2230 | /* Extend the existing region to include the new page. |
| 2231 | This is a compromise between unnecessary flushes and the cost |
| 2232 | of maintaining a full variable size TLB. */ |
| 2233 | mask &= env->tlb_flush_mask; |
| 2234 | while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { |
| 2235 | mask <<= 1; |
| 2236 | } |
| 2237 | env->tlb_flush_addr &= mask; |
| 2238 | env->tlb_flush_mask = mask; |
| 2239 | } |
| 2240 | |
| 2241 | /* Add a new TLB entry. At most one entry for a given virtual address |
| 2242 | is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the |
| 2243 | supplied size is only used by tlb_flush_page. */ |
| 2244 | void tlb_set_page(CPUState *env, target_ulong vaddr, |
| 2245 | target_phys_addr_t paddr, int prot, |
| 2246 | int mmu_idx, target_ulong size) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2247 | { |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2248 | PhysPageDesc *p; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2249 | unsigned long pd; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2250 | unsigned int index; |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 2251 | target_ulong address; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2252 | target_ulong code_address; |
Paul Brook | 355b194 | 2010-04-05 00:28:53 +0100 | [diff] [blame] | 2253 | unsigned long addend; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2254 | CPUTLBEntry *te; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2255 | CPUWatchpoint *wp; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2256 | target_phys_addr_t iotlb; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2257 | |
Paul Brook | d4c430a | 2010-03-17 02:14:28 +0000 | [diff] [blame] | 2258 | assert(size >= TARGET_PAGE_SIZE); |
| 2259 | if (size != TARGET_PAGE_SIZE) { |
| 2260 | tlb_add_large_page(env, vaddr, size); |
| 2261 | } |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2262 | p = phys_page_find(paddr >> TARGET_PAGE_BITS); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2263 | if (!p) { |
| 2264 | pd = IO_MEM_UNASSIGNED; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2265 | } else { |
| 2266 | pd = p->phys_offset; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2267 | } |
| 2268 | #if defined(DEBUG_TLB) |
Stefan Weil | 7fd3f49 | 2010-09-30 22:39:51 +0200 | [diff] [blame] | 2269 | printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx |
| 2270 | " prot=%x idx=%d pd=0x%08lx\n", |
| 2271 | vaddr, paddr, prot, mmu_idx, pd); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2272 | #endif |
| 2273 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2274 | address = vaddr; |
| 2275 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) { |
| 2276 | /* IO memory case (romd handled later) */ |
| 2277 | address |= TLB_MMIO; |
| 2278 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 2279 | addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2280 | if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) { |
| 2281 | /* Normal RAM. */ |
| 2282 | iotlb = pd & TARGET_PAGE_MASK; |
| 2283 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 2284 | iotlb |= IO_MEM_NOTDIRTY; |
| 2285 | else |
| 2286 | iotlb |= IO_MEM_ROM; |
| 2287 | } else { |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2288 | /* IO handlers are currently passed a physical address. |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2289 | It would be nice to pass an offset from the base address |
| 2290 | of that region. This would avoid having to special case RAM, |
| 2291 | and avoid full address decoding in every device. |
| 2292 | We can't use the high bits of pd for this because |
| 2293 | IO_MEM_ROMD uses these as a ram address. */ |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2294 | iotlb = (pd & ~TARGET_PAGE_MASK); |
| 2295 | if (p) { |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2296 | iotlb += p->region_offset; |
| 2297 | } else { |
| 2298 | iotlb += paddr; |
| 2299 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2300 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2301 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2302 | code_address = address; |
| 2303 | /* Make accesses to pages with watchpoints go via the |
| 2304 | watchpoint trap routines. */ |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 2305 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 2306 | if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { |
Jun Koi | bf298f8 | 2010-05-06 14:36:59 +0900 | [diff] [blame] | 2307 | /* Avoid trapping reads of pages with a write breakpoint. */ |
| 2308 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { |
| 2309 | iotlb = io_mem_watch + paddr; |
| 2310 | address |= TLB_MMIO; |
| 2311 | break; |
| 2312 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 2313 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2314 | } |
balrog | d79acba | 2007-06-26 20:01:13 +0000 | [diff] [blame] | 2315 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2316 | index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 2317 | env->iotlb[mmu_idx][index] = iotlb - vaddr; |
| 2318 | te = &env->tlb_table[mmu_idx][index]; |
| 2319 | te->addend = addend - vaddr; |
| 2320 | if (prot & PAGE_READ) { |
| 2321 | te->addr_read = address; |
| 2322 | } else { |
| 2323 | te->addr_read = -1; |
| 2324 | } |
edgar_igl | 5c751e9 | 2008-05-06 08:44:21 +0000 | [diff] [blame] | 2325 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2326 | if (prot & PAGE_EXEC) { |
| 2327 | te->addr_code = code_address; |
| 2328 | } else { |
| 2329 | te->addr_code = -1; |
| 2330 | } |
| 2331 | if (prot & PAGE_WRITE) { |
| 2332 | if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM || |
| 2333 | (pd & IO_MEM_ROMD)) { |
| 2334 | /* Write access calls the I/O callback. */ |
| 2335 | te->addr_write = address | TLB_MMIO; |
| 2336 | } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM && |
| 2337 | !cpu_physical_memory_is_dirty(pd)) { |
| 2338 | te->addr_write = address | TLB_NOTDIRTY; |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 2339 | } else { |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2340 | te->addr_write = address; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2341 | } |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 2342 | } else { |
| 2343 | te->addr_write = -1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2344 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2345 | } |
| 2346 | |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2347 | #else |
| 2348 | |
bellard | ee8b702 | 2004-02-03 23:35:10 +0000 | [diff] [blame] | 2349 | void tlb_flush(CPUState *env, int flush_global) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2350 | { |
| 2351 | } |
| 2352 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 2353 | void tlb_flush_page(CPUState *env, target_ulong addr) |
bellard | 0124311 | 2004-01-04 15:48:17 +0000 | [diff] [blame] | 2354 | { |
| 2355 | } |
| 2356 | |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2357 | /* |
| 2358 | * Walks guest process memory "regions" one by one |
| 2359 | * and calls callback function 'fn' for each region. |
| 2360 | */ |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2361 | |
| 2362 | struct walk_memory_regions_data |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2363 | { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2364 | walk_memory_regions_fn fn; |
| 2365 | void *priv; |
| 2366 | unsigned long start; |
| 2367 | int prot; |
| 2368 | }; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2369 | |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2370 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2371 | abi_ulong end, int new_prot) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2372 | { |
| 2373 | if (data->start != -1ul) { |
| 2374 | int rc = data->fn(data->priv, data->start, end, data->prot); |
| 2375 | if (rc != 0) { |
| 2376 | return rc; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2377 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2378 | } |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2379 | |
| 2380 | data->start = (new_prot ? end : -1ul); |
| 2381 | data->prot = new_prot; |
| 2382 | |
| 2383 | return 0; |
| 2384 | } |
| 2385 | |
| 2386 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2387 | abi_ulong base, int level, void **lp) |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2388 | { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2389 | abi_ulong pa; |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2390 | int i, rc; |
| 2391 | |
| 2392 | if (*lp == NULL) { |
| 2393 | return walk_memory_regions_end(data, base, 0); |
| 2394 | } |
| 2395 | |
| 2396 | if (level == 0) { |
| 2397 | PageDesc *pd = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2398 | for (i = 0; i < L2_SIZE; ++i) { |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2399 | int prot = pd[i].flags; |
| 2400 | |
| 2401 | pa = base | (i << TARGET_PAGE_BITS); |
| 2402 | if (prot != data->prot) { |
| 2403 | rc = walk_memory_regions_end(data, pa, prot); |
| 2404 | if (rc != 0) { |
| 2405 | return rc; |
| 2406 | } |
| 2407 | } |
| 2408 | } |
| 2409 | } else { |
| 2410 | void **pp = *lp; |
Paul Brook | 7296aba | 2010-03-14 14:58:46 +0000 | [diff] [blame] | 2411 | for (i = 0; i < L2_SIZE; ++i) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2412 | pa = base | ((abi_ulong)i << |
| 2413 | (TARGET_PAGE_BITS + L2_BITS * level)); |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2414 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
| 2415 | if (rc != 0) { |
| 2416 | return rc; |
| 2417 | } |
| 2418 | } |
| 2419 | } |
| 2420 | |
| 2421 | return 0; |
| 2422 | } |
| 2423 | |
| 2424 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) |
| 2425 | { |
| 2426 | struct walk_memory_regions_data data; |
| 2427 | unsigned long i; |
| 2428 | |
| 2429 | data.fn = fn; |
| 2430 | data.priv = priv; |
| 2431 | data.start = -1ul; |
| 2432 | data.prot = 0; |
| 2433 | |
| 2434 | for (i = 0; i < V_L1_SIZE; i++) { |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2435 | int rc = walk_memory_regions_1(&data, (abi_ulong)i << V_L1_SHIFT, |
Richard Henderson | 5cd2c5b | 2010-03-10 15:53:37 -0800 | [diff] [blame] | 2436 | V_L1_SHIFT / L2_BITS - 1, l1_map + i); |
| 2437 | if (rc != 0) { |
| 2438 | return rc; |
| 2439 | } |
| 2440 | } |
| 2441 | |
| 2442 | return walk_memory_regions_end(&data, 0, 0); |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2443 | } |
| 2444 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2445 | static int dump_region(void *priv, abi_ulong start, |
| 2446 | abi_ulong end, unsigned long prot) |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2447 | { |
| 2448 | FILE *f = (FILE *)priv; |
| 2449 | |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2450 | (void) fprintf(f, TARGET_ABI_FMT_lx"-"TARGET_ABI_FMT_lx |
| 2451 | " "TARGET_ABI_FMT_lx" %c%c%c\n", |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 2452 | start, end, end - start, |
| 2453 | ((prot & PAGE_READ) ? 'r' : '-'), |
| 2454 | ((prot & PAGE_WRITE) ? 'w' : '-'), |
| 2455 | ((prot & PAGE_EXEC) ? 'x' : '-')); |
| 2456 | |
| 2457 | return (0); |
| 2458 | } |
| 2459 | |
| 2460 | /* dump memory mappings */ |
| 2461 | void page_dump(FILE *f) |
| 2462 | { |
| 2463 | (void) fprintf(f, "%-8s %-8s %-8s %s\n", |
| 2464 | "start", "end", "size", "prot"); |
| 2465 | walk_memory_regions(f, dump_region); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2466 | } |
| 2467 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2468 | int page_get_flags(target_ulong address) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2469 | { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2470 | PageDesc *p; |
| 2471 | |
| 2472 | p = page_find(address >> TARGET_PAGE_BITS); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2473 | if (!p) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2474 | return 0; |
| 2475 | return p->flags; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2476 | } |
| 2477 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2478 | /* Modify the flags of a page and invalidate the code if necessary. |
| 2479 | The flag PAGE_WRITE_ORG is positioned automatically depending |
| 2480 | on PAGE_WRITE. The mmap_lock should already be held. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2481 | void page_set_flags(target_ulong start, target_ulong end, int flags) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2482 | { |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2483 | target_ulong addr, len; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2484 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2485 | /* This function should never be called with addresses outside the |
| 2486 | guest address space. If this assert fires, it probably indicates |
| 2487 | a missing call to h2g_valid. */ |
Paul Brook | b480d9b | 2010-03-12 23:23:29 +0000 | [diff] [blame] | 2488 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2489 | assert(end < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2490 | #endif |
| 2491 | assert(start < end); |
| 2492 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2493 | start = start & TARGET_PAGE_MASK; |
| 2494 | end = TARGET_PAGE_ALIGN(end); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2495 | |
| 2496 | if (flags & PAGE_WRITE) { |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2497 | flags |= PAGE_WRITE_ORG; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | for (addr = start, len = end - start; |
| 2501 | len != 0; |
| 2502 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
| 2503 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2504 | |
| 2505 | /* If the write protection bit is set, then we invalidate |
| 2506 | the code inside. */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2507 | if (!(p->flags & PAGE_WRITE) && |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2508 | (flags & PAGE_WRITE) && |
| 2509 | p->first_tb) { |
bellard | d720b93 | 2004-04-25 17:57:43 +0000 | [diff] [blame] | 2510 | tb_invalidate_phys_page(addr, 0, NULL); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2511 | } |
| 2512 | p->flags = flags; |
| 2513 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2514 | } |
| 2515 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2516 | int page_check_range(target_ulong start, target_ulong len, int flags) |
| 2517 | { |
| 2518 | PageDesc *p; |
| 2519 | target_ulong end; |
| 2520 | target_ulong addr; |
| 2521 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2522 | /* This function should never be called with addresses outside the |
| 2523 | guest address space. If this assert fires, it probably indicates |
| 2524 | a missing call to h2g_valid. */ |
Blue Swirl | 338e9e6 | 2010-03-13 09:48:08 +0000 | [diff] [blame] | 2525 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS |
| 2526 | assert(start < ((abi_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2527 | #endif |
| 2528 | |
Richard Henderson | 3e0650a | 2010-03-29 10:54:42 -0700 | [diff] [blame] | 2529 | if (len == 0) { |
| 2530 | return 0; |
| 2531 | } |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2532 | if (start + len - 1 < start) { |
| 2533 | /* We've wrapped around. */ |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2534 | return -1; |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2535 | } |
balrog | 55f280c | 2008-10-28 10:24:11 +0000 | [diff] [blame] | 2536 | |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2537 | end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */ |
| 2538 | start = start & TARGET_PAGE_MASK; |
| 2539 | |
Richard Henderson | 376a790 | 2010-03-10 15:57:04 -0800 | [diff] [blame] | 2540 | for (addr = start, len = end - start; |
| 2541 | len != 0; |
| 2542 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2543 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2544 | if( !p ) |
| 2545 | return -1; |
| 2546 | if( !(p->flags & PAGE_VALID) ) |
| 2547 | return -1; |
| 2548 | |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2549 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2550 | return -1; |
bellard | dae3270 | 2007-11-14 10:51:00 +0000 | [diff] [blame] | 2551 | if (flags & PAGE_WRITE) { |
| 2552 | if (!(p->flags & PAGE_WRITE_ORG)) |
| 2553 | return -1; |
| 2554 | /* unprotect the page if it was put read-only because it |
| 2555 | contains translated code */ |
| 2556 | if (!(p->flags & PAGE_WRITE)) { |
| 2557 | if (!page_unprotect(addr, 0, NULL)) |
| 2558 | return -1; |
| 2559 | } |
| 2560 | return 0; |
| 2561 | } |
ths | 3d97b40 | 2007-11-02 19:02:07 +0000 | [diff] [blame] | 2562 | } |
| 2563 | return 0; |
| 2564 | } |
| 2565 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2566 | /* called from signal handler: invalidate the code and unprotect the |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2567 | page. Return TRUE if the fault was successfully handled. */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2568 | int page_unprotect(target_ulong address, unsigned long pc, void *puc) |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2569 | { |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2570 | unsigned int prot; |
| 2571 | PageDesc *p; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 2572 | target_ulong host_start, host_end, addr; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2573 | |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2574 | /* Technically this isn't safe inside a signal handler. However we |
| 2575 | know this only ever happens in a synchronous SEGV handler, so in |
| 2576 | practice it seems to be ok. */ |
| 2577 | mmap_lock(); |
| 2578 | |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2579 | p = page_find(address >> TARGET_PAGE_BITS); |
| 2580 | if (!p) { |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2581 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2582 | return 0; |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2583 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2584 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2585 | /* if the page was really writable, then we change its |
| 2586 | protection back to writable */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2587 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { |
| 2588 | host_start = address & qemu_host_page_mask; |
| 2589 | host_end = host_start + qemu_host_page_size; |
| 2590 | |
| 2591 | prot = 0; |
| 2592 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { |
| 2593 | p = page_find(addr >> TARGET_PAGE_BITS); |
| 2594 | p->flags |= PAGE_WRITE; |
| 2595 | prot |= p->flags; |
| 2596 | |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2597 | /* and since the content will be modified, we must invalidate |
| 2598 | the corresponding translated code. */ |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2599 | tb_invalidate_phys_page(addr, pc, puc); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2600 | #ifdef DEBUG_TB_CHECK |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2601 | tb_invalidate_check(addr); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2602 | #endif |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2603 | } |
Aurelien Jarno | 45d679d | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 2604 | mprotect((void *)g2h(host_start), qemu_host_page_size, |
| 2605 | prot & PAGE_BITS); |
| 2606 | |
| 2607 | mmap_unlock(); |
| 2608 | return 1; |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2609 | } |
pbrook | c8a706f | 2008-06-02 16:16:42 +0000 | [diff] [blame] | 2610 | mmap_unlock(); |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2611 | return 0; |
| 2612 | } |
| 2613 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 2614 | static inline void tlb_set_dirty(CPUState *env, |
| 2615 | unsigned long addr, target_ulong vaddr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 2616 | { |
| 2617 | } |
bellard | 9fa3e85 | 2004-01-04 18:06:42 +0000 | [diff] [blame] | 2618 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 2619 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 2620 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2621 | |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2622 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) |
| 2623 | typedef struct subpage_t { |
| 2624 | target_phys_addr_t base; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2625 | ram_addr_t sub_io_index[TARGET_PAGE_SIZE]; |
| 2626 | ram_addr_t region_offset[TARGET_PAGE_SIZE]; |
Paul Brook | c04b2b7 | 2010-03-01 03:31:14 +0000 | [diff] [blame] | 2627 | } subpage_t; |
| 2628 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2629 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 2630 | ram_addr_t memory, ram_addr_t region_offset); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2631 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 2632 | ram_addr_t orig_memory, |
| 2633 | ram_addr_t region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2634 | #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \ |
| 2635 | need_subpage) \ |
| 2636 | do { \ |
| 2637 | if (addr > start_addr) \ |
| 2638 | start_addr2 = 0; \ |
| 2639 | else { \ |
| 2640 | start_addr2 = start_addr & ~TARGET_PAGE_MASK; \ |
| 2641 | if (start_addr2 > 0) \ |
| 2642 | need_subpage = 1; \ |
| 2643 | } \ |
| 2644 | \ |
blueswir1 | 49e9fba | 2007-05-30 17:25:06 +0000 | [diff] [blame] | 2645 | if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \ |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2646 | end_addr2 = TARGET_PAGE_SIZE - 1; \ |
| 2647 | else { \ |
| 2648 | end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \ |
| 2649 | if (end_addr2 < TARGET_PAGE_SIZE - 1) \ |
| 2650 | need_subpage = 1; \ |
| 2651 | } \ |
| 2652 | } while (0) |
| 2653 | |
Michael S. Tsirkin | 8f2498f | 2009-09-29 18:53:16 +0200 | [diff] [blame] | 2654 | /* register physical memory. |
| 2655 | For RAM, 'size' must be a multiple of the target page size. |
| 2656 | If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2657 | io memory page. The address used when calling the IO function is |
| 2658 | the offset from the start of the region, plus region_offset. Both |
Stuart Brady | ccbb4d4 | 2009-05-03 12:15:06 +0100 | [diff] [blame] | 2659 | start_addr and region_offset are rounded down to a page boundary |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2660 | before calculating this offset. This should not be a problem unless |
| 2661 | the low bits of start_addr and region_offset differ. */ |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2662 | void cpu_register_physical_memory_log(target_phys_addr_t start_addr, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2663 | ram_addr_t size, |
| 2664 | ram_addr_t phys_offset, |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2665 | ram_addr_t region_offset, |
| 2666 | bool log_dirty) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2667 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2668 | target_phys_addr_t addr, end_addr; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 2669 | PhysPageDesc *p; |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2670 | CPUState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2671 | ram_addr_t orig_size = size; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2672 | subpage_t *subpage; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2673 | |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2674 | assert(size); |
Michael S. Tsirkin | 0fd542f | 2011-04-06 22:25:38 +0300 | [diff] [blame] | 2675 | cpu_notify_set_memory(start_addr, size, phys_offset, log_dirty); |
Michael S. Tsirkin | f6f3fbc | 2010-01-27 22:06:57 +0200 | [diff] [blame] | 2676 | |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2677 | if (phys_offset == IO_MEM_UNASSIGNED) { |
| 2678 | region_offset = start_addr; |
| 2679 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2680 | region_offset &= TARGET_PAGE_MASK; |
bellard | 5fd386f | 2004-05-23 21:11:22 +0000 | [diff] [blame] | 2681 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2682 | end_addr = start_addr + (target_phys_addr_t)size; |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2683 | |
| 2684 | addr = start_addr; |
| 2685 | do { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2686 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2687 | if (p && p->phys_offset != IO_MEM_UNASSIGNED) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2688 | ram_addr_t orig_memory = p->phys_offset; |
| 2689 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2690 | int need_subpage = 0; |
| 2691 | |
| 2692 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, |
| 2693 | need_subpage); |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2694 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2695 | if (!(orig_memory & IO_MEM_SUBPAGE)) { |
| 2696 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2697 | &p->phys_offset, orig_memory, |
| 2698 | p->region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2699 | } else { |
| 2700 | subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK) |
| 2701 | >> IO_MEM_SHIFT]; |
| 2702 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2703 | subpage_register(subpage, start_addr2, end_addr2, phys_offset, |
| 2704 | region_offset); |
| 2705 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2706 | } else { |
| 2707 | p->phys_offset = phys_offset; |
| 2708 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
| 2709 | (phys_offset & IO_MEM_ROMD)) |
| 2710 | phys_offset += TARGET_PAGE_SIZE; |
| 2711 | } |
| 2712 | } else { |
| 2713 | p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1); |
| 2714 | p->phys_offset = phys_offset; |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2715 | p->region_offset = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2716 | if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM || |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2717 | (phys_offset & IO_MEM_ROMD)) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2718 | phys_offset += TARGET_PAGE_SIZE; |
pbrook | 0e8f096 | 2008-12-02 09:02:15 +0000 | [diff] [blame] | 2719 | } else { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2720 | target_phys_addr_t start_addr2, end_addr2; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2721 | int need_subpage = 0; |
| 2722 | |
| 2723 | CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, |
| 2724 | end_addr2, need_subpage); |
| 2725 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 2726 | if (need_subpage) { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2727 | subpage = subpage_init((addr & TARGET_PAGE_MASK), |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2728 | &p->phys_offset, IO_MEM_UNASSIGNED, |
pbrook | 67c4d23 | 2009-02-23 13:16:07 +0000 | [diff] [blame] | 2729 | addr & TARGET_PAGE_MASK); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2730 | subpage_register(subpage, start_addr2, end_addr2, |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2731 | phys_offset, region_offset); |
| 2732 | p->region_offset = 0; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 2733 | } |
| 2734 | } |
| 2735 | } |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 2736 | region_offset += TARGET_PAGE_SIZE; |
Edgar E. Iglesias | 3b8e6a2 | 2011-04-05 13:00:36 +0200 | [diff] [blame] | 2737 | addr += TARGET_PAGE_SIZE; |
| 2738 | } while (addr != end_addr); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2739 | |
bellard | 9d42037 | 2006-06-25 22:25:22 +0000 | [diff] [blame] | 2740 | /* since each CPU stores ram addresses in its TLB cache, we must |
| 2741 | reset the modified entries */ |
| 2742 | /* XXX: slow ! */ |
| 2743 | for(env = first_cpu; env != NULL; env = env->next_cpu) { |
| 2744 | tlb_flush(env, 1); |
| 2745 | } |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 2746 | } |
| 2747 | |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2748 | /* XXX: temporary until new memory mapping API */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2749 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr) |
bellard | ba86345 | 2006-09-24 18:41:10 +0000 | [diff] [blame] | 2750 | { |
| 2751 | PhysPageDesc *p; |
| 2752 | |
| 2753 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 2754 | if (!p) |
| 2755 | return IO_MEM_UNASSIGNED; |
| 2756 | return p->phys_offset; |
| 2757 | } |
| 2758 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2759 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2760 | { |
| 2761 | if (kvm_enabled()) |
| 2762 | kvm_coalesce_mmio_region(addr, size); |
| 2763 | } |
| 2764 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2765 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size) |
aliguori | f65ed4c | 2008-12-09 20:09:57 +0000 | [diff] [blame] | 2766 | { |
| 2767 | if (kvm_enabled()) |
| 2768 | kvm_uncoalesce_mmio_region(addr, size); |
| 2769 | } |
| 2770 | |
Sheng Yang | 62a2744 | 2010-01-26 19:21:16 +0800 | [diff] [blame] | 2771 | void qemu_flush_coalesced_mmio_buffer(void) |
| 2772 | { |
| 2773 | if (kvm_enabled()) |
| 2774 | kvm_flush_coalesced_mmio_buffer(); |
| 2775 | } |
| 2776 | |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2777 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 2778 | |
| 2779 | #include <sys/vfs.h> |
| 2780 | |
| 2781 | #define HUGETLBFS_MAGIC 0x958458f6 |
| 2782 | |
| 2783 | static long gethugepagesize(const char *path) |
| 2784 | { |
| 2785 | struct statfs fs; |
| 2786 | int ret; |
| 2787 | |
| 2788 | do { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2789 | ret = statfs(path, &fs); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2790 | } while (ret != 0 && errno == EINTR); |
| 2791 | |
| 2792 | if (ret != 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2793 | perror(path); |
| 2794 | return 0; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2795 | } |
| 2796 | |
| 2797 | if (fs.f_type != HUGETLBFS_MAGIC) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2798 | fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2799 | |
| 2800 | return fs.f_bsize; |
| 2801 | } |
| 2802 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2803 | static void *file_ram_alloc(RAMBlock *block, |
| 2804 | ram_addr_t memory, |
| 2805 | const char *path) |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2806 | { |
| 2807 | char *filename; |
| 2808 | void *area; |
| 2809 | int fd; |
| 2810 | #ifdef MAP_POPULATE |
| 2811 | int flags; |
| 2812 | #endif |
| 2813 | unsigned long hpagesize; |
| 2814 | |
| 2815 | hpagesize = gethugepagesize(path); |
| 2816 | if (!hpagesize) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2817 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2818 | } |
| 2819 | |
| 2820 | if (memory < hpagesize) { |
| 2821 | return NULL; |
| 2822 | } |
| 2823 | |
| 2824 | if (kvm_enabled() && !kvm_has_sync_mmu()) { |
| 2825 | fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n"); |
| 2826 | return NULL; |
| 2827 | } |
| 2828 | |
| 2829 | if (asprintf(&filename, "%s/qemu_back_mem.XXXXXX", path) == -1) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2830 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2831 | } |
| 2832 | |
| 2833 | fd = mkstemp(filename); |
| 2834 | if (fd < 0) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2835 | perror("unable to create backing store for hugepages"); |
| 2836 | free(filename); |
| 2837 | return NULL; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2838 | } |
| 2839 | unlink(filename); |
| 2840 | free(filename); |
| 2841 | |
| 2842 | memory = (memory+hpagesize-1) & ~(hpagesize-1); |
| 2843 | |
| 2844 | /* |
| 2845 | * ftruncate is not supported by hugetlbfs in older |
| 2846 | * hosts, so don't bother bailing out on errors. |
| 2847 | * If anything goes wrong with it under other filesystems, |
| 2848 | * mmap will fail. |
| 2849 | */ |
| 2850 | if (ftruncate(fd, memory)) |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2851 | perror("ftruncate"); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2852 | |
| 2853 | #ifdef MAP_POPULATE |
| 2854 | /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case |
| 2855 | * MAP_PRIVATE is requested. For mem_prealloc we mmap as MAP_SHARED |
| 2856 | * to sidestep this quirk. |
| 2857 | */ |
| 2858 | flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE; |
| 2859 | area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0); |
| 2860 | #else |
| 2861 | area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); |
| 2862 | #endif |
| 2863 | if (area == MAP_FAILED) { |
Yoshiaki Tamura | 9742bf2 | 2010-08-18 13:30:13 +0900 | [diff] [blame] | 2864 | perror("file_ram_alloc: can't mmap RAM pages"); |
| 2865 | close(fd); |
| 2866 | return (NULL); |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2867 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2868 | block->fd = fd; |
Marcelo Tosatti | c902760 | 2010-03-01 20:25:08 -0300 | [diff] [blame] | 2869 | return area; |
| 2870 | } |
| 2871 | #endif |
| 2872 | |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2873 | static ram_addr_t find_ram_offset(ram_addr_t size) |
| 2874 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2875 | RAMBlock *block, *next_block; |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2876 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2877 | |
| 2878 | if (QLIST_EMPTY(&ram_list.blocks)) |
| 2879 | return 0; |
| 2880 | |
| 2881 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 2882 | ram_addr_t end, next = RAM_ADDR_MAX; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2883 | |
| 2884 | end = block->offset + block->length; |
| 2885 | |
| 2886 | QLIST_FOREACH(next_block, &ram_list.blocks, next) { |
| 2887 | if (next_block->offset >= end) { |
| 2888 | next = MIN(next, next_block->offset); |
| 2889 | } |
| 2890 | } |
| 2891 | if (next - end >= size && next - end < mingap) { |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2892 | offset = end; |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2893 | mingap = next - end; |
| 2894 | } |
| 2895 | } |
Alex Williamson | 3e837b2 | 2011-10-31 08:54:09 -0600 | [diff] [blame] | 2896 | |
| 2897 | if (offset == RAM_ADDR_MAX) { |
| 2898 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", |
| 2899 | (uint64_t)size); |
| 2900 | abort(); |
| 2901 | } |
| 2902 | |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 2903 | return offset; |
| 2904 | } |
| 2905 | |
| 2906 | static ram_addr_t last_ram_offset(void) |
| 2907 | { |
Alex Williamson | d17b528 | 2010-06-25 11:08:38 -0600 | [diff] [blame] | 2908 | RAMBlock *block; |
| 2909 | ram_addr_t last = 0; |
| 2910 | |
| 2911 | QLIST_FOREACH(block, &ram_list.blocks, next) |
| 2912 | last = MAX(last, block->offset + block->length); |
| 2913 | |
| 2914 | return last; |
| 2915 | } |
| 2916 | |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2917 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2918 | ram_addr_t size, void *host) |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2919 | { |
| 2920 | RAMBlock *new_block, *block; |
| 2921 | |
| 2922 | size = TARGET_PAGE_ALIGN(size); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2923 | new_block = g_malloc0(sizeof(*new_block)); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2924 | |
| 2925 | if (dev && dev->parent_bus && dev->parent_bus->info->get_dev_path) { |
| 2926 | char *id = dev->parent_bus->info->get_dev_path(dev); |
| 2927 | if (id) { |
| 2928 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2929 | g_free(id); |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2930 | } |
| 2931 | } |
| 2932 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); |
| 2933 | |
| 2934 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 2935 | if (!strcmp(block->idstr, new_block->idstr)) { |
| 2936 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", |
| 2937 | new_block->idstr); |
| 2938 | abort(); |
| 2939 | } |
| 2940 | } |
| 2941 | |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 2942 | new_block->offset = find_ram_offset(size); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2943 | if (host) { |
| 2944 | new_block->host = host; |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 2945 | new_block->flags |= RAM_PREALLOC_MASK; |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2946 | } else { |
| 2947 | if (mem_path) { |
| 2948 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 2949 | new_block->host = file_ram_alloc(new_block, size, mem_path); |
| 2950 | if (!new_block->host) { |
| 2951 | new_block->host = qemu_vmalloc(size); |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2952 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2953 | } |
| 2954 | #else |
| 2955 | fprintf(stderr, "-mem-path option unsupported\n"); |
| 2956 | exit(1); |
| 2957 | #endif |
| 2958 | } else { |
| 2959 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
Christian Borntraeger | ff83678 | 2011-05-10 14:49:10 +0200 | [diff] [blame] | 2960 | /* S390 KVM requires the topmost vma of the RAM to be smaller than |
| 2961 | an system defined value, which is at least 256GB. Larger systems |
| 2962 | have larger values. We put the guest between the end of data |
| 2963 | segment (system break) and this value. We use 32GB as a base to |
| 2964 | have enough room for the system break to grow. */ |
| 2965 | new_block->host = mmap((void*)0x800000000, size, |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2966 | PROT_EXEC|PROT_READ|PROT_WRITE, |
Christian Borntraeger | ff83678 | 2011-05-10 14:49:10 +0200 | [diff] [blame] | 2967 | MAP_SHARED | MAP_ANONYMOUS | MAP_FIXED, -1, 0); |
Alexander Graf | fb8b273 | 2011-05-20 17:33:28 +0200 | [diff] [blame] | 2968 | if (new_block->host == MAP_FAILED) { |
| 2969 | fprintf(stderr, "Allocating RAM failed\n"); |
| 2970 | abort(); |
| 2971 | } |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2972 | #else |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 2973 | if (xen_enabled()) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 2974 | xen_ram_alloc(new_block->offset, size); |
| 2975 | } else { |
| 2976 | new_block->host = qemu_vmalloc(size); |
| 2977 | } |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2978 | #endif |
Andreas Färber | e78815a | 2010-09-25 11:26:05 +0000 | [diff] [blame] | 2979 | qemu_madvise(new_block->host, size, QEMU_MADV_MERGEABLE); |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2980 | } |
| 2981 | } |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2982 | new_block->length = size; |
| 2983 | |
| 2984 | QLIST_INSERT_HEAD(&ram_list.blocks, new_block, next); |
| 2985 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 2986 | ram_list.phys_dirty = g_realloc(ram_list.phys_dirty, |
Cam Macdonell | 84b89d7 | 2010-07-26 18:10:57 -0600 | [diff] [blame] | 2987 | last_ram_offset() >> TARGET_PAGE_BITS); |
| 2988 | memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS), |
| 2989 | 0xff, size >> TARGET_PAGE_BITS); |
| 2990 | |
| 2991 | if (kvm_enabled()) |
| 2992 | kvm_setup_guest_memory(new_block->host, size); |
| 2993 | |
| 2994 | return new_block->offset; |
| 2995 | } |
| 2996 | |
Alex Williamson | 1724f04 | 2010-06-25 11:09:35 -0600 | [diff] [blame] | 2997 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size) |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 2998 | { |
Yoshiaki Tamura | 6977dfe | 2010-08-18 15:41:49 +0900 | [diff] [blame] | 2999 | return qemu_ram_alloc_from_ptr(dev, name, size, NULL); |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3000 | } |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 3001 | |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 3002 | void qemu_ram_free_from_ptr(ram_addr_t addr) |
| 3003 | { |
| 3004 | RAMBlock *block; |
| 3005 | |
| 3006 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3007 | if (addr == block->offset) { |
| 3008 | QLIST_REMOVE(block, next); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3009 | g_free(block); |
Alex Williamson | 1f2e98b | 2011-05-03 12:48:09 -0600 | [diff] [blame] | 3010 | return; |
| 3011 | } |
| 3012 | } |
| 3013 | } |
| 3014 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3015 | void qemu_ram_free(ram_addr_t addr) |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 3016 | { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 3017 | RAMBlock *block; |
| 3018 | |
| 3019 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3020 | if (addr == block->offset) { |
| 3021 | QLIST_REMOVE(block, next); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3022 | if (block->flags & RAM_PREALLOC_MASK) { |
| 3023 | ; |
| 3024 | } else if (mem_path) { |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 3025 | #if defined (__linux__) && !defined(TARGET_S390X) |
| 3026 | if (block->fd) { |
| 3027 | munmap(block->host, block->length); |
| 3028 | close(block->fd); |
| 3029 | } else { |
| 3030 | qemu_vfree(block->host); |
| 3031 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 3032 | #else |
| 3033 | abort(); |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 3034 | #endif |
| 3035 | } else { |
| 3036 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 3037 | munmap(block->host, block->length); |
| 3038 | #else |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3039 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3040 | xen_invalidate_map_cache_entry(block->host); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3041 | } else { |
| 3042 | qemu_vfree(block->host); |
| 3043 | } |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 3044 | #endif |
| 3045 | } |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3046 | g_free(block); |
Alex Williamson | 04b1665 | 2010-07-02 11:13:17 -0600 | [diff] [blame] | 3047 | return; |
| 3048 | } |
| 3049 | } |
| 3050 | |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 3051 | } |
| 3052 | |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3053 | #ifndef _WIN32 |
| 3054 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) |
| 3055 | { |
| 3056 | RAMBlock *block; |
| 3057 | ram_addr_t offset; |
| 3058 | int flags; |
| 3059 | void *area, *vaddr; |
| 3060 | |
| 3061 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3062 | offset = addr - block->offset; |
| 3063 | if (offset < block->length) { |
| 3064 | vaddr = block->host + offset; |
| 3065 | if (block->flags & RAM_PREALLOC_MASK) { |
| 3066 | ; |
| 3067 | } else { |
| 3068 | flags = MAP_FIXED; |
| 3069 | munmap(vaddr, length); |
| 3070 | if (mem_path) { |
| 3071 | #if defined(__linux__) && !defined(TARGET_S390X) |
| 3072 | if (block->fd) { |
| 3073 | #ifdef MAP_POPULATE |
| 3074 | flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED : |
| 3075 | MAP_PRIVATE; |
| 3076 | #else |
| 3077 | flags |= MAP_PRIVATE; |
| 3078 | #endif |
| 3079 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3080 | flags, block->fd, offset); |
| 3081 | } else { |
| 3082 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3083 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3084 | flags, -1, 0); |
| 3085 | } |
Jan Kiszka | fd28aa1 | 2011-03-15 12:26:14 +0100 | [diff] [blame] | 3086 | #else |
| 3087 | abort(); |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3088 | #endif |
| 3089 | } else { |
| 3090 | #if defined(TARGET_S390X) && defined(CONFIG_KVM) |
| 3091 | flags |= MAP_SHARED | MAP_ANONYMOUS; |
| 3092 | area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE, |
| 3093 | flags, -1, 0); |
| 3094 | #else |
| 3095 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; |
| 3096 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, |
| 3097 | flags, -1, 0); |
| 3098 | #endif |
| 3099 | } |
| 3100 | if (area != vaddr) { |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 3101 | fprintf(stderr, "Could not remap addr: " |
| 3102 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", |
Huang Ying | cd19cfa | 2011-03-02 08:56:19 +0100 | [diff] [blame] | 3103 | length, addr); |
| 3104 | exit(1); |
| 3105 | } |
| 3106 | qemu_madvise(vaddr, length, QEMU_MADV_MERGEABLE); |
| 3107 | } |
| 3108 | return; |
| 3109 | } |
| 3110 | } |
| 3111 | } |
| 3112 | #endif /* !_WIN32 */ |
| 3113 | |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3114 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3115 | With the exception of the softmmu code in this file, this should |
| 3116 | only be used for local memory (e.g. video ram) that the device owns, |
| 3117 | and knows it isn't going to access beyond the end of the block. |
| 3118 | |
| 3119 | It should not be used for general purpose DMA. |
| 3120 | Use cpu_physical_memory_map/cpu_physical_memory_rw instead. |
| 3121 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3122 | void *qemu_get_ram_ptr(ram_addr_t addr) |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3123 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3124 | RAMBlock *block; |
| 3125 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3126 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3127 | if (addr - block->offset < block->length) { |
Vincent Palatin | 7d82af3 | 2011-03-10 15:47:46 -0500 | [diff] [blame] | 3128 | /* Move this entry to to start of the list. */ |
| 3129 | if (block != QLIST_FIRST(&ram_list.blocks)) { |
| 3130 | QLIST_REMOVE(block, next); |
| 3131 | QLIST_INSERT_HEAD(&ram_list.blocks, block, next); |
| 3132 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3133 | if (xen_enabled()) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3134 | /* We need to check if the requested address is in the RAM |
| 3135 | * because we don't want to map the entire memory in QEMU. |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3136 | * In that case just map until the end of the page. |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3137 | */ |
| 3138 | if (block->offset == 0) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3139 | return xen_map_cache(addr, 0, 0); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3140 | } else if (block->host == NULL) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3141 | block->host = |
| 3142 | xen_map_cache(block->offset, block->length, 1); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3143 | } |
| 3144 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3145 | return block->host + (addr - block->offset); |
| 3146 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3147 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3148 | |
| 3149 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3150 | abort(); |
| 3151 | |
| 3152 | return NULL; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 3153 | } |
| 3154 | |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3155 | /* Return a host pointer to ram allocated with qemu_ram_alloc. |
| 3156 | * Same as qemu_get_ram_ptr but avoid reordering ramblocks. |
| 3157 | */ |
| 3158 | void *qemu_safe_ram_ptr(ram_addr_t addr) |
| 3159 | { |
| 3160 | RAMBlock *block; |
| 3161 | |
| 3162 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3163 | if (addr - block->offset < block->length) { |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3164 | if (xen_enabled()) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3165 | /* We need to check if the requested address is in the RAM |
| 3166 | * because we don't want to map the entire memory in QEMU. |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3167 | * In that case just map until the end of the page. |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3168 | */ |
| 3169 | if (block->offset == 0) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3170 | return xen_map_cache(addr, 0, 0); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3171 | } else if (block->host == NULL) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3172 | block->host = |
| 3173 | xen_map_cache(block->offset, block->length, 1); |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3174 | } |
| 3175 | } |
Michael S. Tsirkin | b2e0a13 | 2010-11-22 19:52:34 +0200 | [diff] [blame] | 3176 | return block->host + (addr - block->offset); |
| 3177 | } |
| 3178 | } |
| 3179 | |
| 3180 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3181 | abort(); |
| 3182 | |
| 3183 | return NULL; |
| 3184 | } |
| 3185 | |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3186 | /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr |
| 3187 | * but takes a size argument */ |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 3188 | void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3189 | { |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 3190 | if (*size == 0) { |
| 3191 | return NULL; |
| 3192 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3193 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3194 | return xen_map_cache(addr, *size, 1); |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3195 | } else { |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3196 | RAMBlock *block; |
| 3197 | |
| 3198 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
| 3199 | if (addr - block->offset < block->length) { |
| 3200 | if (addr - block->offset + *size > block->length) |
| 3201 | *size = block->length - addr + block->offset; |
| 3202 | return block->host + (addr - block->offset); |
| 3203 | } |
| 3204 | } |
| 3205 | |
| 3206 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); |
| 3207 | abort(); |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 3208 | } |
| 3209 | } |
| 3210 | |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3211 | void qemu_put_ram_ptr(void *addr) |
| 3212 | { |
| 3213 | trace_qemu_put_ram_ptr(addr); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3214 | } |
| 3215 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3216 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr) |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3217 | { |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3218 | RAMBlock *block; |
| 3219 | uint8_t *host = ptr; |
| 3220 | |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 3221 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 3222 | *ram_addr = xen_ram_addr_from_mapcache(ptr); |
Stefano Stabellini | 712c2b4 | 2011-05-19 18:35:46 +0100 | [diff] [blame] | 3223 | return 0; |
| 3224 | } |
| 3225 | |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3226 | QLIST_FOREACH(block, &ram_list.blocks, next) { |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3227 | /* This case append when the block is not mapped. */ |
| 3228 | if (block->host == NULL) { |
| 3229 | continue; |
| 3230 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3231 | if (host - block->host < block->length) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3232 | *ram_addr = block->offset + (host - block->host); |
| 3233 | return 0; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3234 | } |
pbrook | 94a6b54 | 2009-04-11 17:15:54 +0000 | [diff] [blame] | 3235 | } |
Jun Nakajima | 432d268 | 2010-08-31 16:41:25 +0100 | [diff] [blame] | 3236 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3237 | return -1; |
| 3238 | } |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3239 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3240 | /* Some of the softmmu routines need to translate from a host pointer |
| 3241 | (typically a TLB entry) back to a ram offset. */ |
| 3242 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) |
| 3243 | { |
| 3244 | ram_addr_t ram_addr; |
Alex Williamson | f471a17 | 2010-06-11 11:11:42 -0600 | [diff] [blame] | 3245 | |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 3246 | if (qemu_ram_addr_from_host(ptr, &ram_addr)) { |
| 3247 | fprintf(stderr, "Bad ram pointer %p\n", ptr); |
| 3248 | abort(); |
| 3249 | } |
| 3250 | return ram_addr; |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3251 | } |
| 3252 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3253 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3254 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3255 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 3256 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3257 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3258 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3259 | cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 1); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3260 | #endif |
| 3261 | return 0; |
| 3262 | } |
| 3263 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3264 | static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3265 | { |
| 3266 | #ifdef DEBUG_UNASSIGNED |
| 3267 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 3268 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3269 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3270 | cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 2); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3271 | #endif |
| 3272 | return 0; |
| 3273 | } |
| 3274 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3275 | static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3276 | { |
| 3277 | #ifdef DEBUG_UNASSIGNED |
| 3278 | printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); |
| 3279 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3280 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3281 | cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 3282 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3283 | return 0; |
| 3284 | } |
| 3285 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3286 | static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3287 | { |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3288 | #ifdef DEBUG_UNASSIGNED |
blueswir1 | ab3d172 | 2007-11-04 07:31:40 +0000 | [diff] [blame] | 3289 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
pbrook | 67d3b95 | 2006-12-18 05:03:52 +0000 | [diff] [blame] | 3290 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3291 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3292 | cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 1); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3293 | #endif |
| 3294 | } |
| 3295 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3296 | static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3297 | { |
| 3298 | #ifdef DEBUG_UNASSIGNED |
| 3299 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3300 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3301 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3302 | cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 2); |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3303 | #endif |
| 3304 | } |
| 3305 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3306 | static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3307 | { |
| 3308 | #ifdef DEBUG_UNASSIGNED |
| 3309 | printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val); |
| 3310 | #endif |
Richard Henderson | 5b45040 | 2011-04-18 16:13:12 -0700 | [diff] [blame] | 3311 | #if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE) |
Blue Swirl | b14ef7c | 2011-07-03 08:53:46 +0000 | [diff] [blame] | 3312 | cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, 4); |
blueswir1 | b4f0a31 | 2007-05-06 17:59:24 +0000 | [diff] [blame] | 3313 | #endif |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3314 | } |
| 3315 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3316 | static CPUReadMemoryFunc * const unassigned_mem_read[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3317 | unassigned_mem_readb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3318 | unassigned_mem_readw, |
| 3319 | unassigned_mem_readl, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3320 | }; |
| 3321 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3322 | static CPUWriteMemoryFunc * const unassigned_mem_write[3] = { |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3323 | unassigned_mem_writeb, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 3324 | unassigned_mem_writew, |
| 3325 | unassigned_mem_writel, |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3326 | }; |
| 3327 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3328 | static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3329 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3330 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3331 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3332 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3333 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3334 | #if !defined(CONFIG_USER_ONLY) |
| 3335 | tb_invalidate_phys_page_fast(ram_addr, 1); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3336 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3337 | #endif |
| 3338 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3339 | stb_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3340 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3341 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3342 | /* we remove the notdirty callback only if the code has been |
| 3343 | flushed */ |
| 3344 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3345 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3346 | } |
| 3347 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3348 | static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3349 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3350 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3351 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3352 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3353 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3354 | #if !defined(CONFIG_USER_ONLY) |
| 3355 | tb_invalidate_phys_page_fast(ram_addr, 2); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3356 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3357 | #endif |
| 3358 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3359 | stw_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3360 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3361 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3362 | /* we remove the notdirty callback only if the code has been |
| 3363 | flushed */ |
| 3364 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3365 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3366 | } |
| 3367 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3368 | static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr, |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3369 | uint32_t val) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3370 | { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3371 | int dirty_flags; |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3372 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3373 | if (!(dirty_flags & CODE_DIRTY_FLAG)) { |
| 3374 | #if !defined(CONFIG_USER_ONLY) |
| 3375 | tb_invalidate_phys_page_fast(ram_addr, 4); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3376 | dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3377 | #endif |
| 3378 | } |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3379 | stl_p(qemu_get_ram_ptr(ram_addr), val); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3380 | dirty_flags |= (0xff & ~CODE_DIRTY_FLAG); |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3381 | cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags); |
bellard | f23db16 | 2005-08-21 19:12:28 +0000 | [diff] [blame] | 3382 | /* we remove the notdirty callback only if the code has been |
| 3383 | flushed */ |
| 3384 | if (dirty_flags == 0xff) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3385 | tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3386 | } |
| 3387 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3388 | static CPUReadMemoryFunc * const error_mem_read[3] = { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3389 | NULL, /* never used */ |
| 3390 | NULL, /* never used */ |
| 3391 | NULL, /* never used */ |
| 3392 | }; |
| 3393 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3394 | static CPUWriteMemoryFunc * const notdirty_mem_write[3] = { |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 3395 | notdirty_mem_writeb, |
| 3396 | notdirty_mem_writew, |
| 3397 | notdirty_mem_writel, |
| 3398 | }; |
| 3399 | |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3400 | /* Generate a debug exception if a watchpoint has been hit. */ |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3401 | static void check_watchpoint(int offset, int len_mask, int flags) |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3402 | { |
| 3403 | CPUState *env = cpu_single_env; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3404 | target_ulong pc, cs_base; |
| 3405 | TranslationBlock *tb; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3406 | target_ulong vaddr; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 3407 | CPUWatchpoint *wp; |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3408 | int cpu_flags; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3409 | |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3410 | if (env->watchpoint_hit) { |
| 3411 | /* We re-entered the check after replacing the TB. Now raise |
| 3412 | * the debug interrupt so that is will trigger after the |
| 3413 | * current instruction. */ |
| 3414 | cpu_interrupt(env, CPU_INTERRUPT_DEBUG); |
| 3415 | return; |
| 3416 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3417 | vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 3418 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3419 | if ((vaddr == (wp->vaddr & len_mask) || |
| 3420 | (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3421 | wp->flags |= BP_WATCHPOINT_HIT; |
| 3422 | if (!env->watchpoint_hit) { |
| 3423 | env->watchpoint_hit = wp; |
| 3424 | tb = tb_find_pc(env->mem_io_pc); |
| 3425 | if (!tb) { |
| 3426 | cpu_abort(env, "check_watchpoint: could not find TB for " |
| 3427 | "pc=%p", (void *)env->mem_io_pc); |
| 3428 | } |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 3429 | cpu_restore_state(tb, env, env->mem_io_pc); |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3430 | tb_phys_invalidate(tb, -1); |
| 3431 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { |
| 3432 | env->exception_index = EXCP_DEBUG; |
| 3433 | } else { |
| 3434 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); |
| 3435 | tb_gen_code(env, pc, cs_base, cpu_flags, 1); |
| 3436 | } |
| 3437 | cpu_resume_from_signal(env, NULL); |
aliguori | 06d55cc | 2008-11-18 20:24:06 +0000 | [diff] [blame] | 3438 | } |
aliguori | 6e140f2 | 2008-11-18 20:37:55 +0000 | [diff] [blame] | 3439 | } else { |
| 3440 | wp->flags &= ~BP_WATCHPOINT_HIT; |
pbrook | 0f459d1 | 2008-06-09 00:20:13 +0000 | [diff] [blame] | 3441 | } |
| 3442 | } |
| 3443 | } |
| 3444 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3445 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, |
| 3446 | so these check for a hit then pass through to the normal out-of-line |
| 3447 | phys routines. */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3448 | static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3449 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3450 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3451 | return ldub_phys(addr); |
| 3452 | } |
| 3453 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3454 | static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3455 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3456 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3457 | return lduw_phys(addr); |
| 3458 | } |
| 3459 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3460 | static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr) |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3461 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3462 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3463 | return ldl_phys(addr); |
| 3464 | } |
| 3465 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3466 | static void watch_mem_writeb(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3467 | uint32_t val) |
| 3468 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3469 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3470 | stb_phys(addr, val); |
| 3471 | } |
| 3472 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3473 | static void watch_mem_writew(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3474 | uint32_t val) |
| 3475 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3476 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3477 | stw_phys(addr, val); |
| 3478 | } |
| 3479 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3480 | static void watch_mem_writel(void *opaque, target_phys_addr_t addr, |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3481 | uint32_t val) |
| 3482 | { |
aliguori | b405133 | 2008-11-18 20:14:20 +0000 | [diff] [blame] | 3483 | check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3484 | stl_phys(addr, val); |
| 3485 | } |
| 3486 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3487 | static CPUReadMemoryFunc * const watch_mem_read[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3488 | watch_mem_readb, |
| 3489 | watch_mem_readw, |
| 3490 | watch_mem_readl, |
| 3491 | }; |
| 3492 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3493 | static CPUWriteMemoryFunc * const watch_mem_write[3] = { |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3494 | watch_mem_writeb, |
| 3495 | watch_mem_writew, |
| 3496 | watch_mem_writel, |
| 3497 | }; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 3498 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3499 | static inline uint32_t subpage_readlen (subpage_t *mmio, |
| 3500 | target_phys_addr_t addr, |
| 3501 | unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3502 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3503 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3504 | #if defined(DEBUG_SUBPAGE) |
| 3505 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__, |
| 3506 | mmio, len, addr, idx); |
| 3507 | #endif |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3508 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3509 | addr += mmio->region_offset[idx]; |
| 3510 | idx = mmio->sub_io_index[idx]; |
| 3511 | return io_mem_read[idx][len](io_mem_opaque[idx], addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3512 | } |
| 3513 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3514 | static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr, |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3515 | uint32_t value, unsigned int len) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3516 | { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3517 | unsigned int idx = SUBPAGE_IDX(addr); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3518 | #if defined(DEBUG_SUBPAGE) |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3519 | printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", |
| 3520 | __func__, mmio, len, addr, idx, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3521 | #endif |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3522 | |
| 3523 | addr += mmio->region_offset[idx]; |
| 3524 | idx = mmio->sub_io_index[idx]; |
| 3525 | io_mem_write[idx][len](io_mem_opaque[idx], addr, value); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3526 | } |
| 3527 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3528 | static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3529 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3530 | return subpage_readlen(opaque, addr, 0); |
| 3531 | } |
| 3532 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3533 | static void subpage_writeb (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3534 | uint32_t value) |
| 3535 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3536 | subpage_writelen(opaque, addr, value, 0); |
| 3537 | } |
| 3538 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3539 | static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3540 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3541 | return subpage_readlen(opaque, addr, 1); |
| 3542 | } |
| 3543 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3544 | static void subpage_writew (void *opaque, target_phys_addr_t addr, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3545 | uint32_t value) |
| 3546 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3547 | subpage_writelen(opaque, addr, value, 1); |
| 3548 | } |
| 3549 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3550 | static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3551 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3552 | return subpage_readlen(opaque, addr, 2); |
| 3553 | } |
| 3554 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3555 | static void subpage_writel (void *opaque, target_phys_addr_t addr, |
| 3556 | uint32_t value) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3557 | { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3558 | subpage_writelen(opaque, addr, value, 2); |
| 3559 | } |
| 3560 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3561 | static CPUReadMemoryFunc * const subpage_read[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3562 | &subpage_readb, |
| 3563 | &subpage_readw, |
| 3564 | &subpage_readl, |
| 3565 | }; |
| 3566 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3567 | static CPUWriteMemoryFunc * const subpage_write[] = { |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3568 | &subpage_writeb, |
| 3569 | &subpage_writew, |
| 3570 | &subpage_writel, |
| 3571 | }; |
| 3572 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3573 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, |
| 3574 | ram_addr_t memory, ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3575 | { |
| 3576 | int idx, eidx; |
| 3577 | |
| 3578 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) |
| 3579 | return -1; |
| 3580 | idx = SUBPAGE_IDX(start); |
| 3581 | eidx = SUBPAGE_IDX(end); |
| 3582 | #if defined(DEBUG_SUBPAGE) |
Blue Swirl | 0bf9e31 | 2009-07-20 17:19:25 +0000 | [diff] [blame] | 3583 | printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__, |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3584 | mmio, start, end, idx, eidx, memory); |
| 3585 | #endif |
Gleb Natapov | 95c318f | 2010-07-29 10:41:45 +0300 | [diff] [blame] | 3586 | if ((memory & ~TARGET_PAGE_MASK) == IO_MEM_RAM) |
| 3587 | memory = IO_MEM_UNASSIGNED; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3588 | memory = (memory >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3589 | for (; idx <= eidx; idx++) { |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3590 | mmio->sub_io_index[idx] = memory; |
| 3591 | mmio->region_offset[idx] = region_offset; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3592 | } |
| 3593 | |
| 3594 | return 0; |
| 3595 | } |
| 3596 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3597 | static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys, |
| 3598 | ram_addr_t orig_memory, |
| 3599 | ram_addr_t region_offset) |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3600 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3601 | subpage_t *mmio; |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3602 | int subpage_memory; |
| 3603 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3604 | mmio = g_malloc0(sizeof(subpage_t)); |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3605 | |
| 3606 | mmio->base = base; |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3607 | subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio, |
| 3608 | DEVICE_NATIVE_ENDIAN); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3609 | #if defined(DEBUG_SUBPAGE) |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3610 | printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__, |
| 3611 | mmio, base, TARGET_PAGE_SIZE, subpage_memory); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3612 | #endif |
aliguori | 1eec614 | 2009-02-05 22:06:18 +0000 | [diff] [blame] | 3613 | *phys = subpage_memory | IO_MEM_SUBPAGE; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3614 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, orig_memory, region_offset); |
blueswir1 | db7b542 | 2007-05-26 17:36:03 +0000 | [diff] [blame] | 3615 | |
| 3616 | return mmio; |
| 3617 | } |
| 3618 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3619 | static int get_free_io_mem_idx(void) |
| 3620 | { |
| 3621 | int i; |
| 3622 | |
| 3623 | for (i = 0; i<IO_MEM_NB_ENTRIES; i++) |
| 3624 | if (!io_mem_used[i]) { |
| 3625 | io_mem_used[i] = 1; |
| 3626 | return i; |
| 3627 | } |
Riku Voipio | c6703b4 | 2009-12-03 15:56:05 +0200 | [diff] [blame] | 3628 | fprintf(stderr, "RAN out out io_mem_idx, max %d !\n", IO_MEM_NB_ENTRIES); |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3629 | return -1; |
| 3630 | } |
| 3631 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3632 | /* |
| 3633 | * Usually, devices operate in little endian mode. There are devices out |
| 3634 | * there that operate in big endian too. Each device gets byte swapped |
| 3635 | * mmio if plugged onto a CPU that does the other endianness. |
| 3636 | * |
| 3637 | * CPU Device swap? |
| 3638 | * |
| 3639 | * little little no |
| 3640 | * little big yes |
| 3641 | * big little yes |
| 3642 | * big big no |
| 3643 | */ |
| 3644 | |
| 3645 | typedef struct SwapEndianContainer { |
| 3646 | CPUReadMemoryFunc *read[3]; |
| 3647 | CPUWriteMemoryFunc *write[3]; |
| 3648 | void *opaque; |
| 3649 | } SwapEndianContainer; |
| 3650 | |
| 3651 | static uint32_t swapendian_mem_readb (void *opaque, target_phys_addr_t addr) |
| 3652 | { |
| 3653 | uint32_t val; |
| 3654 | SwapEndianContainer *c = opaque; |
| 3655 | val = c->read[0](c->opaque, addr); |
| 3656 | return val; |
| 3657 | } |
| 3658 | |
| 3659 | static uint32_t swapendian_mem_readw(void *opaque, target_phys_addr_t addr) |
| 3660 | { |
| 3661 | uint32_t val; |
| 3662 | SwapEndianContainer *c = opaque; |
| 3663 | val = bswap16(c->read[1](c->opaque, addr)); |
| 3664 | return val; |
| 3665 | } |
| 3666 | |
| 3667 | static uint32_t swapendian_mem_readl(void *opaque, target_phys_addr_t addr) |
| 3668 | { |
| 3669 | uint32_t val; |
| 3670 | SwapEndianContainer *c = opaque; |
| 3671 | val = bswap32(c->read[2](c->opaque, addr)); |
| 3672 | return val; |
| 3673 | } |
| 3674 | |
| 3675 | static CPUReadMemoryFunc * const swapendian_readfn[3]={ |
| 3676 | swapendian_mem_readb, |
| 3677 | swapendian_mem_readw, |
| 3678 | swapendian_mem_readl |
| 3679 | }; |
| 3680 | |
| 3681 | static void swapendian_mem_writeb(void *opaque, target_phys_addr_t addr, |
| 3682 | uint32_t val) |
| 3683 | { |
| 3684 | SwapEndianContainer *c = opaque; |
| 3685 | c->write[0](c->opaque, addr, val); |
| 3686 | } |
| 3687 | |
| 3688 | static void swapendian_mem_writew(void *opaque, target_phys_addr_t addr, |
| 3689 | uint32_t val) |
| 3690 | { |
| 3691 | SwapEndianContainer *c = opaque; |
| 3692 | c->write[1](c->opaque, addr, bswap16(val)); |
| 3693 | } |
| 3694 | |
| 3695 | static void swapendian_mem_writel(void *opaque, target_phys_addr_t addr, |
| 3696 | uint32_t val) |
| 3697 | { |
| 3698 | SwapEndianContainer *c = opaque; |
| 3699 | c->write[2](c->opaque, addr, bswap32(val)); |
| 3700 | } |
| 3701 | |
| 3702 | static CPUWriteMemoryFunc * const swapendian_writefn[3]={ |
| 3703 | swapendian_mem_writeb, |
| 3704 | swapendian_mem_writew, |
| 3705 | swapendian_mem_writel |
| 3706 | }; |
| 3707 | |
| 3708 | static void swapendian_init(int io_index) |
| 3709 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3710 | SwapEndianContainer *c = g_malloc(sizeof(SwapEndianContainer)); |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3711 | int i; |
| 3712 | |
| 3713 | /* Swap mmio for big endian targets */ |
| 3714 | c->opaque = io_mem_opaque[io_index]; |
| 3715 | for (i = 0; i < 3; i++) { |
| 3716 | c->read[i] = io_mem_read[io_index][i]; |
| 3717 | c->write[i] = io_mem_write[io_index][i]; |
| 3718 | |
| 3719 | io_mem_read[io_index][i] = swapendian_readfn[i]; |
| 3720 | io_mem_write[io_index][i] = swapendian_writefn[i]; |
| 3721 | } |
| 3722 | io_mem_opaque[io_index] = c; |
| 3723 | } |
| 3724 | |
| 3725 | static void swapendian_del(int io_index) |
| 3726 | { |
| 3727 | if (io_mem_read[io_index][0] == swapendian_readfn[0]) { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3728 | g_free(io_mem_opaque[io_index]); |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3729 | } |
| 3730 | } |
| 3731 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3732 | /* mem_read and mem_write are arrays of functions containing the |
| 3733 | function to access byte (index 0), word (index 1) and dword (index |
Paul Brook | 0b4e6e3 | 2009-04-30 18:37:55 +0100 | [diff] [blame] | 3734 | 2). Functions can be omitted with a NULL function pointer. |
blueswir1 | 3ee8992 | 2008-01-02 19:45:26 +0000 | [diff] [blame] | 3735 | If io_index is non zero, the corresponding io zone is |
blueswir1 | 4254fab | 2008-01-01 16:57:19 +0000 | [diff] [blame] | 3736 | modified. If it is zero, a new io zone is allocated. The return |
| 3737 | value can be used with cpu_register_physical_memory(). (-1) is |
| 3738 | returned if error. */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3739 | static int cpu_register_io_memory_fixed(int io_index, |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3740 | CPUReadMemoryFunc * const *mem_read, |
| 3741 | CPUWriteMemoryFunc * const *mem_write, |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3742 | void *opaque, enum device_endian endian) |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3743 | { |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3744 | int i; |
| 3745 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3746 | if (io_index <= 0) { |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3747 | io_index = get_free_io_mem_idx(); |
| 3748 | if (io_index == -1) |
| 3749 | return io_index; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3750 | } else { |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3751 | io_index >>= IO_MEM_SHIFT; |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3752 | if (io_index >= IO_MEM_NB_ENTRIES) |
| 3753 | return -1; |
| 3754 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3755 | |
Richard Henderson | 3cab721 | 2010-05-07 09:52:51 -0700 | [diff] [blame] | 3756 | for (i = 0; i < 3; ++i) { |
| 3757 | io_mem_read[io_index][i] |
| 3758 | = (mem_read[i] ? mem_read[i] : unassigned_mem_read[i]); |
| 3759 | } |
| 3760 | for (i = 0; i < 3; ++i) { |
| 3761 | io_mem_write[io_index][i] |
| 3762 | = (mem_write[i] ? mem_write[i] : unassigned_mem_write[i]); |
| 3763 | } |
bellard | a4193c8 | 2004-06-03 14:01:43 +0000 | [diff] [blame] | 3764 | io_mem_opaque[io_index] = opaque; |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3765 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3766 | switch (endian) { |
| 3767 | case DEVICE_BIG_ENDIAN: |
| 3768 | #ifndef TARGET_WORDS_BIGENDIAN |
| 3769 | swapendian_init(io_index); |
| 3770 | #endif |
| 3771 | break; |
| 3772 | case DEVICE_LITTLE_ENDIAN: |
| 3773 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3774 | swapendian_init(io_index); |
| 3775 | #endif |
| 3776 | break; |
| 3777 | case DEVICE_NATIVE_ENDIAN: |
| 3778 | default: |
| 3779 | break; |
| 3780 | } |
| 3781 | |
Richard Henderson | f640524 | 2010-04-22 16:47:31 -0700 | [diff] [blame] | 3782 | return (io_index << IO_MEM_SHIFT); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 3783 | } |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 3784 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3785 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
| 3786 | CPUWriteMemoryFunc * const *mem_write, |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3787 | void *opaque, enum device_endian endian) |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3788 | { |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3789 | return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian); |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3790 | } |
| 3791 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3792 | void cpu_unregister_io_memory(int io_table_address) |
| 3793 | { |
| 3794 | int i; |
| 3795 | int io_index = io_table_address >> IO_MEM_SHIFT; |
| 3796 | |
Alexander Graf | dd31053 | 2010-12-08 12:05:36 +0100 | [diff] [blame] | 3797 | swapendian_del(io_index); |
| 3798 | |
aliguori | 8871565 | 2009-02-11 15:20:58 +0000 | [diff] [blame] | 3799 | for (i=0;i < 3; i++) { |
| 3800 | io_mem_read[io_index][i] = unassigned_mem_read[i]; |
| 3801 | io_mem_write[io_index][i] = unassigned_mem_write[i]; |
| 3802 | } |
| 3803 | io_mem_opaque[io_index] = NULL; |
| 3804 | io_mem_used[io_index] = 0; |
| 3805 | } |
| 3806 | |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3807 | static void io_mem_init(void) |
| 3808 | { |
| 3809 | int i; |
| 3810 | |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3811 | cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, |
| 3812 | unassigned_mem_write, NULL, |
| 3813 | DEVICE_NATIVE_ENDIAN); |
| 3814 | cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, |
| 3815 | unassigned_mem_write, NULL, |
| 3816 | DEVICE_NATIVE_ENDIAN); |
| 3817 | cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, |
| 3818 | notdirty_mem_write, NULL, |
| 3819 | DEVICE_NATIVE_ENDIAN); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3820 | for (i=0; i<5; i++) |
| 3821 | io_mem_used[i] = 1; |
| 3822 | |
| 3823 | io_mem_watch = cpu_register_io_memory(watch_mem_read, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 3824 | watch_mem_write, NULL, |
| 3825 | DEVICE_NATIVE_ENDIAN); |
Avi Kivity | e9179ce | 2009-06-14 11:38:52 +0300 | [diff] [blame] | 3826 | } |
| 3827 | |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3828 | static void memory_map_init(void) |
| 3829 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3830 | system_memory = g_malloc(sizeof(*system_memory)); |
Avi Kivity | 8417ceb | 2011-08-03 11:56:14 +0300 | [diff] [blame] | 3831 | memory_region_init(system_memory, "system", INT64_MAX); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3832 | set_system_memory_map(system_memory); |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3833 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 3834 | system_io = g_malloc(sizeof(*system_io)); |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3835 | memory_region_init(system_io, "io", 65536); |
| 3836 | set_system_io_map(system_io); |
Avi Kivity | 62152b8 | 2011-07-26 14:26:14 +0300 | [diff] [blame] | 3837 | } |
| 3838 | |
| 3839 | MemoryRegion *get_system_memory(void) |
| 3840 | { |
| 3841 | return system_memory; |
| 3842 | } |
| 3843 | |
Avi Kivity | 309cb47 | 2011-08-08 16:09:03 +0300 | [diff] [blame] | 3844 | MemoryRegion *get_system_io(void) |
| 3845 | { |
| 3846 | return system_io; |
| 3847 | } |
| 3848 | |
pbrook | e2eef17 | 2008-06-08 01:09:01 +0000 | [diff] [blame] | 3849 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 3850 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3851 | /* physical memory access (slow version, mainly for debug) */ |
| 3852 | #if defined(CONFIG_USER_ONLY) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3853 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 3854 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3855 | { |
| 3856 | int l, flags; |
| 3857 | target_ulong page; |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 3858 | void * p; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3859 | |
| 3860 | while (len > 0) { |
| 3861 | page = addr & TARGET_PAGE_MASK; |
| 3862 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3863 | if (l > len) |
| 3864 | l = len; |
| 3865 | flags = page_get_flags(page); |
| 3866 | if (!(flags & PAGE_VALID)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3867 | return -1; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3868 | if (is_write) { |
| 3869 | if (!(flags & PAGE_WRITE)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3870 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3871 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3872 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3873 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3874 | memcpy(p, buf, l); |
| 3875 | unlock_user(p, addr, l); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3876 | } else { |
| 3877 | if (!(flags & PAGE_READ)) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3878 | return -1; |
bellard | 579a97f | 2007-11-11 14:26:47 +0000 | [diff] [blame] | 3879 | /* XXX: this code should not depend on lock_user */ |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3880 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3881 | return -1; |
aurel32 | 72fb7da | 2008-04-27 23:53:45 +0000 | [diff] [blame] | 3882 | memcpy(buf, p, l); |
aurel32 | 5b25757 | 2008-04-28 08:54:59 +0000 | [diff] [blame] | 3883 | unlock_user(p, addr, 0); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3884 | } |
| 3885 | len -= l; |
| 3886 | buf += l; |
| 3887 | addr += l; |
| 3888 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 3889 | return 0; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3890 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3891 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3892 | #else |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3893 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3894 | int len, int is_write) |
| 3895 | { |
| 3896 | int l, io_index; |
| 3897 | uint8_t *ptr; |
| 3898 | uint32_t val; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3899 | target_phys_addr_t page; |
Anthony PERARD | 8ca5692 | 2011-07-15 04:32:53 +0000 | [diff] [blame] | 3900 | ram_addr_t pd; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3901 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3902 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3903 | while (len > 0) { |
| 3904 | page = addr & TARGET_PAGE_MASK; |
| 3905 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 3906 | if (l > len) |
| 3907 | l = len; |
bellard | 92e873b | 2004-05-21 14:52:29 +0000 | [diff] [blame] | 3908 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3909 | if (!p) { |
| 3910 | pd = IO_MEM_UNASSIGNED; |
| 3911 | } else { |
| 3912 | pd = p->phys_offset; |
| 3913 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3914 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3915 | if (is_write) { |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3916 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3917 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3918 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3919 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3920 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 3921 | /* XXX: could force cpu_single_env to NULL to avoid |
| 3922 | potential bugs */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3923 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3924 | /* 32 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3925 | val = ldl_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3926 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3927 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3928 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3929 | /* 16 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3930 | val = lduw_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3931 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3932 | l = 2; |
| 3933 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3934 | /* 8 bit write access */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3935 | val = ldub_p(buf); |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3936 | io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3937 | l = 1; |
| 3938 | } |
| 3939 | } else { |
Anthony PERARD | 8ca5692 | 2011-07-15 04:32:53 +0000 | [diff] [blame] | 3940 | ram_addr_t addr1; |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 3941 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3942 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 3943 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3944 | memcpy(ptr, buf, l); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3945 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 3946 | /* invalidate code */ |
| 3947 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 3948 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 3949 | cpu_physical_memory_set_dirty_flags( |
| 3950 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 3951 | } |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3952 | qemu_put_ram_ptr(ptr); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3953 | } |
| 3954 | } else { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3955 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 3956 | !(pd & IO_MEM_ROMD)) { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3957 | target_phys_addr_t addr1 = addr; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3958 | /* I/O case */ |
| 3959 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 3960 | if (p) |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3961 | addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 3962 | if (l >= 4 && ((addr1 & 3) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3963 | /* 32 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3964 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3965 | stl_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3966 | l = 4; |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3967 | } else if (l >= 2 && ((addr1 & 1) == 0)) { |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3968 | /* 16 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3969 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3970 | stw_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3971 | l = 2; |
| 3972 | } else { |
bellard | 1c213d1 | 2005-09-03 10:49:04 +0000 | [diff] [blame] | 3973 | /* 8 bit read access */ |
aurel32 | 6c2934d | 2009-02-18 21:37:17 +0000 | [diff] [blame] | 3974 | val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 3975 | stb_p(buf, val); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3976 | l = 1; |
| 3977 | } |
| 3978 | } else { |
| 3979 | /* RAM case */ |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 3980 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK); |
| 3981 | memcpy(buf, ptr + (addr & ~TARGET_PAGE_MASK), l); |
| 3982 | qemu_put_ram_ptr(ptr); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 3983 | } |
| 3984 | } |
| 3985 | len -= l; |
| 3986 | buf += l; |
| 3987 | addr += l; |
| 3988 | } |
| 3989 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 3990 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3991 | /* used for ROM loading : can write in RAM and ROM */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3992 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3993 | const uint8_t *buf, int len) |
| 3994 | { |
| 3995 | int l; |
| 3996 | uint8_t *ptr; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3997 | target_phys_addr_t page; |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 3998 | unsigned long pd; |
| 3999 | PhysPageDesc *p; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4000 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4001 | while (len > 0) { |
| 4002 | page = addr & TARGET_PAGE_MASK; |
| 4003 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4004 | if (l > len) |
| 4005 | l = len; |
| 4006 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 4007 | if (!p) { |
| 4008 | pd = IO_MEM_UNASSIGNED; |
| 4009 | } else { |
| 4010 | pd = p->phys_offset; |
| 4011 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4012 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4013 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 4014 | (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && |
| 4015 | !(pd & IO_MEM_ROMD)) { |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4016 | /* do nothing */ |
| 4017 | } else { |
| 4018 | unsigned long addr1; |
| 4019 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4020 | /* ROM/RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4021 | ptr = qemu_get_ram_ptr(addr1); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4022 | memcpy(ptr, buf, l); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 4023 | qemu_put_ram_ptr(ptr); |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4024 | } |
| 4025 | len -= l; |
| 4026 | buf += l; |
| 4027 | addr += l; |
| 4028 | } |
| 4029 | } |
| 4030 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4031 | typedef struct { |
| 4032 | void *buffer; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4033 | target_phys_addr_t addr; |
| 4034 | target_phys_addr_t len; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4035 | } BounceBuffer; |
| 4036 | |
| 4037 | static BounceBuffer bounce; |
| 4038 | |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4039 | typedef struct MapClient { |
| 4040 | void *opaque; |
| 4041 | void (*callback)(void *opaque); |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 4042 | QLIST_ENTRY(MapClient) link; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4043 | } MapClient; |
| 4044 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 4045 | static QLIST_HEAD(map_client_list, MapClient) map_client_list |
| 4046 | = QLIST_HEAD_INITIALIZER(map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4047 | |
| 4048 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) |
| 4049 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 4050 | MapClient *client = g_malloc(sizeof(*client)); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4051 | |
| 4052 | client->opaque = opaque; |
| 4053 | client->callback = callback; |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 4054 | QLIST_INSERT_HEAD(&map_client_list, client, link); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4055 | return client; |
| 4056 | } |
| 4057 | |
| 4058 | void cpu_unregister_map_client(void *_client) |
| 4059 | { |
| 4060 | MapClient *client = (MapClient *)_client; |
| 4061 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 4062 | QLIST_REMOVE(client, link); |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 4063 | g_free(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4064 | } |
| 4065 | |
| 4066 | static void cpu_notify_map_clients(void) |
| 4067 | { |
| 4068 | MapClient *client; |
| 4069 | |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 4070 | while (!QLIST_EMPTY(&map_client_list)) { |
| 4071 | client = QLIST_FIRST(&map_client_list); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4072 | client->callback(client->opaque); |
Isaku Yamahata | 34d5e94 | 2009-06-26 18:57:18 +0900 | [diff] [blame] | 4073 | cpu_unregister_map_client(client); |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4074 | } |
| 4075 | } |
| 4076 | |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4077 | /* Map a physical memory region into a host virtual address. |
| 4078 | * May map a subset of the requested range, given by and returned in *plen. |
| 4079 | * May return NULL if resources needed to perform the mapping are exhausted. |
| 4080 | * Use only for reads OR writes - not for read-modify-write operations. |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4081 | * Use cpu_register_map_client() to know when retrying the map operation is |
| 4082 | * likely to succeed. |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4083 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4084 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
| 4085 | target_phys_addr_t *plen, |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4086 | int is_write) |
| 4087 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4088 | target_phys_addr_t len = *plen; |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4089 | target_phys_addr_t todo = 0; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4090 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4091 | target_phys_addr_t page; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4092 | unsigned long pd; |
| 4093 | PhysPageDesc *p; |
Anthony PERARD | f15fbc4 | 2011-07-20 08:17:42 +0000 | [diff] [blame] | 4094 | ram_addr_t raddr = RAM_ADDR_MAX; |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 4095 | ram_addr_t rlen; |
| 4096 | void *ret; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4097 | |
| 4098 | while (len > 0) { |
| 4099 | page = addr & TARGET_PAGE_MASK; |
| 4100 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4101 | if (l > len) |
| 4102 | l = len; |
| 4103 | p = phys_page_find(page >> TARGET_PAGE_BITS); |
| 4104 | if (!p) { |
| 4105 | pd = IO_MEM_UNASSIGNED; |
| 4106 | } else { |
| 4107 | pd = p->phys_offset; |
| 4108 | } |
| 4109 | |
| 4110 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4111 | if (todo || bounce.buffer) { |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4112 | break; |
| 4113 | } |
| 4114 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE); |
| 4115 | bounce.addr = addr; |
| 4116 | bounce.len = l; |
| 4117 | if (!is_write) { |
Stefan Weil | 54f7b4a | 2011-04-10 18:23:39 +0200 | [diff] [blame] | 4118 | cpu_physical_memory_read(addr, bounce.buffer, l); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4119 | } |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4120 | |
| 4121 | *plen = l; |
| 4122 | return bounce.buffer; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4123 | } |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 4124 | if (!todo) { |
| 4125 | raddr = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4126 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4127 | |
| 4128 | len -= l; |
| 4129 | addr += l; |
Stefano Stabellini | 38bee5d | 2011-05-19 18:35:45 +0100 | [diff] [blame] | 4130 | todo += l; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4131 | } |
Stefano Stabellini | 8ab934f | 2011-06-27 18:26:06 +0100 | [diff] [blame] | 4132 | rlen = todo; |
| 4133 | ret = qemu_ram_ptr_length(raddr, &rlen); |
| 4134 | *plen = rlen; |
| 4135 | return ret; |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4136 | } |
| 4137 | |
| 4138 | /* Unmaps a memory region previously mapped by cpu_physical_memory_map(). |
| 4139 | * Will also mark the memory as dirty if is_write == 1. access_len gives |
| 4140 | * the amount of memory that was actually read or written by the caller. |
| 4141 | */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4142 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
| 4143 | int is_write, target_phys_addr_t access_len) |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4144 | { |
| 4145 | if (buffer != bounce.buffer) { |
| 4146 | if (is_write) { |
Marcelo Tosatti | e890261 | 2010-10-11 15:31:19 -0300 | [diff] [blame] | 4147 | ram_addr_t addr1 = qemu_ram_addr_from_host_nofail(buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4148 | while (access_len) { |
| 4149 | unsigned l; |
| 4150 | l = TARGET_PAGE_SIZE; |
| 4151 | if (l > access_len) |
| 4152 | l = access_len; |
| 4153 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4154 | /* invalidate code */ |
| 4155 | tb_invalidate_phys_page_range(addr1, addr1 + l, 0); |
| 4156 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4157 | cpu_physical_memory_set_dirty_flags( |
| 4158 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4159 | } |
| 4160 | addr1 += l; |
| 4161 | access_len -= l; |
| 4162 | } |
| 4163 | } |
Jan Kiszka | 868bb33 | 2011-06-21 22:59:09 +0200 | [diff] [blame] | 4164 | if (xen_enabled()) { |
Jan Kiszka | e41d7c6 | 2011-06-21 22:59:08 +0200 | [diff] [blame] | 4165 | xen_invalidate_map_cache_entry(buffer); |
Anthony PERARD | 050a0dd | 2010-09-16 13:57:49 +0100 | [diff] [blame] | 4166 | } |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4167 | return; |
| 4168 | } |
| 4169 | if (is_write) { |
| 4170 | cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len); |
| 4171 | } |
Herve Poussineau | f8a8324 | 2010-01-24 21:23:56 +0000 | [diff] [blame] | 4172 | qemu_vfree(bounce.buffer); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4173 | bounce.buffer = NULL; |
aliguori | ba223c2 | 2009-01-22 16:59:16 +0000 | [diff] [blame] | 4174 | cpu_notify_map_clients(); |
aliguori | 6d16c2f | 2009-01-22 16:59:11 +0000 | [diff] [blame] | 4175 | } |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 4176 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4177 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4178 | static inline uint32_t ldl_phys_internal(target_phys_addr_t addr, |
| 4179 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4180 | { |
| 4181 | int io_index; |
| 4182 | uint8_t *ptr; |
| 4183 | uint32_t val; |
| 4184 | unsigned long pd; |
| 4185 | PhysPageDesc *p; |
| 4186 | |
| 4187 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4188 | if (!p) { |
| 4189 | pd = IO_MEM_UNASSIGNED; |
| 4190 | } else { |
| 4191 | pd = p->phys_offset; |
| 4192 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4193 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4194 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 4195 | !(pd & IO_MEM_ROMD)) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4196 | /* I/O case */ |
| 4197 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4198 | if (p) |
| 4199 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4200 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4201 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4202 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4203 | val = bswap32(val); |
| 4204 | } |
| 4205 | #else |
| 4206 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4207 | val = bswap32(val); |
| 4208 | } |
| 4209 | #endif |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4210 | } else { |
| 4211 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4212 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4213 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4214 | switch (endian) { |
| 4215 | case DEVICE_LITTLE_ENDIAN: |
| 4216 | val = ldl_le_p(ptr); |
| 4217 | break; |
| 4218 | case DEVICE_BIG_ENDIAN: |
| 4219 | val = ldl_be_p(ptr); |
| 4220 | break; |
| 4221 | default: |
| 4222 | val = ldl_p(ptr); |
| 4223 | break; |
| 4224 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4225 | } |
| 4226 | return val; |
| 4227 | } |
| 4228 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4229 | uint32_t ldl_phys(target_phys_addr_t addr) |
| 4230 | { |
| 4231 | return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4232 | } |
| 4233 | |
| 4234 | uint32_t ldl_le_phys(target_phys_addr_t addr) |
| 4235 | { |
| 4236 | return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4237 | } |
| 4238 | |
| 4239 | uint32_t ldl_be_phys(target_phys_addr_t addr) |
| 4240 | { |
| 4241 | return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4242 | } |
| 4243 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4244 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4245 | static inline uint64_t ldq_phys_internal(target_phys_addr_t addr, |
| 4246 | enum device_endian endian) |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4247 | { |
| 4248 | int io_index; |
| 4249 | uint8_t *ptr; |
| 4250 | uint64_t val; |
| 4251 | unsigned long pd; |
| 4252 | PhysPageDesc *p; |
| 4253 | |
| 4254 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4255 | if (!p) { |
| 4256 | pd = IO_MEM_UNASSIGNED; |
| 4257 | } else { |
| 4258 | pd = p->phys_offset; |
| 4259 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4260 | |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 4261 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 4262 | !(pd & IO_MEM_ROMD)) { |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4263 | /* I/O case */ |
| 4264 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4265 | if (p) |
| 4266 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4267 | |
| 4268 | /* XXX This is broken when device endian != cpu endian. |
| 4269 | Fix and add "endian" variable check */ |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4270 | #ifdef TARGET_WORDS_BIGENDIAN |
| 4271 | val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32; |
| 4272 | val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4); |
| 4273 | #else |
| 4274 | val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr); |
| 4275 | val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32; |
| 4276 | #endif |
| 4277 | } else { |
| 4278 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4279 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4280 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4281 | switch (endian) { |
| 4282 | case DEVICE_LITTLE_ENDIAN: |
| 4283 | val = ldq_le_p(ptr); |
| 4284 | break; |
| 4285 | case DEVICE_BIG_ENDIAN: |
| 4286 | val = ldq_be_p(ptr); |
| 4287 | break; |
| 4288 | default: |
| 4289 | val = ldq_p(ptr); |
| 4290 | break; |
| 4291 | } |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 4292 | } |
| 4293 | return val; |
| 4294 | } |
| 4295 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4296 | uint64_t ldq_phys(target_phys_addr_t addr) |
| 4297 | { |
| 4298 | return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4299 | } |
| 4300 | |
| 4301 | uint64_t ldq_le_phys(target_phys_addr_t addr) |
| 4302 | { |
| 4303 | return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4304 | } |
| 4305 | |
| 4306 | uint64_t ldq_be_phys(target_phys_addr_t addr) |
| 4307 | { |
| 4308 | return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4309 | } |
| 4310 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4311 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4312 | uint32_t ldub_phys(target_phys_addr_t addr) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4313 | { |
| 4314 | uint8_t val; |
| 4315 | cpu_physical_memory_read(addr, &val, 1); |
| 4316 | return val; |
| 4317 | } |
| 4318 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4319 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4320 | static inline uint32_t lduw_phys_internal(target_phys_addr_t addr, |
| 4321 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4322 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4323 | int io_index; |
| 4324 | uint8_t *ptr; |
| 4325 | uint64_t val; |
| 4326 | unsigned long pd; |
| 4327 | PhysPageDesc *p; |
| 4328 | |
| 4329 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4330 | if (!p) { |
| 4331 | pd = IO_MEM_UNASSIGNED; |
| 4332 | } else { |
| 4333 | pd = p->phys_offset; |
| 4334 | } |
| 4335 | |
| 4336 | if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && |
| 4337 | !(pd & IO_MEM_ROMD)) { |
| 4338 | /* I/O case */ |
| 4339 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 4340 | if (p) |
| 4341 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
| 4342 | val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4343 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4344 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4345 | val = bswap16(val); |
| 4346 | } |
| 4347 | #else |
| 4348 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4349 | val = bswap16(val); |
| 4350 | } |
| 4351 | #endif |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4352 | } else { |
| 4353 | /* RAM case */ |
| 4354 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
| 4355 | (addr & ~TARGET_PAGE_MASK); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4356 | switch (endian) { |
| 4357 | case DEVICE_LITTLE_ENDIAN: |
| 4358 | val = lduw_le_p(ptr); |
| 4359 | break; |
| 4360 | case DEVICE_BIG_ENDIAN: |
| 4361 | val = lduw_be_p(ptr); |
| 4362 | break; |
| 4363 | default: |
| 4364 | val = lduw_p(ptr); |
| 4365 | break; |
| 4366 | } |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4367 | } |
| 4368 | return val; |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4369 | } |
| 4370 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4371 | uint32_t lduw_phys(target_phys_addr_t addr) |
| 4372 | { |
| 4373 | return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN); |
| 4374 | } |
| 4375 | |
| 4376 | uint32_t lduw_le_phys(target_phys_addr_t addr) |
| 4377 | { |
| 4378 | return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN); |
| 4379 | } |
| 4380 | |
| 4381 | uint32_t lduw_be_phys(target_phys_addr_t addr) |
| 4382 | { |
| 4383 | return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN); |
| 4384 | } |
| 4385 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4386 | /* warning: addr must be aligned. The ram page is not masked as dirty |
| 4387 | and the code inside is not invalidated. It is useful if the dirty |
| 4388 | bits are used to track modified PTEs */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4389 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4390 | { |
| 4391 | int io_index; |
| 4392 | uint8_t *ptr; |
| 4393 | unsigned long pd; |
| 4394 | PhysPageDesc *p; |
| 4395 | |
| 4396 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4397 | if (!p) { |
| 4398 | pd = IO_MEM_UNASSIGNED; |
| 4399 | } else { |
| 4400 | pd = p->phys_offset; |
| 4401 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4402 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4403 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4404 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4405 | if (p) |
| 4406 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4407 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4408 | } else { |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4409 | unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4410 | ptr = qemu_get_ram_ptr(addr1); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4411 | stl_p(ptr, val); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4412 | |
| 4413 | if (unlikely(in_migration)) { |
| 4414 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4415 | /* invalidate code */ |
| 4416 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4417 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4418 | cpu_physical_memory_set_dirty_flags( |
| 4419 | addr1, (0xff & ~CODE_DIRTY_FLAG)); |
aliguori | 7457619 | 2008-10-06 14:02:03 +0000 | [diff] [blame] | 4420 | } |
| 4421 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4422 | } |
| 4423 | } |
| 4424 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4425 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val) |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4426 | { |
| 4427 | int io_index; |
| 4428 | uint8_t *ptr; |
| 4429 | unsigned long pd; |
| 4430 | PhysPageDesc *p; |
| 4431 | |
| 4432 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4433 | if (!p) { |
| 4434 | pd = IO_MEM_UNASSIGNED; |
| 4435 | } else { |
| 4436 | pd = p->phys_offset; |
| 4437 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4438 | |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4439 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 4440 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4441 | if (p) |
| 4442 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4443 | #ifdef TARGET_WORDS_BIGENDIAN |
| 4444 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32); |
| 4445 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val); |
| 4446 | #else |
| 4447 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4448 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32); |
| 4449 | #endif |
| 4450 | } else { |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4451 | ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) + |
j_mayer | bc98a7e | 2007-04-04 07:55:12 +0000 | [diff] [blame] | 4452 | (addr & ~TARGET_PAGE_MASK); |
| 4453 | stq_p(ptr, val); |
| 4454 | } |
| 4455 | } |
| 4456 | |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4457 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4458 | static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val, |
| 4459 | enum device_endian endian) |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4460 | { |
| 4461 | int io_index; |
| 4462 | uint8_t *ptr; |
| 4463 | unsigned long pd; |
| 4464 | PhysPageDesc *p; |
| 4465 | |
| 4466 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4467 | if (!p) { |
| 4468 | pd = IO_MEM_UNASSIGNED; |
| 4469 | } else { |
| 4470 | pd = p->phys_offset; |
| 4471 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4472 | |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4473 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4474 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 4475 | if (p) |
| 4476 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4477 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4478 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4479 | val = bswap32(val); |
| 4480 | } |
| 4481 | #else |
| 4482 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4483 | val = bswap32(val); |
| 4484 | } |
| 4485 | #endif |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4486 | io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val); |
| 4487 | } else { |
| 4488 | unsigned long addr1; |
| 4489 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4490 | /* RAM case */ |
pbrook | 5579c7f | 2009-04-11 14:47:08 +0000 | [diff] [blame] | 4491 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4492 | switch (endian) { |
| 4493 | case DEVICE_LITTLE_ENDIAN: |
| 4494 | stl_le_p(ptr, val); |
| 4495 | break; |
| 4496 | case DEVICE_BIG_ENDIAN: |
| 4497 | stl_be_p(ptr, val); |
| 4498 | break; |
| 4499 | default: |
| 4500 | stl_p(ptr, val); |
| 4501 | break; |
| 4502 | } |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4503 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4504 | /* invalidate code */ |
| 4505 | tb_invalidate_phys_page_range(addr1, addr1 + 4, 0); |
| 4506 | /* set dirty bit */ |
Yoshiaki Tamura | f7c11b5 | 2010-03-23 16:39:53 +0900 | [diff] [blame] | 4507 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4508 | (0xff & ~CODE_DIRTY_FLAG)); |
bellard | 3a7d929 | 2005-08-21 09:26:42 +0000 | [diff] [blame] | 4509 | } |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 4510 | } |
| 4511 | } |
| 4512 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4513 | void stl_phys(target_phys_addr_t addr, uint32_t val) |
| 4514 | { |
| 4515 | stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 4516 | } |
| 4517 | |
| 4518 | void stl_le_phys(target_phys_addr_t addr, uint32_t val) |
| 4519 | { |
| 4520 | stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 4521 | } |
| 4522 | |
| 4523 | void stl_be_phys(target_phys_addr_t addr, uint32_t val) |
| 4524 | { |
| 4525 | stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 4526 | } |
| 4527 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4528 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4529 | void stb_phys(target_phys_addr_t addr, uint32_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4530 | { |
| 4531 | uint8_t v = val; |
| 4532 | cpu_physical_memory_write(addr, &v, 1); |
| 4533 | } |
| 4534 | |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4535 | /* warning: addr must be aligned */ |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4536 | static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val, |
| 4537 | enum device_endian endian) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4538 | { |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4539 | int io_index; |
| 4540 | uint8_t *ptr; |
| 4541 | unsigned long pd; |
| 4542 | PhysPageDesc *p; |
| 4543 | |
| 4544 | p = phys_page_find(addr >> TARGET_PAGE_BITS); |
| 4545 | if (!p) { |
| 4546 | pd = IO_MEM_UNASSIGNED; |
| 4547 | } else { |
| 4548 | pd = p->phys_offset; |
| 4549 | } |
| 4550 | |
| 4551 | if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) { |
| 4552 | io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1); |
| 4553 | if (p) |
| 4554 | addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset; |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4555 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 4556 | if (endian == DEVICE_LITTLE_ENDIAN) { |
| 4557 | val = bswap16(val); |
| 4558 | } |
| 4559 | #else |
| 4560 | if (endian == DEVICE_BIG_ENDIAN) { |
| 4561 | val = bswap16(val); |
| 4562 | } |
| 4563 | #endif |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4564 | io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val); |
| 4565 | } else { |
| 4566 | unsigned long addr1; |
| 4567 | addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK); |
| 4568 | /* RAM case */ |
| 4569 | ptr = qemu_get_ram_ptr(addr1); |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4570 | switch (endian) { |
| 4571 | case DEVICE_LITTLE_ENDIAN: |
| 4572 | stw_le_p(ptr, val); |
| 4573 | break; |
| 4574 | case DEVICE_BIG_ENDIAN: |
| 4575 | stw_be_p(ptr, val); |
| 4576 | break; |
| 4577 | default: |
| 4578 | stw_p(ptr, val); |
| 4579 | break; |
| 4580 | } |
Michael S. Tsirkin | 733f0b0 | 2010-04-06 14:18:19 +0300 | [diff] [blame] | 4581 | if (!cpu_physical_memory_is_dirty(addr1)) { |
| 4582 | /* invalidate code */ |
| 4583 | tb_invalidate_phys_page_range(addr1, addr1 + 2, 0); |
| 4584 | /* set dirty bit */ |
| 4585 | cpu_physical_memory_set_dirty_flags(addr1, |
| 4586 | (0xff & ~CODE_DIRTY_FLAG)); |
| 4587 | } |
| 4588 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4589 | } |
| 4590 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4591 | void stw_phys(target_phys_addr_t addr, uint32_t val) |
| 4592 | { |
| 4593 | stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN); |
| 4594 | } |
| 4595 | |
| 4596 | void stw_le_phys(target_phys_addr_t addr, uint32_t val) |
| 4597 | { |
| 4598 | stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN); |
| 4599 | } |
| 4600 | |
| 4601 | void stw_be_phys(target_phys_addr_t addr, uint32_t val) |
| 4602 | { |
| 4603 | stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN); |
| 4604 | } |
| 4605 | |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4606 | /* XXX: optimize */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4607 | void stq_phys(target_phys_addr_t addr, uint64_t val) |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4608 | { |
| 4609 | val = tswap64(val); |
Stefan Weil | 71d2b72 | 2011-03-26 21:06:56 +0100 | [diff] [blame] | 4610 | cpu_physical_memory_write(addr, &val, 8); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 4611 | } |
| 4612 | |
Alexander Graf | 1e78bcc | 2011-07-06 09:09:23 +0200 | [diff] [blame] | 4613 | void stq_le_phys(target_phys_addr_t addr, uint64_t val) |
| 4614 | { |
| 4615 | val = cpu_to_le64(val); |
| 4616 | cpu_physical_memory_write(addr, &val, 8); |
| 4617 | } |
| 4618 | |
| 4619 | void stq_be_phys(target_phys_addr_t addr, uint64_t val) |
| 4620 | { |
| 4621 | val = cpu_to_be64(val); |
| 4622 | cpu_physical_memory_write(addr, &val, 8); |
| 4623 | } |
| 4624 | |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4625 | /* virtual memory access for debug (includes writing to ROM) */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4626 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
bellard | b448f2f | 2004-02-25 23:24:04 +0000 | [diff] [blame] | 4627 | uint8_t *buf, int len, int is_write) |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4628 | { |
| 4629 | int l; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 4630 | target_phys_addr_t phys_addr; |
j_mayer | 9b3c35e | 2007-04-07 11:21:28 +0000 | [diff] [blame] | 4631 | target_ulong page; |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4632 | |
| 4633 | while (len > 0) { |
| 4634 | page = addr & TARGET_PAGE_MASK; |
| 4635 | phys_addr = cpu_get_phys_page_debug(env, page); |
| 4636 | /* if no physical page mapped, return an error */ |
| 4637 | if (phys_addr == -1) |
| 4638 | return -1; |
| 4639 | l = (page + TARGET_PAGE_SIZE) - addr; |
| 4640 | if (l > len) |
| 4641 | l = len; |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4642 | phys_addr += (addr & ~TARGET_PAGE_MASK); |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4643 | if (is_write) |
| 4644 | cpu_physical_memory_write_rom(phys_addr, buf, l); |
| 4645 | else |
aliguori | 5e2972f | 2009-03-28 17:51:36 +0000 | [diff] [blame] | 4646 | cpu_physical_memory_rw(phys_addr, buf, l, is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4647 | len -= l; |
| 4648 | buf += l; |
| 4649 | addr += l; |
| 4650 | } |
| 4651 | return 0; |
| 4652 | } |
Paul Brook | a68fe89 | 2010-03-01 00:08:59 +0000 | [diff] [blame] | 4653 | #endif |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 4654 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4655 | /* in deterministic execution mode, instructions doing device I/Os |
| 4656 | must be at the end of the TB */ |
| 4657 | void cpu_io_recompile(CPUState *env, void *retaddr) |
| 4658 | { |
| 4659 | TranslationBlock *tb; |
| 4660 | uint32_t n, cflags; |
| 4661 | target_ulong pc, cs_base; |
| 4662 | uint64_t flags; |
| 4663 | |
| 4664 | tb = tb_find_pc((unsigned long)retaddr); |
| 4665 | if (!tb) { |
| 4666 | cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", |
| 4667 | retaddr); |
| 4668 | } |
| 4669 | n = env->icount_decr.u16.low + tb->icount; |
Stefan Weil | 618ba8e | 2011-04-18 06:39:53 +0000 | [diff] [blame] | 4670 | cpu_restore_state(tb, env, (unsigned long)retaddr); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4671 | /* Calculate how many instructions had been executed before the fault |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4672 | occurred. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4673 | n = n - env->icount_decr.u16.low; |
| 4674 | /* Generate a new TB ending on the I/O insn. */ |
| 4675 | n++; |
| 4676 | /* On MIPS and SH, delay slot instructions can only be restarted if |
| 4677 | they were already the first instruction in the TB. If this is not |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4678 | the first instruction in a TB then re-execute the preceding |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4679 | branch. */ |
| 4680 | #if defined(TARGET_MIPS) |
| 4681 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { |
| 4682 | env->active_tc.PC -= 4; |
| 4683 | env->icount_decr.u16.low++; |
| 4684 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 4685 | } |
| 4686 | #elif defined(TARGET_SH4) |
| 4687 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 |
| 4688 | && n > 1) { |
| 4689 | env->pc -= 2; |
| 4690 | env->icount_decr.u16.low++; |
| 4691 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
| 4692 | } |
| 4693 | #endif |
| 4694 | /* This should never happen. */ |
| 4695 | if (n > CF_COUNT_MASK) |
| 4696 | cpu_abort(env, "TB too big during recompile"); |
| 4697 | |
| 4698 | cflags = n | CF_LAST_IO; |
| 4699 | pc = tb->pc; |
| 4700 | cs_base = tb->cs_base; |
| 4701 | flags = tb->flags; |
| 4702 | tb_phys_invalidate(tb, -1); |
| 4703 | /* FIXME: In theory this could raise an exception. In practice |
| 4704 | we have already translated the block once so it's probably ok. */ |
| 4705 | tb_gen_code(env, pc, cs_base, flags, cflags); |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 4706 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 4707 | the first in the TB) then we end up generating a whole new TB and |
| 4708 | repeating the fault, which is horribly inefficient. |
| 4709 | Better would be to execute just this insn uncached, or generate a |
| 4710 | second new TB. */ |
| 4711 | cpu_resume_from_signal(env, NULL); |
| 4712 | } |
| 4713 | |
Paul Brook | b3755a9 | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 4714 | #if !defined(CONFIG_USER_ONLY) |
| 4715 | |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4716 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4717 | { |
| 4718 | int i, target_code_size, max_target_code_size; |
| 4719 | int direct_jmp_count, direct_jmp2_count, cross_page; |
| 4720 | TranslationBlock *tb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 4721 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4722 | target_code_size = 0; |
| 4723 | max_target_code_size = 0; |
| 4724 | cross_page = 0; |
| 4725 | direct_jmp_count = 0; |
| 4726 | direct_jmp2_count = 0; |
| 4727 | for(i = 0; i < nb_tbs; i++) { |
| 4728 | tb = &tbs[i]; |
| 4729 | target_code_size += tb->size; |
| 4730 | if (tb->size > max_target_code_size) |
| 4731 | max_target_code_size = tb->size; |
| 4732 | if (tb->page_addr[1] != -1) |
| 4733 | cross_page++; |
| 4734 | if (tb->tb_next_offset[0] != 0xffff) { |
| 4735 | direct_jmp_count++; |
| 4736 | if (tb->tb_next_offset[1] != 0xffff) { |
| 4737 | direct_jmp2_count++; |
| 4738 | } |
| 4739 | } |
| 4740 | } |
| 4741 | /* XXX: avoid using doubles ? */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4742 | cpu_fprintf(f, "Translation buffer state:\n"); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4743 | cpu_fprintf(f, "gen code size %td/%ld\n", |
bellard | 26a5f13 | 2008-05-28 12:30:31 +0000 | [diff] [blame] | 4744 | code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size); |
| 4745 | cpu_fprintf(f, "TB count %d/%d\n", |
| 4746 | nb_tbs, code_gen_max_blocks); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4747 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4748 | nb_tbs ? target_code_size / nb_tbs : 0, |
| 4749 | max_target_code_size); |
Stefan Weil | 055403b | 2010-10-22 23:03:32 +0200 | [diff] [blame] | 4750 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4751 | nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0, |
| 4752 | target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4753 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", |
| 4754 | cross_page, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4755 | nb_tbs ? (cross_page * 100) / nb_tbs : 0); |
| 4756 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 4757 | direct_jmp_count, |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4758 | nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0, |
| 4759 | direct_jmp2_count, |
| 4760 | nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 4761 | cpu_fprintf(f, "\nStatistics:\n"); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4762 | cpu_fprintf(f, "TB flush count %d\n", tb_flush_count); |
| 4763 | cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count); |
| 4764 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
bellard | b67d9a5 | 2008-05-23 09:57:34 +0000 | [diff] [blame] | 4765 | tcg_dump_info(f, cpu_fprintf); |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 4766 | } |
| 4767 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4768 | #define MMUSUFFIX _cmmu |
Blue Swirl | 3917149 | 2011-09-21 18:13:16 +0000 | [diff] [blame] | 4769 | #undef GETPC |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4770 | #define GETPC() NULL |
| 4771 | #define env cpu_single_env |
bellard | b769d8f | 2004-10-03 15:07:13 +0000 | [diff] [blame] | 4772 | #define SOFTMMU_CODE_ACCESS |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 4773 | |
| 4774 | #define SHIFT 0 |
| 4775 | #include "softmmu_template.h" |
| 4776 | |
| 4777 | #define SHIFT 1 |
| 4778 | #include "softmmu_template.h" |
| 4779 | |
| 4780 | #define SHIFT 2 |
| 4781 | #include "softmmu_template.h" |
| 4782 | |
| 4783 | #define SHIFT 3 |
| 4784 | #include "softmmu_template.h" |
| 4785 | |
| 4786 | #undef env |
| 4787 | |
| 4788 | #endif |